Low-voltage CMOS Process Research Articles

Design of Dual-Configuration Dual-Mode Stimulator in Low-Voltage CMOS Process for Neuro-Modulation.

A dual-configuration dual-mode stimulator for neuro-modulation is proposed and designed. All the electrical stimulation patterns that frequently used for neuro-modulation can be generated by the proposed stimulator chip. Dual-configuration represents the bipolar or monopolar structure, meanwhile dual-mode stands for the current or voltage output. No matter what stimulation circumstance is chosen, biphasic or monophasic waveforms can be fully supported by the proposed stimulator chip. The stimulator chip with 4 stimulation channels has been fabricated in 0.18-μm 1.8-V/3.3-V low-voltage CMOS process with common grounded p-type substrate, which is suitable for SoC integration. The design has conquered the overstress and reliability issues in the low-voltage transistors under the negative voltage power domain. Each channel in the stimulator chip only occupies the silicon area of 0.052 mm2, and the maximum output level of stimulus amplitude is up to ±3.6 mA and ±3.6 V. With the built-in discharge function, bio-safety concern of unbalanced charge in neuro-stimulation can be dealt with properly. Moreover, the proposed stimulator chip has been applied on both imitation measurement and in-vivo animal test successfully.

A Fully Integrated, Power-Efficient, 0.07-2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process.

This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of . Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode–tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology’s nominal supply, (2) residual charge—without passive discharging phase—was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.

Combined In-Pixel Linear and Single-Photon Avalanche Diode Operation With Integrated Biasing for Wide-Dynamic-Range Optical Sensing

This article presents a fully integrated, wide linear dynamic range (DR) optical sensor array combining linear and single-photon avalanche diode (SPAD) operation within each pixel. A pulse-counting readout scheme provides in-pixel digitization in an area-efficient manner for both the operation modes, enabling fully parallel measurement across the array. The proposed dual-mode optical sensor array alternately requires high-voltage (10–20 V) and low-voltage supply (2–5 V) for reverse bias of the photodiodes, which is provided by a reconfigurable, closed-loop high-voltage charge pump in the same substrate. An $8\times 8$ array architecture along with the dual-mode bias generator is fabricated in a general purpose 180-nm CMOS process and demonstrates 129-dB DR while maintaining linear photoresponse operating with a dual-mode frame rate of 20 Hz. We present a pixel design methodology for implementing a dual-mode optical sensor scalable to an array format, as well as high-voltage dc–dc conversion in a low-voltage CMOS process.

A regulated multiple-output high-voltage charge pump IC for implantable neural stimulators

In this paper, a single-input multiple-output high-voltage charge pump integrated circuit (IC) for neural stimulation applications is presented. The proposed circuit, implemented using 0.18-μm standard low-voltage CMOS process, reliably generates three high-voltage outputs of 12.8 V, 9.6 V, and 6.4 V from a single 2.8 V-input source while regulating the output with load current up to 1 mA. In addition, an input voltage modulated regulation scheme is employed for good efficiency and regulation performance. The designed IC, which includes three charge pump cores and regulation circuits, occupies 0.8 mm2 of core die area.

An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process

A wide-output, power-efficient, high-voltage charge pump with a variable number of stages is proposed and realized in a $0.18~\mu \text{m}$ 1.8 V/3.3 V CMOS process. The proposed stage selection circuit changes the node voltages in the charge pump circuit in a domino effect to ensure that the maximum voltages across the terminals of each transistor are kept within the normal supply voltage ( $\text{V}_{\mathrm {DD}}$ ). The stage selection circuit is able to bypass or activate each stage of the charge pump. Experimental results indicate that the proposed charge pump provides a wide-output voltage range: 3.3–12.6 V from a 3.3 V input source. A peak efficiency of 70% was reached in the charge pump at a current loading of 3.5 mA. By selecting the optimal number of active stages, the overall power efficiencies can be greater than 60% under the output voltages of 4.8 V, 8.1 V, and 10.8 V, respectively. By optimizing the number of active stages, an increase of up to 35% power efficiency can be gained. The proposed stage selection circuit is applicable to other on-chip wide-output charge-pumps.

A High-Voltage Generation Charge-Pump IC Using Input Voltage Modulated Regulation for Neural Implant Devices

This brief presents a high-voltage generation charge pump integrated circuit (IC) with a novel regulation scheme for neural stimulation applications. Instead of using a widely used pulse frequency modulation approach with a variable clock frequency for regulation, an input voltage modulated regulation with a low drop-out regulator at the input of the feedforward path is used to maintain the charge pump output voltage with varying load current between 10 μA to 1 mA. The proposed charge pump IC, implemented with 0.18-μm standard low-voltage CMOS process, reliably generates 12.8-V output voltage from a 2.8-V input and achieves more than 80% power efficiency at 1 mA load condition. The proposed IC occupies 0.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of core die area.

Electron Multiplying Low-Voltage CCD With Increased Gain

Novel designs for the gain elements in electron multiplying (EM) charge-coupled devices (CCDs) have been implemented in a device manufactured in a low-voltage CMOS process. Derived with help from TCAD simulations, the designs employ modified gate geometries in order to significantly increase the EM gain over traditional structures. Two new EM elements have been demonstrated with an order of magnitude higher gain than the typical rectangular gate designs, achieved over 100 amplifying stages and without an increase in the electric field. The principles presented in this paper can be used in CMOS and CCD imagers employing electron multiplication in order to boost the gain and reduce undesirable effects such as clock-induced charge generation and gain aging.

Statically triggered 3×VDD-Tolerant ESD detection circuit in a 90-nm low-voltage CMOS process

A statically triggered 3 × VDD-tolerant electrostatic discharge (ESD)detection circuit using only low-voltage devices in a 90-nm 1.2-V CMOS process is proposed. A bias circuit is added to enhance the ESD trigger efficiency. Since no NMOSFETs are used, it is unnecessary to use any deep N-well even though the circuit can sustain 3 × VDD stress. The proposed detection circuit can generate a 38 mA current to turn on the substrate-triggered silicon controlled rectifier (SCR) during ESD events. Under normal operating conditions, all the devices are free from over-stress voltage. Without the gate leakage current of a MOS capacitor, the leakage current is only 63 nA under 3 × VDD stress at 25 °C. The simulation result shows the proposed circuit can be successfully used for a 3 × VDD-tolerant I/O buffer.

Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs

This paper presents design analysis and insights for a new continuous-time input pipeline (CTIP) analog-to-digital converter (ADC) architecture that has enhanced bandwidth. An all-pass filter-based analog delay in the signal path allows bandwidth extension to Nyquist signal bandwidths. A resetting integrator gain stage provides a signal path delay helping to increase the bandwidth while reducing the power cost. The noise filtering property of the resetting integrator gain stage preserves the medium resistive input benefit of CTIP ADCs. The resetting integrator allows the architecture to be implemented with a feedforward compensated op-amp using low-voltage CMOS processes. This paper has been verified by simulation results of a CTIP ADC with 1.2-V supply voltage designed in TSMC's 65-nm CMOS technology.

Resistor-Triggered SCR Device for ESD Protection in High-Speed I/O Interface Circuits

In this letter, an on-chip electrostatic discharge (ESD) protection device was proposed for high-speed I/O interface circuits. A resistor-triggered silicon-controlled rectifier device with improved performance was designed and investigated in a nanoscale CMOS process. As verified in a 0.18- $\mu \text{m}$ CMOS process, the proposed design exhibits a lower clamping voltage and low enough overshoot voltage during ESD stress conditions, and lower parasitic capacitance and low enough leakage current during normal circuit operating conditions. Therefore, the proposed design is suitable for ESD protection of high-speed circuits in low-voltage CMOS processes.

Regulated Charge Pump With New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process

A regulated cross-couple charge pump with new charging current smoothing technique is proposed and verified in a 0.18- $\mu \text {m}~1.8$ -V/3.3-V CMOS process. The transient behaviors of 3-stage cross-couple charge pump and the expressions for the charging current are described in detail. The experiment results show that the charging current ripples are reduced by a factor of three through using the proposed new clocking scheme. The voltage ripples in the power supply line, which is connected with the charge pump input, are also smoothed greatly as the filter circuit does. The proposed scheme is used to decrease the smoothing capacitance in the power line of charge pump for reducing the size of implantable devices in biomedical application. In addition, the power efficiency is improved. The proposed cross-couple charge pump can provide 10.5-V output voltage with 3.5-mA output current, and the power efficiency of the charge pump can be up to 69%.

A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS

This paper presents a 44.2-mW 3.2-GHz 3-port register file (RF) that demonstrates measured operation from 1.2 V down to 0.4 V. The 32-entry× 32-bit/word 2-read/1-write RF is fabricated in TSMC 65-nm low-power low threshold voltage (low-V t ) CMOS process. A four-transistor read port is presented that permits the design of low-capacitance dynamic local bitlines (LBLs). Switching power in the LBLs and the LBL precharge buffer is thereby reduced. Based on extensive simulation results, the proposed read port is recommended for use in wide-worded RFs, which employ a wide dynamic-OR structure at the LBL stage. The proposed RF outperforms the conventional design in terms of power consumption for frequencies exceeding 3-GHz. The read port exploits intrinsic capacitive coupling to achieve robust operation over a wide voltage range. The architecture of the read port simultaneously enhances robustness of the dynamic bitline by 58.8% as compared to the conventional low-V t bitline.

A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process.

This paper presents a 4 × VDD neuro-stimulator in a 0.18- μm 1.8 V/3.3 V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent transistors from the electrical overstress and gate-oxide reliability issue. A high-voltage-tolerant level shifter with power-on protection is used to drive the neuro-stimulator The reliability measurement of up to 100 million periodic cycles with 3000- μA biphasic stimulations in 12-V power supply has verified that the proposed neuro-stimulator is robust. Precise charge balance is achieved by using a novel current memory cell with the dual calibration loops and leakage current compensation. The charge mismatch is down to 0.25% over all the stimulus current ranges (200-300 μA) The residual average dc current is less than 6.6 nA after shorting operation.

Improved Body Effect and Analog Characteristics of n-Channel MOSFET With Lateral Asymmetric Substrate Doping

An n-channel MOSFET with lateral asymmetric substrate doping (LASD) is presented in this paper. The proposed LASD device has a p-well on the source side and a p-substrate on the drain side. The LASD MOSFET was designed by the simple p-well layout approach and fabricated using the 0.18 \(\mu \) m standard low-voltage CMOS process without any process modification. The experimental measurements showed the improved analog performances of the LASD MOSFET: higher transconductance (g \(_{\mathbf {m}}\) ), lower drain conductance (g \(_{{\mathrm {ds}}}\) ), lower drain induced barrier lowering, higher transconductance generation factor (g \(_{{\mathrm {m}}}/{\mathrm I}_{{\mathrm {D}}}\) ), and higher Early voltage (V \(_{{\mathrm {EA}}}\) ). In addition, the LASD device showed strong body-effect immunity: smaller V \(_{{\mathrm {T}}}\) shift according to body bias and lower body bias sensitivity factor (g \(_{{\mathrm {mb}}}/{\mathrm g}_{{\mathrm {m}}}\) ).

ESD Protection Device With Dual-Polarity Conduction and High Blocking Voltage Realized in CMOS Process

Electrostatic discharge (ESD) protection devices fabricated in a low-voltage CMOS process for communication interface applications typically provide relatively small blocking voltage, thus limiting the interface operating voltage range for which the ESD device can be used. This letter introduces a CMOS-based silicon controlled rectifier with a large blocking voltage beyond ±20 V and a high trigger current. Such a high blocking voltage is achieved by selectively defining native-buffer regions in critical blocking junctions of the device. Experimental characterization of the ESD robustness and standing operation are presented to validate the new device for low capacitance, high-voltage-tolerant communication interface ESD protection applications.

Design of high-voltage-tolerant stimulus driver with adaptive loading consideration to suppress epileptic seizure in a 0.18-μm CMOS process

A novel design of high-voltage-tolerant stimulus driver for epileptic seizure suppression with low power design and adaptive loading consideration is proposed in this work. The proposed design can deliver the required stimulus current within a specific range of loading impedance. Besides, this design in 0.18-μm low-voltage CMOS process can be operated with high supply voltage (VCC) of 5–10 V without using the high-voltage transistors, and the process steps of high-voltage transistors can be reduced. The proposed design can be further integrated for an electronic epilepsy prosthetic system-on-chip.

Voltage Spikes in Integrated CMOS Buck DC-DC Converters: Analysis for Resonant and Hard Switching Topologies

Abstract In an integrated DC-DC converter, voltage spikes are generated during the commutation of the power switches and they may cause the device malfunction if its magnitude is excessive. That occurs when, targeting high efficiency, very fast switching is implemented in a low voltage CMOS process, with higher impact when the converter output current is high. These conditions that cause spikes of significant magnitude, in the order of Volts, are common in modern DC-DC converters for portable equipment powered by batteries. Magnitude limitation of voltage spikes in hard switching converters is a hot research topic and the known solutions are surveyed here. Resonant switches topologies are frequently mentioned as an alternative to overcome voltage spikes in a DC-DC converter, but generally this solution is dismissed in integrated implementations. This paper investigates if the resonant topologies are an effective solution to overcome voltage spikes during the switches commutation in a buck converter. Two buck DC-DC converters using resonant switches are analyzed, namely a QR-ZCS topology and a QSW- ZVS topology. The analysis proceeds in two steps that can be easily applied to other resonant converters. Results show that resonant DC-DC converters also generate voltage spikes which magnitude is sometimes higher than that generated in a hard switching converter, and is superimposed to the overvoltage occurring in the resonant phase. This is an important result since resonant, or soft switching, converters are occasionally mistakenly mentioned as free of voltage spikes.

A Reconfigurable and Power-Scalable 10–12 Bit 0.4–44 MS/s Pipelined ADC With 0.35–0.5 pJ/Step in 1.2 V 90 nm Digital CMOS

A pipelined ADC, reconfigurable over bandwidths of 0.2-22 MHz (sampling frequencies of 0.4-44 MS/s) and resolutions of 10-12 bits, is described for applications in multi-standard wireless terminals. Fabricated in a 1.2-V 90-nm digital CMOS technology, this ADC achieves low power (figure-of-merit of FOM=0.35 to 0.5 pJ per A/D conversion step) over its full bandwidth-resolution range. Accordingly, compared to state-of-the-art power-efficient reconfigurable pipelined ADCs, this ADC provides a larger bandwidth-resolution reconfigurability space, while maintaining a highly competitive FOM over this entire space. To achieve such low-power performance in a low-voltage nanometer CMOS process, this work utilizes: (1) a current-scalable frequency-compensation technique to design low-power current-scalable two-stage opamps; (2) a switched-capacitor technique to design dynamic comparators with low input capacitance (input-loading effect); and (3) a low-power digital background gain-calibration technique. The large bandwidth and resolution reconfigurability ranges are achieved using current-scaling and stage-bypass techniques, respectively.

Multiple-Valued Pulse-Position Modulation Techniques for Efficient Data Transmission

This paper proposes multiple-valued pulse-position modulation (MVPPM) techniques toachieve efficient data transmission in VLSI systems. The MVPPM coding employs 2-dimensional informationrepresentation in both time and amplitude domain to increase data rates. This time-domaininformation processing uses timing resolution, and therefore fits well with advanced high-speed lowvoltageCMOS processes. An 8-valued MVPPM transceiver is designed and simulated using SPICE todemonstrate the capability of compensating for deterioration of signals caused by interconnections.

New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process

A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with consideration of the gate leakage issue has been proposed and verified in a 65-nm low-voltage CMOS process. Consisting of the new low-leakage ESD-detection circuit and the ESD clamp device of a substrate-triggered silicon-controlled rectifier, the new proposed power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has a very low leakage current of only 116 nA at room temperature (25°C ) under the power-supply voltage of 1 V. Moreover, the new proposed power-rail ESD clamp circuit can achieve ESD robustness of over 8 kV, 800 V, and over 2 kV in human-body-model, machine-model, and charged-device-model ESD tests, respectively.