Low Threshold Voltage Transistors Research Articles

Dual Threshold Voltage Pseudo Domino Logic - Based Buffer with Reduced Power

In this paper, a new technique of power reduction in pseudo domino logic-based buffer is proposed with dual threshold voltage. The proposed method employs the dual threshold voltage technique to reduce the power. During the precharge stage, we have used the high threshold voltage transistor in the non-critical path of the circuit, to reduce the leakage current due to which the average power dissipation is minimized. In critical path, low threshold voltage transistors are used. The low threshold voltage transistors are used in evaluation stage, for the performance enhancement of the circuit. Keeper circuit is used with two PMOS transistor which helps in maintaining voltage of dynamic node and improves the noise immunity and speed of the circuit. Also, a NMOS transistor, which is operated by the dynamic node is used which minimizes the leakage by creating a stacking impact. In addition, the clock inverter is enabled via low voltage NMOS which significantly reduces the current in the inverter due to direct connection between the supply voltage (Vdd) to ground.

High Gain, Low Noise and Power Transimpedance Amplifier Based on Second Generation Voltage Conveyor in 65 nm CMOS Technology.

A transimpedance amplifier (TIA) based on a voltage conveyor structure designed for high gain, low noise, low distortion, and low power consumption is presented in this work. Following a second-generation voltage conveyor topology, the current and voltage blocks are a regulated cascode amplifier and a down converter buffer, respectively. The proposed voltage buffer is designed for low distortion and low power consumption, whereas the regulated cascode is designed for low noise and high gain. The resulting TIA was fabricated in 65 nm CMOS technology for logic and mixed-mode designs, using low-threshold voltage transistors and a supply voltage of ±1.2 V. It exhibited a 52 dBΩ transimpedance gain and a 1.1 GHz bandwidth, consuming 55.3 mW using a ±1.2 V supply. Our preamplifier stage, based on a regulated cascode, was designed considering detector capacitance, bonding wire, and packaging capacitance. The voltage buffer was designed for low-power consumption and low distortion. The measured input-referred noise of the TIA was 22 pA/√Hz. The obtained total harmonic distortion of the TIA was close to 5%. In addition, the group delay is constant for the considered bandwidth. Comparisons against published results in terms of area (A), power consumption (P), bandwidth (BW), transimpedance gain (G), and noise (N) are were performed. Both figures of merit FoMs—the ratio √ (G × BW) and P × A—and FoM/N values demostrated the advantages of the proposed approach.

2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations

A 2[Formula: see text]VDD CMOS output buffer with process, voltage and leakage (PVL) detection mechanism is proposed such that slew rate is auto-adjusted to reduce the variations at different corners. To boost the driving current, low threshold voltage transistors are used instead of devices with typical threshold voltage in the driving transistor of output stage. More importantly, to prevent large leakage of those large low threshold voltage devices, leakage detection resistors are added at the gates of the always-on low threshold voltage transistors to clamp the leakage. The static power consumption is reduced when it is not activated. Another feature of the proposed design is that the gate-oxide leakage is also reduced by lengthening the driving transistors. Besides, all biases in the proposed design are generated from bandgap circuits such that not only is the variation caused by temperature drifting reduced, the area overhead and power dissipation are also minimized. The proposed design is carried out by using 28-nm CMOS process. The data rate proved by physical measurement is proved to be 2.0[Formula: see text]GHz given 1.8/1.05[Formula: see text]V supply voltage, namely, VDD or 2[Formula: see text]VDD, when the proposed PVL detection as well as the compensation circuitry are activated.

High performance CMOS level up shifter with full–scale 1.2 V output voltage

This paper introduces a very low static current CMOS level up shifter for low voltage single supply and high performance. The proposed low to high voltage level shifter is implemented using low threshold voltage transistors in 65 nm CMOS technology and based on differential topology. The shifter circuit was designed to be functional for an input voltage from 0.45 up to 1.2 V. Driving a 450 fF of capacitive load, the shifter's energy–delay product (EPD) is a 54% lower than a similar single supply level up shifter. Post–layout simulations, for every technological corner, temperature range from 25 up to 125 °C, operating input voltages and output capacitive loads (maximum of 740 fF), demonstrate the topology is fully functional without any impact on the static power consumption and the operating frequency of 500 MHz. Monte Carlo analysis shows the robustness of the proposed shifter within a 3σ device mismatch.

A loadless 6T SRAM cell for sub- & near- threshold operation implemented in 28 nm FD-SOI CMOS technology

Most ultra low power SRAM cells operating in the sub and near threshold region deploy 8 or more transistors per storage cell to ensure stability. In this paper we propose and design a low voltage, differential write, single ended read memory cell that consists of a total of 6 transistors. The innovative idea is to bring the loadless 4-transistor latch into the realm of low voltage memory cells by exploiting features of the 28 nm FDSOI Process and by adding a 2-transistor readbuffer with a footer line. Stand-alone and on a system level, the cell is stable during read, write and hold operations and it has great write-ability due to its differential write and loadless nature. The single NWELL option in 28 nm FD-SOI allows the loadless core to have minimal device widths while greatly improving the time it takes to evaluate the read bit-line. The cell has, in this paper, been used in a 128 kb (217) SRAM in a 16 block configuration exploring 3 different types of logic libraries for the peripheral logic of the system. Depending on the application, the IO-peripheral logic may be implemented using either high threshold voltage transistors or low threshold voltage transistors in where the power consumption of the 128 kb system was found to range from 1.31 µW to 71.09 µW, the maximum operational frequency lies within 1.87 MHz and 14.97 MHz while the read energy varies from 13.08 to 75.21 fJ/operation/bit for a supply voltage of 350 mV. The minimum retention voltage of the loadless SRAM cell is found to be 230 mV covering 5σ of variation with Monte Carlo simulations.

High performance single supply CMOS 0.45–1 V input to 1.1 V output level up shifter

This paper presents the design of a single supply CMOS level up shifter for low voltage and low energy consumption. The proposed voltage level converter is implemented using low threshold voltage transistors in 65nm CMOS technology. The shifter circuit designed for an output of 1.1V was verified, through the post–layout simulation, to be functional for an input voltage range of 0.45–1V. We compare our work with several other level shifters. With a 50fF of capacitive load, the shifter's energy–delay product is a 40% lower than a similar single supply level up shifter. Moreover, the measurements on the fabricated dies show that the proposed structure is able to drive a double capacitive load of up to 105fF, without any impact on the static power consumption. Monte–Carlo analysis demonstrates the robustness of the proposed shifter within a 3σ device mismatch.

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

This paper presents a new nine-transistor (9T) SRAM cell operating in the subthreshold region. In the proposed 9T SRAM cell, a suitable read operation is provided by suppressing the drain-induced barrier lowering effect and controlling the body---source voltage dynamically. Proper usage of low-threshold voltage (L-$$V_{\mathrm{t}}$$Vt) transistors in the proposed design helps to reduce the read access time and enhance the reliability in the subthreshold region. In the proposed cell, a common bit-line is used in the read and write operations. This design leads to a larger write margin without using extra circuits. The simulation results at 90 nm CMOS technology demonstrate a qualified performance of the proposed SRAM cell in terms of power dissipation, power---delay product, write margin, read access time and sensitivity to process, voltage and temperature variations as compared to the other most efficient low-voltage SRAM cells previously presented in the literature.

Design of Transformer-Based Boost Converter for High Internal Resistance Energy Harvesting Sources With 21 mV Self-Startup Voltage and 74% Power Efficiency

Thin-film thermoelectric generators (TEG) or graphene-based microbial fuel cells (MFC) are emerging energy harvesting sources with promising power density and sustainability. Nevertheless, conventional transformer-based boost converters commonly used to achieve autonomous low voltage startup encounter low efficiency and potential startup problems with these novel power sources due to their high internal resistance. In this paper, an improved design of transformer-based boost converter addressing these issues is demonstrated with prototype chip fabricated using a standard 0.13 μm CMOS process. The self-start oscillation does not rely on the conventional LC resonant principle, but instead is dependent on the MOS transistor's active-over-leakage current ratio and the mutual coupling between the two identical transformer coils. Circuit design techniques to regulate output voltage and to track system's maximum power point (MPP) of this boost converter are presented. Measurement results confirmed that the proposed circuit works with either low threshold voltage or native MOS transistors. It needs minimum self-startup voltage of 21 mV (at 5.8 μW input power) and minimum startup power of 1.3 μW (at 35 mV input voltage) respectively. The maximum output power is 2 mW and peak power conversion efficiency is 74% at a regulated output voltage of 1 V.

Design of Low Leakage Multi Threshold (Vth) CMOS Level Shifter

In this paper, a low leakage multi V th level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using MTCMOS technique and sleepy keeper. MTCMOS is an effective circuit level technique that improves the performance and design by utilizing both low and high threshold voltage transistors. Leakage power dissipation has become an overriding concern for VLSI circuit designers. In this a “sleepy keeper” approach is preferred which reduces the leakage current while saving exact logic state. The new low-power level shifter using sleepy keeper is compared with the previous work for different values of the lower supply voltage. When the circuits are individually analyzed for power consumption at 45nm CMOS technology, the new level shifter offer significant power savings up to 37% as compared to the previous work. Alternatively, when the circuits are individually analyzed for minimum propagation delay, speed is enhanced by up to 48% with our approach to the circuit. All the simulation results are based on 45nm CMOS technology and simulated in cadence tool. DOI: http://dx.doi.org/10.11591/ijece.v3i5.3166

A 1V Low Voltage 4GHz Phase-Switching Dual-Modulus Prescaler in 0.18μm CMOS

A 1V low-voltage phase switching dual-modulus prescaler in standard 0.18μm TSMC RF CMOS technology is presented. Forward phase switching technique is used to prevent glitches. Low threshold voltage transistors are applied to overcome low voltage supply. Circuit techniques are used to improve driving ability and ensure reliability. The post simulation results show the prescaler operates correctly from 0.8GHz to 4GHz with power dissipation of 2.059mW at a maximum input frequency of 4GHz from 1V power supply.

Low Threshold Voltage Transistors Based on Individual Single‐Crystalline Submicrometer‐Sized Ribbons of Copper Phthalocyanine

Single-crystalline submicrometer-sized ribbons of copper phthalocyanine (CuPc) have been synthesized (see Figure). Organic field-effect transistors (OFETs) fabricated using individual ribbons of CuPc exhibit high mobilities and low threshold voltages. These characteristics are highly reproducible and stable, indicating the high quality of the transistors. Moreover, CuPc submicrometer-sized ribbons show excellent flexibility, which may lead to their application in flexible electronics. Supporting information for this article is available on the WWW under http://www.wiley-vch.de/contents/jc_2089/2006/c1654_s.pdf or from the author. Please note: The publisher is not responsible for the content or functionality of any supporting information supplied by the authors. Any queries (other than missing content) should be directed to the corresponding author for the article.

An sram design using dual threshold voltage transistors and low-power quenchers

Static random access memories (SRAM) are widely used in computer systems and many portable devices. In this paper, we propose an SRAM cell with dual threshold voltage transistors. Low threshold voltage transistors are mainly used in driving bit-lines while high threshold voltage transistors are used in latching data voltages. The advantages of dual threshold voltage transistors can be used to reduce the access time and maintain data retention at the same time. Also, the unwanted oscillation of the output bitlines of memories caused by large currents in bitlines is reduced by adding two back-to-back quenchers. The proposed quenchers not only prevent oscillation, but also reduce the idle power consumption when the memory cells are not activated by wordline signals. Meanwhile, a large noise margin is provided such that the gain of the sense amplifier will not be reduced to avoid the oscillation. Hence, high-speed and low-power readout operations of the SRAMs are feasible.