An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

Abstract

This paper presents a new nine-transistor (9T) SRAM cell operating in the subthreshold region. In the proposed 9T SRAM cell, a suitable read operation is provided by suppressing the drain-induced barrier lowering effect and controlling the body---source voltage dynamically. Proper usage of low-threshold voltage (L-$$V_{\mathrm{t}}$$Vt) transistors in the proposed design helps to reduce the read access time and enhance the reliability in the subthreshold region. In the proposed cell, a common bit-line is used in the read and write operations. This design leads to a larger write margin without using extra circuits. The simulation results at 90 nm CMOS technology demonstrate a qualified performance of the proposed SRAM cell in terms of power dissipation, power---delay product, write margin, read access time and sensitivity to process, voltage and temperature variations as compared to the other most efficient low-voltage SRAM cells previously presented in the literature.