Low-temperature Furnace Annealing Research Articles

Leakage current analysis of silicon diode with anode activated by furnace annealing or laser annealing using deep level transient spectroscopy

Silicon P-i-N diodes with a p+ region in the anode—where boron atoms are implanted and activated with relatively low-temperature furnace annealing (FA) or high-temperature laser annealing (LA)—show a large difference between the leakage currents of the diode samples activated using FA and LA. In this paper, in order to clarify the cause of the difference in leakage current, the generation current and diffusion current are verified. For estimating the generation current, the trap level was analyzed by deep level transient spectroscopy (DLTS) in a wide bias range of +0.3 V to −160 V, which corresponds to a depletion region width of 0 µm–37 µm, and trap density depth profiles are analyzed using DLTS. The DLTS analysis shows that the trap density is relatively uniform in the FA sample; however, the LA sample has a lower trap density near the p+ region of the anode. The leakage current of the diodes is calculated using the trap density profiles based on the leakage current model that includes generation and diffusion currents. The calculated and measured leakage currents are compared, and the relationship between the trap density and the leakage current is investigated. The reverse bias dependence of the calculated leakage current corresponds with the measured value for the LA sample, which implies that the trap density in the n-substrate obtained by DLTS can explain the measured leakage current well. For the FA sample, the measured leakage current is larger than the calculated value in the high reverse bias region. This suggests that there are large amounts of inactivated boron in the p+ region of the anode of the FA sample because of the low activation temperature. Only a few parts of the inactivated boron are believed to form a deep energy level trap that increases the generation leakage current. In order to reduce the leakage current of the P-i-N diode, it is effective to increase the activation rate of boron in the anode p+ region. By applying the LA method to a reverse-blocking insulated gate bipolar transistor with a built-in P-i-N diode on the collector side, the reverse leakage current can be reduced, and the operating temperature can be improved.

Deep level transient spectroscopic analysis of p/n junction implanted with boron in n-type silicon substrate

For P-i-N diodes implanted and activated with boron ions into a highly-resistive n-type Si substrate, it is found that there is a large difference in the leakage current between relatively low temperature furnace annealing (FA) and high temperature laser annealing (LA) for activation of the p-layer. Since electron trap levels in the n-type Si substrate is supposed to be affected, we report on Deep Level Transient Spectroscopy (DLTS) measurement results investigating what kinds of trap levels are formed. As a result, three kinds of electron trap levels are confirmed in the region of 1–4 μm from the p-n junction. Each DLTS peak intensity of the LA sample is smaller than that of the FA sample. In particular, with respect to the trap level which is the closest to the silicon band gap center most affecting the reverse leakage current, it was not detected in LA. It is considered that the electron trap levels are decreased due to the thermal energy of LA. On the other hand, four kinds of trap levels are confirmed in the region of 38–44 μm from the p-n junction and the DLTS peak intensities of FA and LA are almost the same, considering that the thermal energy of LA has not reached this area. The large difference between the reverse leakage current of FA and LA is considered to be affected by the deep trap level estimated to be the interstitial boron.

Effects of furnace annealing and hot pressing on the properties of SZO thin films and on the characteristics of SZO-TFTs

Silicon zinc oxide (SZO) thin films were deposited via co-sputtering, while thin-film transistors (TFTfs) with the SZO film as the active layer were fabricated with a bottom gate configuration. Two kinds of post-treatment, furnace annealing and hot pressing, were carried out on the deposited SZO films. The effects of the post-treatment on the crystalline structure, chemical bond, surface roughness, and optical transmittance of the deposited SZO TFTs were analyzed as functions of the post-treatment conditions that were used. It was observed from the X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS) results that the structure of the SZO film became amorphous and the amount of Si-O bonds in the SZO film drastically increased after low-temperature furnace annealing. The on-off current ratio was 1.35× 108 for the TFT after furnace annealing (200°C) and 1.93× 108 for the TFT after hot-pressing (200°C, 2MPa), while that of the as-deposited SZO-TFT was 3.16×106. The experiment results showed that the hot pressing method would be preferable because it could improve the electrical characteristics of the SZO-TFTs, yielding similar results from the case where furnace annealing for about 60min was carried out, in spite of the short process time (about 30s) of the hot pressing method.

Study of ultra-shallow p +n junctions formed by excimer laser annealing

Excellent ultra-shallow p +n junctions have been formed by thermally treating the BF 2 +-implanted Si samples by excimer laser annealing (ELA) at 300–400 mJ cm −2 with post low-temperature long-time furnace annealing (FA) at 600 °C. A junction with a leakage current density lower than 20 nA cm −2 and a sheet resistance smaller than 200 Ω □ −1 can be well achieved. No considerable dopant diffusion is observed by using this low-thermal-budget annealing process. However, by simply using the ELA treatment at 300–400 mJ cm −2, the resultant junction shows a leakage current density as high as 10 4 nA cm −2 and a peripheral leakage current density of 10 3 nA cm −1. The large junction leakage is primarily due to the leakage current generated within the junction region near the local-oxidation-of-silicon (LOCOS) edge, and which is substantially caused by the ELA treatment. The large peripheral junction leakage current density can be significantly reduced to be about 0.2 nA cm −1 after a post low-temperature FA treatment at 600 °C. As a result, the scheme that employs ELA treatment with post low-temperature FA treatment would be efficient for forming excellent ultra-shallow p +n junctions at low thermal budget.

Excimer UV-Light Irradiation Effects on the Initial Formation Process of Implanted Luminescent Si Nanocrystals

Si ion implantation was widely used to synthesize specimens of SiO2 containing supersaturated Si and subsequent high temperature annealing induces the formation of embedded luminescent Si nanocrystals. In this work, the potentialities of excimer UV-light (172 nm, 7.2 eV) irradiation and rapid thermal annealing (RTA) to enhance the photoluminescence and achieve low temperature (below 1000 ℃) formation of Si nanocrystals have been investigated. The Si ions were introduced at acceleration energy of 180 keV to fluence of 7.5 x 1016 ions/cm2. The implanted samples were subsequently irradiated with a excimer-UV lamp. After the process, the samples were rapidly thermal annealed before furnace annealing (FA). Photoluminescence spectra were measured at various stages at the process. We found that the luminescence intensity is strongly enhanced with excimer-UV irradiation and RTA prior to conventional FA at 1050 ℃. Moreover, effective visible photoluminescence is found to be observed even after FA at 900 ℃, only for specimens treated with excimer-UV lamp and RTA, prior to a low temperature FA process. Based on our experimental results, we discuss the effects of excimer-UV lamp irradiation and RTA process on the luminescence.

Low temperature formation of luminescent Si nanocrystals with combined process of excimer UV-light irradiation and RTA

Si ion implantation was widely used to synthesize specimens of SiO2 containing supersaturated Si and subsequent high temperature annealing induces the formation of embedded luminescent Si nanocrystals. In this work, the potentialities of excimer UV-light (172nm, 7.2eV) irradiation and rapid thermal annealing (RTA) to achieve low temperature (below 1000°C) formation of luminescent Si nanocrystals in SiO2 have been investigated. The Si ions were introduced at acceleration energy of 180keV to fluences of 7.5×1016 and 1.5×1017ions/cm2. The implanted samples were subsequently irradiated with an excimer-UV lamp for 2h. After the process, the samples were rapidly thermal annealed at 1050°C for 5min before furnace annealing (FA) at 900°C. Photoluminescence spectra were measured at various stages at the process. Effective visible photoluminescence is found to be observed even after FA at 900°C, only for specimens treated with excimer-UV lamp and RTA, prior to a low temperature FA process. Based on our experimental results, we discuss the mechanism for the initial formation process of the luminescent Si nanocrystals in SiO2, together with the effects with excimer lamp irradiation and RTA process on the luminescence.

Formation and Characterization of NiSi-Silicided n+p Shallow Junctions

NiSi-silicided n+p shallow junctions are fabricated by P+/F+ dual implantation into/through a thin NiSi silicide layer followed by low-temperature furnace annealing. The incorporation of fluorine atoms in the 61-nm-thick NiSi film retards film agglomeration, making the film stable up to 750 °C for 90 min. A forward ideality factor of 1.08 and a reverse bias current density (at 5 V) of 0.7 nA/cm2 can be attained for the NiSi (61 nm)/n+p junctions with an area of 580×580 µm2 fabricated by P+/F+ dual implantation at 35/30 keV to a dose of 5×1015/5×1015 cm-2 followed by 750 °C thermal annealing. The junction formed is about 71 nm from the NiSi/Si interface. Activation energy measurement shows that the reverse bias area current of the NiSi/n+p junctions is dominated by the diffusion current, while their reverse bias peripheral current is dominated by the minority generation current at room temperature. This implies the presence of generation centers in and/or close to the junction region along the perimeter.

Cobalt Contamination in Silicon

The properties of cobalt as a contaminant in p-type silicon are studied by using cobaltimplanted wafers annealed by RTP or by RTP plus a low temperature furnace annealing. It is shown that after RTP most cobalt is under the form of CoB pairs. A quantification of cobalt contamination is provided based upon SPV measurements and optical pair dissociation. However, this quantification fails in furnace-annealed wafers because of the formation of a different level. It is shown that the CoB level is located near the band edges, whereas the level formed upon a low temperature furnace annealing is located near midgap. Besides, when the cobalt concentration is high enough a small fraction of cobalt is in a level different from the CoB pair even in RTP samples. This level can probably be identified with a previously observed midgap level. It is suggested that the same level is formed in RTP plus low temperature furnace annealed samples and in high concentration RTP annealed samples, and that this level may consist in some cobalt agglomerate.

Post-annealing sequence effects on the characteristics of 20 keV BF2 ion implantation at various ion fluences

Various ion fluences together with different post-annealing sequences were performed to investigate the shallow-junction characteristics produced by 20keV BF2+ molecular ions implanted into silicon. The ion fluences under investigation were 5×1014 and 2×1015cm−2. Post-annealing methods consisted of low-temperature furnace annealing (FA) at 550°C for 1h and high-temperature rapid thermal annealing (RTA) at 1050°C for 10s. The shallow-junction characteristics were analyzed using secondary ion mass spectrometry (SIMS), Rutherford backscattering spectrometry with channeling (RBS/C), transmission electron microscopy (TEM) and a four-point probe. The results revealed that the junction depth (xj) of the FA+RTA annealing sequence was shallower than that of RTA+FA in both ion fluences. However, the sheet resistance (Rs) of FA+RTA was lower than that of RTA+FA in the 2×1015cm−2 specimen, while just the opposite is true in the 5×1014cm−2 specimen. It is concluded that FA+RTA, leading to a smaller xjRs, is a better two-step post-annealing sequence compared to RTA+FA for both ion fluences.

Characteristics of heavily doped p+∕n ultrashallow junction prepared by plasma doping and laser annealing

High quality p+∕n ultrashallow junctions were fabricated by high dose plasma doping and two step annealing involving low-temperature furnace annealing and excimer laser annealing. Without a preamorphization process, laser annealing is effective in terms of activation and annealing. Meanwhile, the junction depth can be controlled by the low-temperature annealing process prior to the laser annealing. By combining low-temperature preannealing and laser annealing, ultrashallow (junction depth ∼22nm), low sheet resistance (∼275Ω∕sq.), and a defect-free p+∕n junction can be obtained without preamorphization.

Formation of NiSi-Silicided p + n Shallow Junctions Using Implant-Through-Silicide and Low-Temperature Furnace Annealing

NiSi-silicided shallow junctions are fabricated using implantation into/through thin NiSi silicide layer (implant-through-silicide technology) followed by low-temperature furnace annealing (from 550 to 800°C). The NiSi film agglomerates following a thermal annealing at 600°C and may result in the formation of discontinuous islands at a higher temperature. The incorporation of fluorine atoms in the NiSi film can retard the formation of film agglomeration and thus improving the film’s thermal stability. The forward ideality factor of about 1.02 and the reverse current density of about 1 nA/cm2 can be attained for the NiSi junctions fabricated by implantation at 35 keV to a dose of followed by a 650°C thermal annealing; the junction formed is about 60 nm measured from the NiSi/Si interface. Activation energy measurement indicates that the reverse bias junction currents are dominated by the diffusion current, indicating that most of the implanted damages can be recovered after annealing at a temperature as low as 650°C. © 2003 The Electrochemical Society. All rights reserved.

A Novel Two-Step Annealing Technique for the Fabrication of High Performance Low Temperature Poly-Si TFTs

Low temperature processed (LTP) poly-Si thin film transistors (TFTs) fabricated with a poly-Si film crystallized by a novel two-step annealing (NTSA) technique were investigated and compared with those using conventional solid phase crystallization (SPC) and excimer laser annealing (ELA) schemes. The NTSA scheme is characterized by the combination of an excimer laser induced formation of nucleation centers and a short-time low temperature furnace annealing (about 6 h at 600°C) creating clear crystalline grains with very few in-grain defects. The LTP poly-Si TFTs fabricated with a NTSA poly-Si film not only exhibit a better performance but also significantly shorten the crystallization time as compared to those fabricated using the conventional SPC (about 20 h or longer at 600°C). In addition, the uniformity of the device characteristics for the devices using the NTSA scheme is superior to that using the ELA scheme and is comparable to that using the SPC scheme. © 2003 The Electrochemical Society. All rights reserved.

Kinetics of solid phase regrowth of self-ion-implanted amorphous SiC during low temperature furnace annealing

The solid phase regrowth (SPR) model for the amorphous SiC phase induced by self-ion-implantation is shown. This was derived from in situ time-resolved optical reflectivity (TROR) measurements, and the crystallinity evaluation method based on Raman spectrometry and Rutherford backscattering spectrometry (RBS). The roughness of an amorphous–recrystalline layer interface was monitored during a heat treatment. By the TROR measurements, it was proven that the roughness of moving interface increases during the SPR. Raman spectrometry measurements have confirmed that the polytype of the SPR layer is the same as that of the substrate. RBS channeling measurements have made it clear that the fraction of c-axis orientation in the SPR layer was about 13%.

Formation of NiSi-Silicided p + n Shallow Junctions Using Implant Through Silicide and Low Temperature Furnace Annealing

AbstractNiSi-silicided p+n shallow junctions are fabricated using BF2+ implantation into/through thin NiSi silicide layer (ITS technology) followed by low temperature furnace annealing (from 550 to 800°C). The NiSi film agglomerates following a thermal annealing at 600°C, and may result in the formation of discontinuous islands at a higher temperature. The incorporation of fluorine atoms in the NiSi film can retard the formation of film agglomeration and thus improve the film's thermal stability. A forward ideality factor of about 1.02 and a reverse current density of about 1nA/cm2 can be attained for the NiSi(310Å)/p+n junctions fabricated by BF2+ implantation at 35 keV to a dose of 5×1015cm-2 followed by a 650°C thermal annealing; the junction formed is about 60nm measured from the NiSi/Si interface. Activation energy measurements show that the reverse bias junction currents are dominated by the diffusion current, indicating that most of the implanted damages can be recovered after annealing at a temperature as low as 650°C.

Formation of Shallow p+n Junctions Using Different Annealing Schemes with Low Thermal Budget

The formation of shallow p+n junctions by directly implanting BF2 dopant into the Si substrates and then treating the samples by different annealing schemes with a low thermal budget has been studied. Nosignificant dopant diffusion is observed by using these annealing processes with a low thermal budget. After conventional furnace annealing (FA) at a medium temperature of 800°C for 30 min, the resulting junction characteristics are poor. A low-temperature long-time FA treatment at 600°C for 2 h, prior to the medium-temperature FA treatment, can considerably improve the junction formation. Furthermore, shallow p+n junctions with a leakage smaller than 10 nA/cm2 can be achieved by an annealing scheme that employs low-temperature FA followed by medium-temperature rapid thermal annealing (RTA) at 800°C for 30 s. However, an annealing process that employs medium-temperature RTA at 800°C for 30 s followed by low-temperature FA treatment cannot produce good junctions. In addition, the low-temperature annealing time of 2–3 h is found to be sufficient for forming good shallow p+n junctions in the annealing scheme that employs low-temperature FA followed by medium-temperature RTA.

Shallow p/sup +/n junctions formed by using a two-step annealing scheme with low thermal budget

Shallow p/sup +/n junctions have been formed by directly implanting BF/sub 2/ dopant into the Si substrate and then treating the samples by an annealing scheme with low thermal budget. A junction leakage smaller than 10 nA/cm/sup 2/ can be achieved by an annealing scheme that employs low-temperature long-time furnace annealing (FA) at 600/spl deg/C for 3 h followed by medium-temperature rapid thermal annealing (RTA) at 800/spl deg/C for 30 s. No considerable dopant diffusion is observed by using this low-thermal-budget annealing process. In addition, a moderate low-temperature annealing time of about 2-3 h should be employed to optimize the shallow p/sup +/n junction formed by this scheme. However, the annealing process that employs medium-temperature RTA followed by low-temperature FA treatment produces worse junctions than the annealing scheme that employs long-time FA at 600/spl deg/C followed by RTA at 800/spl deg/C.

Deposition and crystallization of a-Si thin films by rapid thermal processing

The deposition and crystallization of a-Si thin films grown by rapid thermal processing have been studied, using transmission electron microscopy. The a-Si films were deposited in a rapid thermal processor at reduced pressures in the temperature range of 530–580°C, at different deposition pressures and silane flow rates and subsequently were annealed in-situ by high temperature rapid thermal annealing (RTA) or by a two-step annealing process involving low temperature furnace annealing (FA) followed by high temperature RTA. The activation energy of a-Si deposition was found to be approximately 1.7 eV, in reasonable agreement with the conventional LPCVD technique. It has been found that the deposition temperature and deposition rate have a strong effect on the grain size, which is attributed to the nucleation processes in the bulk of the films. The combination of low deposition temperature, high deposition rate and a two-step annealing process permits the low temperature growth of poly-Si films of 100 nm thickness, with large grains of 520 nm size, containing a low density of microtwins and characterized by very low surface roughness of 2.2 nm.

Fabrication and Characterization of the Pd-Silicided Emitters for Field-Emission Devices

The structure of Pd-silicided field emitters based on the silicon micromachining technology has been demonstrated. The uniform and extremely sharp silicided emitters are formed using wet chemical etching, low-temperature oxidation sharpening (LTOS), metal coating, and furnace annealing. The silicided emitters are firstly identified by the bright-field, dark-field images, and diffraction patterns of transmission electron microscope (TEM). Under the applied voltage of 1100 V, the anode currents of the Pd-coated and silicided emitters are 16 µ A and 26 µ A, respectively. The values of threshold voltage V T for Pd-coated and silicided emitters are about 745 V and 785 V, respectively. The lower threshold voltage of the Pd-coated emitters is duo to the smaller emission work function of palladium. The emission work function of the Pd-silicided emitters is calculated to be 8.31 eV. Furthermore, the long and short-term current stabilities of silicided emitters is also better than that of Pd-coated ones. These results show that these silicided emitters have potential applications in vacuum microelectronics to obtain superior lifetime, reliability, and stability.

A study of base contact formation in epitaxial [formula omitted] HBT structures

An HBT structure was grown by LP-VPE and comprises a 45 nm thick Si 0.88Ge 0.12 base layer, of which the central 25 nm is doped with boron (2 × 10 19 cm −3). The base was capped by a 150 nm thick low doped emitter (LDE) layer (10 18 As cm −3). Three different implantation conditions were employed in order to make contact to the base through the LDE, two of which involved preamorphisation with Ge +. The redistribution of epitaxial and implanted boron after low temperature (600°C) furnace annealing and rapid thermal processing (RTP) at 1000°C was studied by SIMS. The information from SIMS is correlated with observations of the defect structures (TEM and RBS/C) and amorphous layer thicknesses before and after annealing. This study shows that preamorphisation leads to a significant reduction in the defect density of the LDE after RTP, reduces the amount of implant channelling and increases control over the boron profile. Care must be taken to ensure that the residual damage from the implants, does not intersect the base layer.

Formation of cobalt silicided shallow junction using implant into/through silicide technology and low temperature furnace annealing

This work investigates the shallow CoSi/sub 2/ contacted junctions formed by BF/sub 2//sup +/ and As/sup +/ implantation, respectively, into/through cobalt silicide followed by low temperature furnace annealing. For p/sup +/n junctions fabricated by 20 keV BF/sub 2//sup +/ implantation to a dose of 5/spl times/10/sup 15/ cm/sup -2/, diodes with a leakage current density less than 2 nA/cm/sup 2/ at 5 V reverse bias can be achieved by a 700/spl deg/C/60 min annealing. This diode has a junction depth less than 0.08 /spl mu/m measured from the original silicon surface. For n/sup +/p junctions fabricated by 40 keV As/sup +/ implantation to a dose of 5/spl times/10/sup 15/ cm/sup -2/, diodes with a leakage current density less than 5 nA/cm/sup 2/ at 5 V reverse bias can be achieved by a 700/spl deg/C/90 min annealing; the junction depth is about 0.1 /spl mu/m measured from the original silicon surface. Since the As/sup +/ implanted silicide film exhibited degraded characteristics, an additional fluorine implantation was conducted to improve the stability of the thin silicide film. The fluorine implantation can improve the silicide/silicon interface morphology, but it also introduces extra defects. Thus, one should determine a tradeoff between junction characteristics, silicide film resistivity, and annealing temperature.