Low Switching Losses Research Articles

A Review of Switching Slew Rate Control for Silicon Carbide Devices Using Active Gate Drivers

Driving solutions for power semiconductor devices are experiencing new challenges since the emerging wide bandgap power devices, such as silicon carbide (SiC), with superior performance become commercially available. Generally, high switching speed is desired due to the lower switching loss, yet high dv/dt and di/dt can result in elevated electromagnetic interference (EMI) emission, false-triggering, and other detrimental effects during switching transients. Active gate drivers (AGDs) have been proposed to balance the switching losses and the switching speed of each switching transient. The review of the in-existence AGD methodologies for SiC devices has not been reported yet. This review starts with the essence of the slew rate control and its significance. Then, a comprehensive review categorizing the state-of-the-art AGD methodologies is presented. It is followed by a summary of the AGDs control and timing strategies. In this work, using AGD to reduce the EMI noise of a 10-kV SiC MOSFET system is reported. This work also highlights other capabilities of AGDs, including reliability enhancement of power devices and rebalancing the mismatched electrical parameters of parallel- and series-connected devices. These application scenarios of AGDs are validated via simulation and experimental results.

FFS modulated VSC with different phase‐shifted 12‐pulse configured transformers for grid integrated large‐scale solar PV plant

The requirement for high capacity power conditioning unit (PCU) has increased for application in large-scale solar photovoltaic (PV) plant for optimisation of the balance of system cost. For high power applications, one of the most important criteria for designing of PCU is to have lower switching losses to minimise the heat generated in the power switching devices. Conventionally, PCU utilises traditional two-level or three-level voltage source converter (VSC) topology with high-frequency switching techniques and due to this, they have lower conversion efficiency and higher device switching losses. In this study, fundamental frequency switching (FFS) modulated three-level neutral point clamp (3L-NPC) VSC is used for MW scale PCU, as they have lower switching losses, higher conversion efficiency and higher AC/DC voltage ratio. The 3L-NPC VSC generates lower order current harmonics, which are mitigated by using different phase-shifted 12-pulse PCU transformers located at different pooling location inside solar PV plant. The PV plant configuration for a 40 MW (AC) plant capacity is developed in the Matlab/Simulink environment and implemented in real-time simulator OPAL-RT to validate the proposed concept. Harmonics, steady-state and dynamic performances are demonstrated at constant and changing solar irradiance levels.

A 28-/60-GHz Band-Switchable Bidirectional Amplifier for Reconfigurable mm-Wave Transceivers

Performance limits and design techniques for millimeter-wave amplifiers employing switches for multiband operation are presented in this article. A bidirectional dual-band amplifier is designed in a 130-nm silicon-germanium (SiGe) process. The amplifier can shift its operational frequency between 28 or 60 GHz and can operate in low-noise receive or high-power transmit mode. The frequency shift and transmit-receive (T/R) mode change has been realized using shunt switches based on SiGe HBTs. The switches are co-optimized and integrated with amplifiers to reduce the die area and improve performance. An analysis of switch loss reduction and associated tradeoffs is provided. The designed shunt switch, for band-switching operation, achieves the simulated ON-loss of as low as 1 dB at 60 GHz and OFF-loss of 0.7 dB at 28 GHz. By using these low-loss switches and a codesign approach, the proposed T/R amplifier surpasses the state-of-the-art performance in terms of mm-wave multiband amplifiers.

Evolutionary algorithm based selective harmonic elimination for three-phase cascaded H-bridge multilevel inverters with optimized input sources

Multilevel inverters are finding wide application in electric drives, traction, flexible AC transmission systems (FACTS) and renewable energy systems. A cascaded H-bridge type multilevel inverter (CHBMLI) produces a near sinusoidal output voltage with lower switching stress and a higher conversion efficiency than the other types of MLIs. The Selective Harmonic Elimination (SHE) strategy is used to eliminate lower-order harmonic profiles and to regulate the fundamental component in the output voltage. SHE has the advantages of low switching frequency, low switching losses and low stress. In this paper, the modulation index and input voltage values are also considered as optimization variables along with the conventional switching angles to analyze the performance improvement in selective harmonic elimination. Heterogeneous Comprehensive Learning Particle Swarm Optimization (HCLPSO) and Gravitational Search Algorithm (GSA) algorithms are used to find the optimal switching angles, modulation index and input voltage source values for minimizing the lower-order harmonics present in the output voltage of seven-level and eleven-level CHBMLIs, while maintaining the fundamental component of the output voltage. The results obtained from MATLAB simulations and an experimental setup clearly indicate that the proposed HCLPSO-based multilevel inverter provides better performance when compared with GSA, firefly and Differential Search Algorithm (DSA)-based MLIs.

Using Gated Recurrent Units for Selective Harmonic Current Mitigation-PWM in Grid-Tied Cascaded H-Bridge Converters

Grid-tied converters become more popular for electric vehicle, renewable energy, and energy storage systems applications. Different modulation techniques such as low-frequency (e.g., selective harmonic elimination-PWM, selective harmonic mitigation-PWM, and selective harmonic current mitigation-PWM (SHCM-PWM)) and high-frequency modulation techniques (e.g., phase shift-PWM and space vector modulation) are used in the literature for grid-tied converters. Low-frequency modulation techniques have a high-efficiency due to the low-switching power losses. One of the main challenges of low-frequency modulation techniques such as SHCM-PWM is how to implement the proposed technique in real-time, due to the transcendental Fourier equations of SHCM-PWM. In this paper, a deep learning technique (i.e., gated recurrent units) is adopted to implement the SHCM-PWM technique in real-time. To evaluate the effectiveness of the proposed learning-based technique, both simulation and experiments are performed for a single-phase 3-cell 7-level CHB converter.

Dynamic characteristics of PdCoO2/β-Ga2O3 Schottky junctions

A high-frequency diode is an essential component in electrical circuits providing the current rectification function for AC/DC converters, radio frequency detectors, and automotive inverters. Schottky barrier diodes based on wide-bandgap semiconductors are promising for the high-frequency applications owing to short reverse recovery time that minimizes the energy dissipation during the switching. In this study, we report dynamic characteristics of Schottky junctions composed of a layered oxide metal PdCoO2 and an n-type β-Ga2O3 substrate. Rectifying current–voltage characteristics with reasonably small hysteresis were demonstrated up to a high frequency of 3 MHz in the PdCoO2/β-Ga2O3 Schottky junctions. For the on-state to off-state switching with the current ramp rate of approximately −2 × 1010 A/scm2, the reverse recovery time was as short as 11 ns. The short reverse recovery time was constantly obtained in the operation temperature range of 25–350 °C, showing low-loss switching properties of the PdCoO2/β-Ga2O3 Schottky junctions. The Schottky barrier height of ∼1.78 eV and the ideality factor of ∼1.06 were maintained after the 108-times on–off switching cycles. The fast switching with less energy dissipation and high durability of the PdCoO2/β-Ga2O3 Schottky junctions would be suitable for application in high-frequency power devices operating at high temperature.

A Hybrid Compensator Configuration for VAR Control and Harmonic Suppression in All-Electric Shipboard Power Systems

This paper proposes a cost-effective compensator to suppress harmonics and compensate the power factor of all-electric shipboard power systems (SPSs). This compensator, which is based on a fixed capacitor-thyristor controlled reactor (FC-TCR), behaves as a low-pass filter and therefore can reject both low and high-order harmonics. Moreover, the FC-TCR compensator is featured by the low switching losses; hence, it can effectively be implemented for low and medium voltage applications. The design of the filter is detailed via equivalent lossy circuits, which exhibit the mechanism of the harmonic mitigation. Furthermore, theoretical analyses and mathematical developments are suggested to enhance the filtering performance. Besides, details of the Fixed-Point iteration technique which is applied to extract the firing angle of the TCR are conducted. A practical SPS is selected to ensure and demonstrate the performance of proposed methodology via thorough simulations under MATLAB/Simulink environment. The obtained results verify the theoretical analyses and confirm the effectiveness of proposed solution.

Interleaved Ultrahigh Step-Down Converter With Low Component Count

An ultrahigh step-down converter with a low number of semiconductor devices is presented in this article. Important features of this converter are simple structure with low size and cost, low voltage and current stress on components, low output current ripple, and low conduction and switching losses. In this converter, the power switches are turned on under zero current switching (ZCS) condition, whereas the output diodes commutate under ZCS condition without any auxiliary circuit. Thereby, in addition to the converter efficiency improvement, the diodes reverse recovery problem is alleviated. The proposed topology has employed a two-phase interleaved structure to reduce current stress, three windings coupled inductors to further decrease the voltage gain, and two series capacitors to diminish the voltage stress on the semiconductors elements and recover the leakage inductances energy. The experimental results of an implemented prototype are provided to evaluate the effectiveness of the proposed topology at 100 kHz and 200 W, which converts a 400-V input voltage into a 12-V output voltage.

A High Voltage Gain Step-up Resonant DC-DC Converter Topology with Reduced Switch Count

The resonant converters have attracted a lot of attention because of their high efficiency and low switching losses. This paper presents the analysis of a high voltage gain non-isolated step-up DC-DC converter topology using resonant technology. The proposed converter configuration has reduced number of power semiconductor switches compared to the existing isolated converter topology having four semiconductor switches. The proposed topology employs capacitor-inductor-capacitor (C-L-C) resonant circuit configuration. The size of the proposed converter and the losses in the converter are greatly reduced. Both the converters with resonant components are simulated in Matlab/Simulink platform to validate their performance. The time-domain simulation results demonstrate that the proposed non-isolated converter gives improved voltage gain compared to the existing two-stage isolated resonant DC-DC converter.

CMOS Active Gate Driver for Closed-Loop dv/dt Control of GaN Transistors

This article shows both theoretical and experimental analyses of a fully integrated CMOS active gate driver (AGD) developed to control the high dv/dt of GaN transistors for both 48 and 400 V applications. To mitigate negative effects in the high-frequency spectrum emission, an original technique is proposed to reduce the dv/dt with lower switching losses compared to classical solutions. The AGD technique is based on a subnanosecond delay feedback loop, which reduces the gate current only during the dv/dt sequence of the switching transients. Hence, the dv/dt and di/dt can be actively controlled separately, and the tradeoff between the dv/dt and EON switching energy is optimized. Since GaN transistors have typical voltage switching times on the order of a few nanoseconds, introducing a feedback loop from the high voltage drain to the gate terminal is quite challenging. In this article, we successfully demonstrate the active gate driving of GaN transistors for both 48 and 400 V applications, with initial open-loop voltage switching times of 3 ns, due to a full CMOS integration. Other methods for dv/dt active control are further discussed. The limits of these methods are explained based on both experimental and simulation results. The AGD showed a clear reduction in the peak dv/dt from -175 to -120 V/ns for the 400 V application.

A Novel Multilevel Inverter with Reduced Number of Switches Using Simplified PWM Technique

Multilevel inverter (MLI) topologies greatly sustained the emergence of modish power-electronic device as an expressive substitute of traditional two-level inverters in the area of medium-voltage high-power energy conversion schemes. It recommends the most outstanding solutions for high-power applications particularly in distributed generation schemes and plays a key role for establishment of novel MLI structures with fewer switching components. This paper proposes the novel 7-level asymmetric MLI topology and administered by both fundamental frequency-based pulse-width modulation (PWM) scheme and advanced multi-carrier PWM scheme. The proposed asymmetric 7-level smart MLI topology offers low switching elements, low gate drive circuits, low cost, minimum space requirement, low-voltage dv/dt switch stress, low switching loss and high efficiency over the traditional topologies. The critical evaluation of proposed 7-level asymmetric MLI performance is verified by MATLAB/Simulink platform and validated through experimental prototype; results are illustrated with proper comparisons.

A Coupled Inductor Based High Step-Up Converter for DC Microgrid Applications

A high gain nonisolated dc-dc converter is proposed for the distributed generation systems. High voltage gain is achieved by integrating different methods with reduced duty ratio. Inductive voltage spikes across MOSFETs are alleviated and stress is reduced with inclusion of a passive-clamp circuit. Thus, lower voltage rating (small R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds(ON)</sub> ) active devices can be adopted. Using this clamp, zero-voltage switching over wide load range is achieved for both the MOSFETs. In addition, leakage energy of the coupled inductor is recycled without using auxiliary switch and thus, the gain get further improved. Zero-current switching is obtained for all the diodes using quasi - resonance principle, which diminishes voltage spikes across the diode caused by the parasitic ringing between leakage inductance and diode's stray capacitance. Therefore, snubbers are not necessary to protect the diodes and to mitigate reverse-recovery losses. Overall efficiency improves because of lower switching and conduction losses of the semiconductor devices. A 600 W prototype working at 75 kHz is built in the laboratory to verify the performance. The peak efficiency is nearly 96.5% and is above 95% for wide load range.

Application of the IGCT for Resonant Conversion with Low Switching Losses

Application of the IGCT for Resonant Conversion with Low Switching Losses

A Novel 4H-SiC Super Junction UMOSFET with Hetero-Junction Diode for Enhanced Reverse Recovery Characteristics and Low Switching Loss

In this paper, a novel silicon carbide (SiC) super-junction U-shape metal-oxide semiconductor field-effect transistor (UMOSFET) with an integrated hetero-junction diode (HJD) is proposed and investigated using numerical simulations. The integrated HJD substantially improves body diode characteristics and reduces switching losses without degrading the static characteristics of the device. In this structure, a p+ shielding region between the p-poly region and p-pillar protects not only the bottom gate oxide but also the p-poly region from high electric fields. Compared with conventional SJ UMOSFETs, the proposed structure reduces the peak reverse recovery current (IRR) by a factor of 2.58 and the reverse recovery charge (QRR) by a factor of 4.94. Moreover, the total switching energy loss is decreased by 50.2%.

Design, control and comparative analysis of an LCLC coupling hybrid active power filter

This study provides the design, control and comparative analysis of the proposed LCLC coupling hybrid active power filter (LCLC-HAPF). Compared with the conventional L filter coupling active power filters (APFs), LC filter and LCL filter coupling HAPFs (LC-HAPFs and LCL-HAPFs), the proposed LCLC-HAPF provides better switching frequency harmonics elimination, lower dc-link voltage rating and switching loss. Although the LCLC-HAPF has some advantages, two main challenges will still be confronted in practical implementations. Those are stability problems caused by resonance of LCLC filter, and parameter design for the LCLC filter. In this study, a new active damping method is proposed to overcome the high order resonance problem existing in the proposed LCLC-HAPF. After that, the stability analysis and parameter design are given for the proposed LCLC-HAPF. Finally, the effectiveness of the proposed LCLC-HAPF topology is validated through both simulation and experimental studies in comparison with the conventional APFs and HAPFs.

Resonance-Based Optimized Buck LED Driver Using Unequal Turn Ratio Coupled Inductance

Losses in light-emitting-diode (LED) driver cause increasing temperature and shorten their lifespan. Therefore, improving the efficiency of LED drivers not only saves energy but also is indispensable to increase their lifespan. In this article, a new LED driver topology is proposed to improve the performance of valley switching by decreasing the mosfet switching losses. The proposed topology is designed in a way that the mosfet works at the significantly lower switching and conduction losses in compared with conventional LED drivers. It elaborates how the proposed topology also improves the overall efficiency by decreasing power losses in other main elements of the driver, including inductance and diode. In addition, a new valley switching implementation is introduced for the new converter, which decreases the cost and dimension of the LED drivers. The experimental results confirm the high efficient operation of the proposed LED driver by reaching the efficiency up to 97% at a wide range of operating voltage.

Comparative analysis of CBPWM methods for two-phase three-leg inverters using zero sequence concept

This paper proposes carrier-based PWM (CBPWM) methods that apply a zero sequence concept in a two-phase three-leg inverter. The total harmonic distortion (THD) and switching losses are analyzed and compared for the five CBPWM methods. The voltage and current THDs decrease when the modulation index (MI) increases in all the PWM methods. The space vector PWM (SVPWM) shows the lowest current THD. The switching losses increase linearly with an increasing MI, and the discontinuous PWM (DPWM) methods have lower switching losses than the continuous PWM (CPWM) methods such as sinusoidal PWM (SPWM) and SVPWM. Simulations and experiments are carried out to verify the performances of the CBPWM methods using a zero sequence concept.

Real-Time Selective Harmonic Mitigation Technique for Power Converters Based on the Exchange Market Algorithm

Hand-in-hand with the smart-grid paradigm development, power converters used in high-power applications are facing important challenges related to efficiency and power quality. To overcome these issues, the pre-programmed Pulse-Width Modulation (PWM) methods have been extensively applied to reduce the harmonic distortion with very low power switching losses for high-power converters. Among the pre-programmed PWM techniques, Selective Harmonic Elimination (SHE) has been the prevailing solution, but recently, Selective Harmonic Mitigation (SHM) stands as a superior alternative to provide further control of the harmonic spectrum with similar losses. However, the large computational burden required by the SHM method to find a solution confines it as an off-line application, where the switching set valid solutions are pre-computed and stored in a memory. In this paper, for the first time, a real-time implementation of SHM using an off-the-shelf mid-range microcontroller is presented and tested. The Exchange Market Algorithm (EMA), initially focused on optimizing financial transactions, is considered and executed to achieve the SHM targets. The performance of the EMA-based SHM is presented showing experimental results considering a reduced number of switching angles applied to a specific three-level converter, but the method can be extrapolated to any other three-level converter topology.

Analysis and Design Capacitive Power Transfer (CPT) System for Low Application Using Class-E LCCL Inverter by Investigate Distance between Plates Capacitive.

This study presents the analysis and design of a Capacitive Power Transfer (CPT) system for low power application using a Class-E LCCL inverter based on varying the distance between capacitance plates. The Class-E LCCL inverter can produce a high-frequency alternate current and reduce the size of the capacitance plate to minimise power losses during energy transfer besides yielding low switching losses. In specific, the performance of the LCCL CPT system at 1 MHz operating frequency and 24 V DC supply voltage was analysed via simulation and experimental works. Finally, a prototype of the CPT system was successfully designed, producing 10 W output power through a capacitive plate size of 0.0327 m2 and a 0.1 cm air gap at 96.68% efficiency. Based on the performance of the LCCL CPT System design, an efficiency analysis of the LCCL CPT System was performed; the capacitance plate distance was varied from 1 cm to 20 cm and produced a change in total impedance calculation from 57.69+j198.42 Ohm to −2.05j Ohm. Meanwhile, efficiency decreased from 96.68% to 1.25% but power was still transmitted in that range. These findings could be beneficial for hazardous electrical environments, portable applications, consumer electronics, and medical implants.

Dc‐link capacitor voltage control for the NPC three‐level inverter with a newly MPC‐based virtual vector modulation

Dc-link capacitor voltage unbalance would affect the performance of the neutral-point clamped (NPC) three-level inverter. With the traditional virtual space vector modulation (VSVPWM) method, the dc-link capacitor voltage could be kept balance under the different modulation indexes or power factors. With the virtual medium vector being set as an adjustable one, the voltage balance could be better guaranteed no matter there might have some non-linear factors However, whether the traditional or improved VSVPWM method has a complicated trigonometric calculation, thus, a newly MPC-based virtual vector modulation has been proposed in this paper. With the 19 virtual space vectors being in roll optimisation, a nice current trajectory, dc-link capacitor voltage balance, even a relative low switch losses have been implemented. Considering that the optimised virtual space vector could not be taken as a direct output, the distribution of the basic vectors has been generated to make it being favourable for modulation. The effectiveness of this MPC-based virtual vector modulation is verified in comparisons with other methods, which can save over 67.3% execution time of the traditional SVPWM method, and over 46.6% of the improved VSVPWM way while provide a better dc-link capacitor voltage balance and output current quality.