Low Subthreshold Swing Values Research Articles

Stabilization of Tetragonal Phase in Hafnium Zirconium Oxide by Cation Doping for High-K Dielectric Insulators.

As electronic circuit integration intensifies, there is a rising demand for dielectric insulators that provide both superior insulation and high dielectric constants. This study focuses on developing high-k dielectric insulators by controlling the phase of the Hf0.5Zr0.5O2 (HZO) film with additional doping, utilizing yttrium (Y), tantalum (Ta), gallium (Ga), silicon (Si), and aluminum (Al) as dopants. Doping changes the ratio of tetragonal to monoclinic phases in doped HZO films, and Y-doped HZO (Y:HZO) films specifically exhibit a high tetragonal phase ratio and a dielectric constant of 40.9, indicating superior insulating properties compared to undoped HZO films. To clarify the fundamental mechanism driving the enhancement in dielectric properties, we have carried out various analyses combined with density functional theory (DFT) calculations. Through the optimization of the post-deposition annealing (PDA) process and the heterojunction structure with Al2O3, an Al2O3/Y:HZO heterojunction with a high dielectric constant and even lower leakage current compared to a single layer was developed. The thin-film transistor (TFT) with the Au/Ti/amorphous InGaZnO4 (a-IGZO)/Al2O3/YHZO/TiN heterojunction structure exhibits low subthreshold swing (SS) values within a narrow gate-source voltage (Vsg) range. This study advances knowledge on how the controlled-phase doped HZO films affect the dielectric constant and leakage current and will contribute to semiconductor technology advancements by overcoming the limitations of conventional high-k dielectric insulators.

Two-Dimensional Vertical Transistor with One-Dimensional van der Waals Contact.

Two-dimensional (2D) materials enable vertical field effect transistors (VFETs), which provide an alternative path for scaling down the channels of transistors. The challenge is the short channel effect when the thickness of the 2D channel decreases to ∼10 nm. Here, we show that a VFET with an ultrashort channel can be accomplished by employing a semimetal carbon nanotube (CNT) as a 1D van der Waals (vdW) contact. The CNT-VFETs with 5-10 nm MoS2 channels exhibit high on/off ratios exceeding 105, low subthreshold swing values of 160-120 mV/dec, and high current densities over 104 A/cm2. Such a switch even works with an ∼ 3.4 nm thick channel. The excellent comprehensive performance can be ascribed to the reduced short channel effect as the sub-2 nm CNT contact has weaker electrostatic screening to the gate, a reduced Fermi level pinning effect, and a highly tunable barrier. The VFETs with 1D vdW contacts hold great promise for ultrascaled transistors and are prospective in future nanoelectronics and nano-optoelectronics.

Comparative Study on Indium Precursors for Plasma-Enhanced Atomic Layer Deposition of In2O3 and Application to High-Performance Field-Effect Transistors.

Indium oxide (In2O3) is a transparent wide-bandgap semiconductor suitable for use in the back-end-of-line-compatible channel layers of heterogeneous monolithic three-dimensional (M3D) devices. The structural, chemical, and electrical properties of In2O3 films deposited by plasma-enhanced atomic layer deposition (PEALD) were examined using two different liquid-based precursors: (3-(dimethylamino)propyl)-dimethyl indium (DADI) and (N,N-dimethylbutylamine)trimethylindium (DATI). DATI-derived In2O3 films had higher growth per cycle (GPC), superior crystallinity, and low defect density compared with DADI-derived In2O3 films. Density functional theory calculations revealed that the structure of DATI can exhibit less steric hindrance compared with that of DADI, explaining the superior physical and electrical properties of the DATI-derived In2O3 film. DATI-derived In2O3 field-effect transistors (FETs) exhibited unprecedented performance, showcasing a high field-effect mobility of 115.8 cm2/(V s), a threshold voltage of -0.12 V, and a low subthreshold gate swing value of <70 mV/decade. These results were achieved by employing a 10-nm-thick HfO2 gate dielectric layer with an effective oxide thickness of 3.9 nm. Both DADI and DATI-derived In2O3 FET devices exhibited remarkable stability under bias stress conditions due to a high-quality In2O3 channel layer, good gate dielectric/channel interface matching, and a suitable passivation layer. These findings underscore the potential of ALD In2O3 films as promising materials for upper-layer channels in the next generation of M3D devices.

Design and Performance Analysis of Low Sub-threshold Swing p-Channel Cylindrical Thin-film Transistors

Background: Tin monoxide (SnO) attracts considerable interest for p-channel Cylindrical Thin Film Transistors (CTFTs) applications due to their merits, including low hole effective mass, Sn s and O p orbital hybridization at the valance band maxima, and ambipolar nature, among other p-type oxide semiconductors. Objective: This article analyses the influence of channel radius and the impact of dielectric materials on the performance of SnO-based CTFT devices through 3D numerical simulations. Methods: The radius of the active layer in the CTFT was varied in the range from 10 nm to 30 nm, and it has been observed that an increase in channel radius reduces the switching behavior of the devices. Results: The 10 nm thick CTFT exhibited superior results with a lower threshold voltage of 1.5 V and higher field-effect mobility of 13.12 cm2/V-s over other simulated CTFTs. Conclusion: The obtained mobility values are superior to the existing planar TFTs reports. To improve the device performance further, the CTFTs with various dielectric materials have been simulated and optimized with high field-effect mobility and low sub-threshold swing values.

Enhancement of device characteristics of CNT-TFET: Role of electrostatic doping and work function engineering

In this work, an Electrostatic Doped Carbon Nanotube Tunneling FET (ED CNT-TFET) has been designed and simulated using a work function engineering technique. An intrinsic CNT is introduced as a channel material and a doped pocket is created between the source and the channel by utilizing an appropriate work function to boost the ON-state current of the device. Moreover, dielectric pocket engineering is applied to boost the high-frequency performance. The simulations, performed in this work, are conducted through a 2D solution of Poisson and Schrodinger equations which are done by utilizing the unbalanced Green function formalism. Simulation results demonstrate that the proposed device structure could improve the ON-current, cut-off frequency, and achieve a low subthreshold swing (SS) value which makes it suitable for low power applications. Additionally, the presented structure could also eliminate ambipolar conduction.

Few-Layered MnAl2S4 Dielectrics for High-Performance van der Waals Stacked Transistors.

The gate dielectric layer is an important component in building a field-effect transistor. Here, we report the synthesis of a layered rhombohedral-structured MnAl2S4 crystal, which can be mechanically exfoliated down to the monolayer limit. The dielectric properties of few-layered MnAl2S4 flakes are systematically investigated, whereby they exhibit a relative dielectric constant of over 6 and an electric breakdown field of around 3.9 MV/cm. The atomically smooth thin MnAl2S4 flakes are then applied as a dielectric top gate layer to realize a two-dimensional van der Waals stacked field-effect transistor, which uses MoS2 as a channel material. The fabricated transistor can be operated at a small drain-source voltage of 0.1 V and gate voltages within ranges of ±2 V, which exhibit a large on-off ratio over 107 at 0.5 V and a low subthreshold swing value of 80 mV/dec. Our work demonstrates that the few-layered MnAl2S4 can work as a dielectric layer to realize high-performance two-dimensional transistors, and thus broadens the research on high-κ 2D materials and may provide new opportunities in developing low-dimensional electronic devices with a low power consumption in the future.

All 2D Heterostructure Tunnel Field-Effect Transistors: Impact of Band Alignment and Heterointerface Quality.

Van der Waals heterostructures are the ideal material platform for tunnel field-effect transistors (TFETs) because a band-to-band tunneling (BTBT) dominant current is feasible at room temperature (RT) because of ideal, dangling bond-free heterointerfaces. However, achieving subthreshold swing (SS) values lower than 60 mV dec-1 of the Boltzmann limit is still challenging. In this work, we systematically studied the band alignment and heterointerface quality in n-MoS2 channel heterostructure TFETs. By selecting a p+-MoS2 source with a sufficiently high doping level, stable gate modulation to a type III band alignment was achieved regardless of the number of MoS2 channel layers. For the gate stack formation, it was found that the deposition of Al2O3 as the top gate introduces defect states for the generation current under reverse bias, while the integration of a hexagonal boron nitride (h-BN) top gate provides a defect-free, clean interface, resulting in the BTBT dominant current even at RT. All 2D heterostructure TFETs produced by combining the type III n-MoS2/p+-MoS2 heterostructure with the h-BN top-gate insulator resulted in low SS values at RT.

Enhanced zirconia oxide dielectric quality of germanium p-channel metal oxide semiconductor field effect transistor by in-situ low temperature treatment in atomic layer deposition process

The gate dielectric quality of germanium (Ge) p-channel metal oxide semiconductor field effect transistor (MOSFET) is enhanced by using an in-situ low temperature treatment in atomic layer deposition (ALD) process in this work. With additional oxygen flow or remote oxygen-based plasma, the dangling bond, oxygen vacancy, and oxide traps in the ALD-formed zirconia oxide gate dielectric can be effectively passivated. Unlike the traditional post deposition annealing process that generally causes an increased equivalent oxide thickness (EOT) significantly, the in-situ low temperature treatment can lower the EOT value, reduce the gate leakage current, and improve the gate dielectric quality at the same time. As a result, the sample with an additional oxygen gas flow can exhibit a lower hysteresis value, better frequency dispersion characteristics, higher on/off current ratio, lower sub-threshold swing value, higher transconductance value, higher field effect mobility value, and better uniformity, simultaneously. This dielectric quality enhancement technique with in-situ low temperature process is promising to overcome the trade-off between EOT and gate leakage for the future Ge MOSFET devices.

Organic single crystals of cyano-substituted p-phenylene vinylene derivatives as transistors with low surface trap density.

We obtained two high-quality lamellar crystals of cayno-substituted p-phenylene vinylene derivatives and fabricated their transistors. The transistors demonstrated hysteresis-free, low subthreshold swing values of 0.15 and 0.10 V dec-1, and high mobilities of 0.56 and 2.73 cm2 V-1 s-1, respectively. More importantly, the low defect density of 1 per 9.22 × 103 and 1.82 × 104 molecules, respectively, confirmed their high crystal quality.

3D GaN nanoarchitecture for field-effect transistors

Abstract The three-dimensionality of 3D GaN field-effect transistors (FETs) provides them with unique advantages compared to their planar counterparts, introducing a promising path towards future FETs beyond Moore's law. Similar to today's Si processor technology, 3D GaN FETs offer multi-gate structures that provide excellent electrostatic control over the channel and enable very low subthreshold swing values close to the theoretical limit. Various concepts have been demonstrated, including both lateral and vertical devices with GaN nanowire (NW) or nanofin (NF) geometries. Outstanding transport properties were achieved with laterally contacted NWs that were grown in a bottom-up approach and transferred onto an insulating substrate. For higher power application, vertical FETs based on regular arrays of GaN nanostructures are particularly promising due to their parallel integration capability and large sidewall surfaces, which can be utilized as channel area. In this paper, we review the current status of 3D GaN FETs and discuss their concepts, fabrication techniques, and performances. In addition to the potential benefits, reliability issues and difficulties that may arise in complex 3D processing are discussed, which need to be tackled to pave the way for future switching applications.

Operation Up to 500 °C of Al0.85Ga0.15N/Al0.7Ga0.3N High Electron Mobility Transistors

AlGaN channel high electron mobility transistors (HEMTs) are the potential next step after GaN channel HEMTs, as the high aluminum content channel leads to an ultra-wide bandgap, higher breakdown field, and improved high temperature operation. Al0.85Ga0.15N/Al0.7Ga0.3N (85/70) HEMTs were operated up to 500 °C in ambient causing only 58% reduction of dc current relative to 25 °C measurement. The low gate leakage current contributed to high gate voltage operation up to +10 V under Vds = 10 V, with $\text{I}_{\mathrm{ ON}}/\text{I}_{\mathrm{ OFF}}$ ratios of $> 2 \times 10^{11}$ and 3 $\times \,\,10^{6}$ at 25 and 500 °C, respectively. Gate-lag measurements at 100 kHz and 10% duty cycle were ideal and only slight loss of pulsed current at high gate voltages was observed. Low interfacial defects give rise to high quality pulsed characteristics and a low subthreshold swing value of 80 mV/dec at room temperature. Herein is an analysis of AlGaN-channel HEMTs and their potential future for high power and high temperature applications.

High-Performance Thin Film Transistor with an Neodymium-Doped Indium Zinc Oxide/Al₂O₃ Nanolaminate Structure Processed at Room Temperature.

In this work, a high-performance thin film transistor with an neodymium-doped indium zinc oxide (Nd:IZO) semiconductor via a room temperature approach and adopting the Nd:IZO/Al2O3 nanolaminate structure was investigated. The effects of the ultrathin Al2O3 layer and the thickness of Nd:IZO layer in the nanolaminate structure on the improvement of electrical performance and stability of thin film transistors (TFTs) were systematically studied. Besides the carrier movement confined along the near-channel region, driven by the Al2O3 layer under an electrical field, the high performance of the TFT is also attributed to the high quality of the 8-nm-thick Nd:IZO layer and the corresponding optimal Nd:IZO/Al2O3 interface, which reduce the scattering effect and charge trapping with strong M–O bonds in bulk and the back-channel surface of Nd:IZO, according to the X-ray reflectivity (XRR), X-ray photoelectron spectroscopy (XPS), and micro-wave photo conductivity decay (μ-PCD) results. As a result, the Nd:IZO/Al2O3 TFT exhibits an outstanding performance, with a high μsat of 32.7 cm2·V−1·s−1, an Ion/Ioff of 1.9 × 108, and a low subthreshold swing (SS) value of 0.33 V·dec−1, which shows great potential for the room temperature fabrication of TFTs in high-resolution or high-frame-rate displays by a scalable, simple, and feasible approach.

Influence of impurity concentration in Ge sources on electrical properties of Ge/Si hetero-junction tunneling field-effect transistors

We have experimentally demonstrated that there is the optimum B doping concentration in the Ge source in terms of the electric performance of Ge/Si hetero-junction tunneling field-effect transistors (TFETs). The degradation in subthreshold swing (SS) is observed for TFETs with the source B concentration higher than 1 × 1020 cm−3, which can cause the degeneration in Ge. This source concentration dependence can be explained by the depression of the energy filtering effect due to the degeneracy of the Fermi level (EF). This interpretation is supported by the temperature dependence of SS in the Ge/Si TFETs with different source concentrations. Also, a low SS value of 60.6 mV/dec, an Ion value of 82.3 nA/μm, and a large Ion/Ioff ratio of 6.8 × 106 are obtained for the 1.1% tensile strain channel with the optimized B concentration in the Ge source. It is found that the influence of the source EF on the electrical characteristics of TFETs is more pronounced for the strained-Si channel TFETs with smaller Eg.eff.

Impact of Hf and Al Co-Incorporation into the Atomic-Layer-Deposited ZnO Active Channel for the Thin-Film Transistor Applications

ZnO-based oxide semiconductors have attracted much attention as active layer for thin film transistors (TFTs) due to their special features such as low-temperature process compatibility, high transparency, and wide bandgap (~3.37 eV). However, the instability and difficulty in controlling the electrical conductivity of ZnO still remain as critical issues. To solve these problems, various metal atoms have been introduced in ZnO, such as In, Ga, Sn, Al, and Hf. Among them, Hf and Al can be acted as stability enhancer by suppressing oxygen vacancies formation and as conductivity modulator by adjusting doping concentration, respectively. To effectively exploit their advantages, the composition control is one of the important parameters to be carefully adjusted. Furthermore, the active channel layer should have homogenous and smooth surface for forming good interface between Hf-Al-Zn-O (HAZO) active and Al2O3 gate insulator layers. From these viewpoints, atomic layer deposition (ALD) can be an optimum method to deposit the HAZO thin films because of such benefits as excellent conformality and good controllability for composition and film thickness. Thus, in this work, we fabricated top-gate transparent oxide TFTs using newly presented HAZO active channels deposited by ALD method and investigated the effects of Hf and Al concentration on the device performance including basic characteristics such as carrier mobility, subthreshold swing (SS), and turn-on voltage (Von), and reliability characteristics. The ALD temperature of HAZO was fixed at 100 oC. Tetrakis(ethylmethylamino)hafnium (TEMAHf), trimethylaluminium (TMA), diethylzinc (DEZ), and H2O were used as Hf, Al, Zn, and O2 sources, respectively. In this work, the composition control of Hf and Al was selected as main strategy to modulate device property. The atomic composition of 20-nm-thick HAZO thin films was controlled by adding TEMAHf and TMA cycles among a total 100 cycles. Total ALD cycles were designed so that the HfO2 and Al2O3 were located in the intervals of ZnO. For the HAZO thin film with 2-at%-Hf and 2-at%-Al, the position of two TEMAHf cycles were placed on 40th and 80th cycles, and two TMA cycles were placed on 20th and 60th cycles of total 100 cycles, separately. The incorporated amounts of Hf and Al were modulated into 2, 4, 6, 8, and 10 at% and 2 and 4 at%, respectively. The data figure shows the comparisons in transfer characteristics for the fabricated top-gate TFTs using HAZO active layers with various amounts of incorporated Hf when the incorporated Al amount was fixed at 2 at%. The fabricated devices show distinct differences in device characteristics depending on the incorporated Hf and Al compositions. When the Hf amounts were varied from 2 to 10 at%, the Von’s shifted to positive direction from negative side toward 0 V and SS values were improved from 1.12 to 0.37 V/dec. In contrast, the carrier mobility was slightly decreased from 2.97 to 1.24 cm2/Vs. The post-annealing effects were also investigated. The fabricated TFTs were thermally treated at the temperature range from 150 to 250 oC for 1 h in oxygen atmosphere. The Von shifted toward positive direction and SS were improved as the increase in annealing temperature, although the on-current and carrier mobility showed decreasing trend. In conclusion, we successfully confirmed that the new composition of oxide semiconductor, HAZO, can be utilized as an active layer for the oxide TFT, and that the electronic natures of the HAZO channel layers can be well controlled by adjusting the ALD conditions. The top-gate TFT using the HAZO channel with 10-at%-Hf and 2-at%-Al showed the best device characteristics such as low SS value of 370 mV/dec, low-voltage operation at around 0 V, and comparable carrier mobility of 1.24 cm2/Vs. It was also found that thermal treatment in oxygen atmosphere markedly influenced on the transfer characteristics including the location of Von. Here, we believe that the device performance can be far improved by simultaneously optimizing the Hf and Al incorporating amounts and the post annealing process condition. Optimum ALD conditions for preparing the HAZO channel layers will also be important for better device performance for the HAZO TFTs. Furthermore, we have plans to investigate the device reliability, which is one of the most important factor in evaluating device characteristics, such as positive bias temperature stress stability (PBTS), and negative bias illumination stability (NBIS). As results, highly-stable TFTs will be implemented with practical value of carrier mobility by employing HAZO channel with appropriate incorporating amounts of Hf and Al at optimum ALD conditions. Figure 1

Double-gated ultra-thin-body GaAs-on-insulator p-FETs on Si

We demonstrated ultra-thin-body (UTB) junctionless (JL) p-type field-effect transistors (pFETs) on Si using GaAs channels. Wafer bonding and epitaxial lift-off techniques were employed to fabricate the UTB p-GaAs-on-insulator on a Si template. Subsequently, we evaluated the JL FETs having different p-GaAs channel thicknesses considering both maximum depletion width and doping concentration for high performance. Furthermore, by introducing a double-gate operation, we more effectively controlled threshold voltage and attained an even higher ION/IOFF of &amp;gt;106, as well as a low subthreshold swing value of 300 mV/dec.

Low-power functionality of silicon-nanowire-assembled inverters on bendable plastics

In this paper, we demonstrate the low-power functionality of silicon nanowire (SiNW)-assembled inverters on bendable plastics. Our bendable inverters are capable of operating at supply voltages as low as 0.8 V with a switching (or standby) power consumption of ∼0.2 nW (or ∼6.6 pW). The low-power inverting operation with a voltage gain of ∼18 is attributable to the near-ideal characteristics of the component transistors that have selectively thinned SiNW channels and exhibit low, symmetrical threshold voltages of 0.40 and −0.39 V and low sub-threshold swing values of 81 and 65 mV/dec. Moreover, mechanical bendability reveals that the inverting operation has good, stable fatigue properties.

Enhancement of photodetection characteristics of MoS2 field effect transistors using surface treatment with copper phthalocyanine.

Recently, two-dimensional materials such as molybdenum disulfide (MoS2) have been extensively studied as channel materials for field effect transistors (FETs) because MoS2 has outstanding electrical properties such as a low subthreshold swing value, a high on/off ratio, and good carrier mobility. In this study, we characterized the electrical and photo-responsive properties of MoS2 FET when stacking a p-type organic copper phthalocyanine (CuPc) layer on the MoS2 surface. We observed that the threshold voltage of MoS2 FET could be controlled by stacking the CuPc layers due to a charge transfer phenomenon at the interface. Particularly, we demonstrated that CuPc/MoS2 hybrid devices exhibited high performance as a photodetector compared with the pristine MoS2 FETs, caused by more electron-hole pairs separation at the p-n interface. Furthermore, we found the optimized CuPc thickness (∼2 nm) on the MoS2 surface for the best performance as a photodetector with a photoresponsivity of ∼1.98 A W(-1), a detectivity of ∼6.11 × 10(10) Jones, and an external quantum efficiency of ∼12.57%. Our study suggests that the MoS2 vertical hybrid structure with organic material can be promising as efficient photodetecting devices and optoelectronic circuits.

Drain Bias Effect on the Instability of Amorphous InGaZnO Thin-Film Transistors under Negative Gate Bias and Illumination Stress

Recently, amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) have been much investigated for their applications due to their excellent electrical properties such as high mobility (μ) and low subthreshold swing (SS) values. However, device reliability under light exposure has been recognized as an issue remaining to be resolved. In this study, the effect of drain bias (V DS) on the negative bias and illumination stress (NBIS) stability of a-IGZO TFTs was investigated. The degradation mechanisms of a-IGZO TFTs under NBIS with different V DSbiases were clarified.The fabrication process of the bottom-gate IGZO TFT was reported in detail elsewhere (1). NBIS was applied with a gate voltage (V GS) of −40 V under blue light (460 nm) at an intensity of 0.2 mW/cm2. The NBIS was temporarily interrupted when the transfer characteristics were measured by a double-sweeping V GS mode in darkness at V DS of 0.1 V, and then NBIS was reapplied up to an accumulated stress time of 104 s. For the double-sweeping V GS mode, transfer characteristics were measured with V GSfrom −10 to 20 V (denoted hereafter as forward measurement), and then scanned instantly back to −10 V (denoted hereafter as reverse measurement).Figure 1 shows the variation in the transfer characteristics under NBIS with grounded V DS for the forward and reverse measurements, respectively. In the initial stage of NBIS (< 1000 s), the transfer curves shifted in the negative V GS direction without SS degradation; on-current degradation was then observed in the subsequent stage (> 1000 s) in the forward measurement. In contrast, for the reverse measurements, the transfer curves hardly shifted within the initial NBIS duration of 1000 s, and then these exhibited a parallel shift in the positive V GS direction without SS degradation with increasing NBIS duration. We considered that the generated donor-like defects, originated from the ionized oxygen vacancies (VO + and/or VO 2+) and contributing to on-current degradation, were stabilized by capturing electrons during the forward measurement, and the trapped holes at the front-channel interface were detrapped by the positive V GSduring the forward measurement (2); therefore, electron trapping at the back-channel interface was an origin of the positive shift of the transfer curve without SS degradation in the subsequent reverse measurement.To investigate the effect of the V DS bias on the NBIS degradation, V DS biases of 40 and −60 V were applied with V GS of −40 V. Figure 2 shows the transfer characteristics in the forward and reverse measurements before and after NBIS duration of 104 s with different V DS biases. NBIS with an additional positive V DS bias of 40 V accelerated the donor-like state creation near the source side because of the positively charged VO + and/or VO 2+ drifting from the drain to the source side under the influence of the lateral electric field, which contributed to more severe on-current degradation. The NBIS degradation was significantly suppressed by applying a large negative V DS bias of −60 V, because the positive charges of VO + and/or VO 2+ were easily neutralized by electrons under the accumulation condition in the drain region. The detailed degradation mechanisms of a-IGZO TFTs under NBIS with various V DSbiases will be presented at the conference.Reference1. D. Wang, M. P. Hung, J. Jiang, T. Toda, C. Li, and M. Furuta, Jpn. J. Appl. Phys., 53, 03CC01 (2014).2. M. P. Hung, D. Wang, J. Jiang, and M. Furuta, ECS Solid State Letters, 3 (3), Q13 (2014).

DC Compact Model for SOI Tunnel Field-Effect Transistors

A physics-based dc compact model for SOI tunnel field-effect transistors (TFETs) has been developed in this paper utilizing Landauer approach. The important transistor electrical parameters, i.e., threshold voltage Vth, charge in the channel Q, gate capacitance CG, drain current IDS, subthreshold swing S, transconductance gm, and output conductance gDS, have been modeled. The model predicts the low subthreshold swing values (less than 60 mV/dec) observed in TFETs and shows a good match with the technology computer aided design (TCAD) results. Model validation was carried out using TCAD simulation for different TFET structures with abrupt junctions, i.e., 40-nm Si nTFET and pTFET, a 0.4-μm Si nTFET, and a 40-nm Ge nTFET. The compact model predictions are in good agreement with the TCAD simulation results.

Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility of 8.7 cm2/Vs was obtained along with an Ion/Ioff ratio of 106. The ferroelectric thin film transistors showed a low sub-threshold swing value of 0.19 V/dec and a significantly reduced device operating voltage (±4 V) compared to the reported hetero-junction ferroelectric transistors, which is very promising for low-power non-volatile memory applications.