Low Standby Power Research Articles

Steep‐Slope IGZO Transistor Monolithically Integrated with Initialization‐Free Ag/Ti/Hf0.8Zr0.2O2 Atomic Threshold Switch

AbstractA steep‐slope In‐Ga‐Zn‐O (IGZO) field‐effect transistor (FET) monolithically integrated with an Ag/Ti/Hf0.8Zr0.2O2 atomic threshold switch (ATS) device is presented, which allows switching below the Boltzmann limit of 60 mV dec−1 at room temperature (25 °C). The low‐temperature processable IGZO FET is combined with the Hf0.8Zr0.2O2‐based ATS device, which featured initialization‐free and low‐voltage switching, to achieve an ultra‐low power device solution with back‐end‐of‐line process compatibility (≤400 °C). To further assess the potential of the ATS‐IGZO FET devices for circuit applications, they are applied to logic and memory integrated circuits. Inverter ring oscillator simulations are performed to investigate the relationship between switching speed and power consumption. In addition, static random‐access memory simulations are performed to verify that ATS‐IGZO FETs can achieve a stable noise margin along with low standby power consumption. This comprehensive evaluation provides an in‐depth assessment of the applicability of ATS‐IGZO FETs for ultra‐low power logic and memory applications, highlighting their potential for substantial performance improvements.

Broadband ultraviolet photodetector based on rare-earth metal oxide Nd2O3

The detection of ultraviolet (UV) radiation holds significant importance in various fields. As the demand for superior detector performance grows alongside advancements in science and technology, there is a need for detectors with larger light-to-dark rejection ratios and lower standby power consumption. This paper presents the outstanding performance of the rare earth metal oxide Nd2O3 in broadband UV detection. With a wide forbidden band width of 4.6 eV, eliminating the requirement for additional filters, Nd2O3 emerges as an ideal material for broadband UV detectors. The device exhibits remarkable characteristics, including a dark current of only 1.66 × 10−11 A at a 5 V bias voltage, a light-to-dark rejection ratio of 1.33 × 103 at 280 nm and 15 μW cm−2, a responsiveness of 0.061 A W−1, and a detection rate of 4.7 × 1012 Jones. Furthermore, the performance of the device can be significantly enhanced through the formation of a heterojunction with TiO2. The heterojunction device exhibits a shortened response time of 78.64%, a reduced recovery time of 88.97%, and an increased light-to-dark rejection ratio of 2.75 × 103 at a 5 V bias voltage. This significant improvement in performance highlights the potential of the Nd2O3/TiO2 heterojunction in broadband UV detection.

Electrical characteristics assessment and noise analysis of pocket-doped multi source T-shaped gate tunnel FET

A detailed analysis of a novel multi-source T-shaped gate Tunnel FET (MS-TTFET) is presented in this study in order to address the main issues with conventional TFETs. Due to its exceptionally low off-state current (IOFF) and remarkable sub-threshold properties, the tunnel field effect transistor has received a great deal of interest for low standby power applications. The MSR's integration into the SOI platform increases the device's on current, which increases the effective tunnelling area in the middle of the source-channel junctions. An isolator oxide has been added to prevent the source and drain regions from being directly coupled. A SiGe pocket has been suggested at the source and channel junction; silicon-germanium, a low bandgap material which enhances the tunnelling of charge carriers. A T-shaped gate can increase the effectiveness of the tunnel junction in order to limit the lower value of the leakage current. The multi-source regions of the T-shaped gate tunnel field effect transistor can boost the on-state current (ION) by improving tunnel junction areas. The device's ION/IOFF ratio, which is 1013 for our suggested construction, is the standard measure of merit for any device. It is possible to achieve an increased ON current of the order of 10−5 A/μm with a negligible subthreshold swing (SS) of 42 mV/decade. Moreover, the effect of low frequency flicker noise on the device behavior has been investigated.

Single-Power-Supply Six-Transistor CMOS SRAM Enabling Low-Voltage Writing, Low-Voltage Reading, and Low Standby Power Consumption

We developed a self-controllable voltage level (SVL) circuit and applied this circuit to a single-power-supply, six-transistor complementary metal-oxide-semiconductor static random-access memory (SRAM) to not only improve both write and read performances but also to achieve low standby power and data retention (holding) capability. The SVL circuit comprises only three MOSFETs (i.e., pull-up, pull-down and bypass MOSFETs). The SVL circuit is able to adaptively generate both optimal memory cell voltages and word line voltages depending on which mode of operation (i.e., write, read or hold operation) was used. The write margin (VWM) and read margin (VRM) of the developed (dvlp) SRAM at a supply voltage (VDD) of 1 V were 0.470 and 0.1923 V, respectively. These values were 1.309 and 2.093 times VWM and VRM of the conventional (conv) SRAM, respectively.At a large threshold voltage (Vt) variability (=+6σ), the minimum power supply voltage (VMin) for the write operation of the conv SRAM was 0.37 V, whereas it decreased to 0.22 V for the dvlp SRAM. VMin for the read operation of the conv SRAM was 1.05 V when the Vt variability (= -6σ) was large, but the dvlp SRAM lowered it to 0.41 V. These results show that the SVL circuit expands the operating voltage range for both write and read operations to lower voltages. The dvlp SRAM reduces the standby power consumption (PST) while retaining data. The measured PST of the 2k-bit, 90-nm dvlp SRAM was only 0.957 μW at VDD = 1.0 V, which was 9.46% of PST of the conv SRAM (10.12 μW). The Si area overhead of the SVL circuits was only 1.383% of the dvlp SRAM.

A Compact Auxiliary Power Supply Design for a Medium Frequency Solid State Transformer

The design of auxiliary power supply (APS) in solid-state transformers (SSTs) is quite challenging. To minimize the isolation requirement, this APS is usually powered by dc-link capacitors. However, it poses voltage unbalance issues when the main converter is not in operation. To address this problem, a compact and cost-effective APS design is proposed, which utilizes the isolation structure of main medium-frequency transformers (MFTs). The proposed APS system also provides half-duplex communication, which replaces the costly optical fiber system. The interference between main and auxiliary power transfer links has been significantly reduced by the decoupled transformer design and the dual-band scheme for inductor-inductor-capacitor (LLC) and inductor-capacitor-inductor-capacitor (LCLC) converters. In addition, a new startup strategy with a low standby power is applied to this APS system. A 3.2-kW SST prototype with a peak efficiency of 97.9% has been built, whose APS is 6 W. The experimental results verify the feasibility and performance of the proposed techniques.

A Novel Structured Single Device Neuron for Low Standby Power and Compact System Application

We propose a single device neuron that utilizes a ferroelectric layer, a split gate, and a truncated floating gate structure. The proposed neuron device, named Single-Device Leaky-FeFET (SD L-FeFET), successfully emulates the neuronal dynamics for both excitatory and inhibitory connections while reducing the standby power by eliminating tail current. A spiking neural network (SNN) using the newly developed SD L-FeFET neuron shows MNIST handwriting digit pattern recognition of 92.5% and face recognition of 91.7%, which is comparable performance to the state-of-art SNN simulation results using conventional complex cell designs.

Investigation of Source/Drain Recess Engineering and Its Impacts on FinFET and GAA Nanosheet FET at 5 nm Node

Impacts of source/drain (S/D) recess engineering on the device performance of both the gate-all-around (GAA) nanosheet (NS) field-effect transistor (FET) and FinFET have been comprehensively studied at 5 nm node technology. TCAD simulation results show that the device off-leakage, including subthreshold leakage through the channel (Isub) and punch-through leakage (IPT) in the sub-channel, is strongly related to the S/D recess process. Firstly, device electrical characteristics such as current density distributions, On/Off-state current (Ion, Ioff), subthreshold swing (SS), RC delay, and gate capacitance (Cgg) are investigated quantitatively for DC/AC performance evaluation and comparison according to S/D lateral recess depth (Lrcs) variations. For both device types, larger Lrcs will result in a shorter effective channel length (Leff), so that the Ion and Ioff simultaneously increase. At the constant Ioff, the Lrcs can be optimized to enhance the device’s drivability by ~3% and improve the device’s RC delay by ~1.5% due to a larger Cgg as a penalty. Secondly, S/D over recess depth (Hrcs) in the vertical direction severely affects the punch-through leakage in the Sub-Fin or bottom parasitic channel region. The NSFET exhibits less Ioff sensitivity provided that it can be well controlled under 12 nm since the bottom parasitic channel is still gated. Furthermore, with both Hrcs and Lrcs accounted for in the device fabrication, the NSFET still shows better control of the off-leakage in the intrinsic and bottom parasitic channel regions and ~37% leakage reduction compared with FinFETs, which would be critical to enable further scaling and the low standby power application. Finally, the S/D recess engineering strategy has been given: a certain lateral recess could be optimized to obtain the best drive current and RC delay, while the vertical over-recess should be in tight management to keep the static power dissipation as low as possible.

MC-CIM: Compute-in-Memory With Monte-Carlo Dropouts for Bayesian Edge Intelligence

We propose MC-CIM, a compute-in-memory (CIM) framework for robust, yet low power, Bayesian edge intelligence. Deep neural networks (DNN) with deterministic weights cannot express their prediction uncertainties, thereby pose critical risks for applications where the consequences of mispredictions are fatal such as surgical robotics. To address this limitation, Bayesian inference of a DNN has gained attention. Using Bayesian inference, not only the prediction itself, but the prediction confidence can also be extracted for planning risk-aware actions. However, Bayesian inference of a DNN is computationally expensive, ill-suited for real-time and/or edge deployment. An approximation to Bayesian DNN using Monte Carlo Dropout (MC-Dropout) has shown high robustness along with low computational complexity. Enhancing the computational efficiency of the method, we discuss a novel CIM module that can perform in-memory probabilistic dropout in addition to in-memory weight-input scalar product to support the method. We also propose a compute-reuse reformulation of MC-Dropout where each successive instance can utilize the product-sum computations from the previous iteration. Even more, we discuss how the random instances can be optimally ordered to minimize the overall MC-Dropout workload by exploiting combinatorial optimization methods. Application of the proposed CIM-based MC-Dropout execution is discussed for MNIST character recognition and visual odometry (VO) of autonomous drones. The framework reliably gives prediction confidence amidst non-idealities imposed by MC-CIM to a good extent. Proposed MC-CIM with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16\times 31$ </tex-math></inline-formula> SRAM array, 0.85 V supply, 16nm low-standby power (LSTP) technology consumes 32 pJ for 30 MC-Dropout instances of probabilistic inference in its most optimal computing and peripheral configuration, saving <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 34$ </tex-math></inline-formula> % energy compared to typical execution.

Continuous-Time Analog Filters for Audio Edge Intelligence: Review on Circuit Designs [Feature

Edge audio devices can reduce data bandwidth requirements by pre-processing input speech on the device before transmission to the cloud. As edge devices are required to ensure always-on operation, their stringent power constraints pose several design challenges and force IC designers to look for solutions that use low standby power. One promising bio-inspired approach is to combine the continuous-time analog filter channels with a small memory footprint deep neural network that is trained on edge tasks such as keyword spotting, thereby allowing all blocks to be embedded in an IC. This paper reviews the historical background of the continuous-time analog filter circuits that have been used as feature extractors for current edge audio devices. Starting from the interpretation of a basic biquad filter as a two-integrator-loop topology, we introduce the progression in the design of second-order low-pass and band-pass filters ranging from OTA-based to source-follower-based architectures. We also derive and analyze the small-signal transfer function and discuss their usage in edge audio applications.

Digital Voltage Sampling Scheme for Primary-Side Regulation Flyback Converter in CCM and DCM Modes

Primary-side regulation (PSR) flyback topology with discontinuous conduction modulation (DCM) mode has been widely used in low-power application due to its high stability, wide input voltage range, low cost, and low standby power. To improve the output power, continuous conduction modulation (CCM) mode is always introduced. However, in CCM mode, conventional PSR voltage-sampling method cannot realize high precision of output voltage or the voltage sampling method requires complex control of high cost. In this paper, a simple digital voltage sampling scheme with two reference voltages outputted from a digital-to-analog converter (DAC) is put forward to trace the “accurate-point” voltage for DCM and CCM modes. In CCM mode, the sampling voltage error of the “knee-point” voltage can be compensated just by inserting DCM switching cycle to obtain the “accurate-point” voltage. Voltage difference between DCM mode and CCM mode will be eliminated, and high precision is easily realized. The proposed method is verified in a 20V, 65W PSR flyback converter. The sampling method only requires a low speed DAC, three comparators and a digital controller. The output voltage precision is within 0.6% with universal input voltage.

Quantum Tunneling Based Ultra-Compact and Energy Efficient Spiking Neuron Enables Hardware SNN

Low-power and low-area neurons are essential for hardware implementation of large-scale SNNs. Various novel-physics-based leaky-integrate-and-fire (LIF) neuron architectures have been proposed with low power and area, but are not compatible with CMOS technology to enable brain scale implementation of SNN. In this paper, for the first time, we demonstrate hardware implementation of recurrent SNN using proposed low-power, low-area, and low-leakage band-to-band-tunneling (BTBT) based neurons. A low-power thresholding circuit is proposed. We further propose a predistortion technique to linearize a nonlinear neuron without any area and power overhead. We establish the equivalence of the proposed neuron with the ideal LIF neuron to demonstrate its versatility. The tunneling regime enables a high input impedance in the BTBT neurons (few <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{G}\Omega$ </tex-math></inline-formula> ) to enable a voltage input without loading the synaptic array. To verify the effect of the proposed neuron, a 36-neuron recurrent SNN is fabricated in GF-45nm PDSOI technology. We achieved 5000x lower energy-per-spike at a similar area and 10x lower standby power at a similar area and energy-per-spike. Such overall performance improvement enables brain scale computing.

Design and Simulation of Content-Aware Hybrid DRAM-PCM Memory System

Phase Change Memory (PCM) can directly connect persistent memory to main memory bus, while it achieves high read throughput and low standby power, the critical concerns are its poor write performance and limited durability. A naturally in-spired design is the hybrid memory architecture that fuses DRAM and PCM, so as to exploit the positive aspects of both types of memory. Unfortunately, existing solutions are seriously challenged by the limited main memory size, which is the primary bottleneck of in-memory computing. In this paper, we introduce a novel Content Aware Hybrid DRAM-PCM memory system framework—CAHRAM, which exploits deduplication to improve line sharing with high memory efficiency. It reduces write traffic to hybrid memory by removing unnecessary duplicate line writes, thereby further enhancing the write endurance of PCM. And it also substantially extends available free memory space by coalescing redundant lines in hybrid memory. We also design a reference-based page migration technique to minimize the access overheads caused by the performance gap between DRAM and PCM. Compared with the state-of-the-art in a hybrid memory simulator, our experiment results show that CAHRAM can achieve the highest I/O performance and the longest PCM lifetime with the competitive efficiencies in space and energy.

A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins

This paper explores a low standby power 10T (LP10T) SRAM cell with high read stability and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross-coupled structure consisting standard inverter with a stacked transistor and Schmitt-trigger inverter with a double-length pull-up transistor. This along with the read path separated from true internal storage nodes eliminates the read-disturbance. Furthermore, it performs its write operation in pseudo differential form through write bitline and control signal with a write-assist technique. To estimate the proposed LP10T SRAM cell’s performance, it is compared with some state-of-the-art SRAM cells using HSPICE in 16-nm CMOS predictive technology model at 0.7 V supply voltage under harsh manufacturing process, voltage, and temperature variations. The proposed SRAM cell offers 4.65X/1.57X/1.46X improvement in RSNM/WSNM/WM and 4.40X/1.69X narrower spread in RSNM/WM compared to the conventional 6T SRAM cell. Furthermore, it shows 1.26X/1.08X/1.01X higher RSNM/WSNM/WM and 1.71X/1.25X tighter/wider spread in RSNM/WM compared to the best studied SRAM cells. The proposed SRAM cell indicates 74.48%/1.41% higher/lower read/write delay compared to the 6T SRAM cell. Moreover, it exhibits the third-(second-) best read (write) dynamic power, consuming 29.69% (26.87%) lower than the 6T SRAM cell. The leakage power is minimized by the proposed design, which is 37.35% and 12.08% lower than that of the 6T and best studied cells, respectively. Nonetheless, the proposed LP10T SRAM cell occupies 1.313X higher area compared to the 6T SRAM cell.

A write-optimal and concurrent persistent dynamic hashing with radix tree assistance

Non-volatile memory (NVM) is expected to coexist with DRAM as a hybrid memory to fully exploit DRAM’s low read–write latency and NVM’s high density, persistence, and low standby power. However, existing persistent hashing schemes cannot efficiently reap the hybrid-memory benefits, and suffer from a significant performance penalty due to consistency guarantee. In this paper, we present an optimized extendible hashing variant for hybrid DRAM-NVM memory, named OP-HMEH. In our design, hash buckets are persisted in NVM while the directory is placed in DRAM for faster access. We also keep a radix-tree-structured directory in NVM to instantaneously recover the directory in DRAM after system crashes. To reduce consistency guarantee overhead, OP-HMEH designs a cross-KV mechanism to reorganize items which can avoid the use of expensive persist barriers in most cases. Meanwhile, we employ low-overhead structural modification operations schemes to further improve system performance. For concurrency control, the original version uses two lock-based techniques. We then propose an optimistic concurrency strategy that exploits lightweight locking to protect segments and enables lock-free search/operations of directories by leveraging atomic instructions. On real Intel Optane DCPMM, experimental results with YCSB workloads show that our OP-HMEH outperforms the state-of-the-art NVM-based hashing structures by up to 2.18×. The optimized HMEH obtains higher insert performance than the original HMEH.

Analytical modeling and TCAD simulation for subthreshold characteristics of asymmetric Tunnel FET

In this paper, a 2-D analytical model has been developed for asymmetric Tunnel FET known as Non-Uniform Body with Dual Material Source TFET (NUTFET-DMS) Device. The proposed model formulation is based on the solution of Poisson’s equation using suitable boundary conditions. The derived model for subthreshold characteristics is proposed for numerous device parameters such as surface potential, lateral, vertical electric fields, drain current and threshold voltage. In this work, for the first time the model accounts the prodigious non-uniform nature of the Channel, Gate Dielectric Thickness, Dielectric Constants and Oxide Capacitance, at different portions of the device. Next, to validate the accuracy of the model, device simulation using Sentaurus TCAD with calibrated models is reported and a close agreement with 85–95% accuracy is observed. The detailed and systematic device analysis is presented by studying different cases of applied biases, variation of device dimensions, oxide materials etc. It is reported that the proposed TFET device is able to obtain a vertical and lateral electric field of ± 5 MV/cm near the tunneling junction, implying a drain current in the order of 10−5A/μm. The present study highlights that the proposed TFET offers great potential for low standby power logic and low power applications.

Reliability improvement of IGZO‐TFT in hybrid process with LTPS

AbstractAn AMOLED panel using hybrid backplane technology based on p‐type low temperature polycrystalline silicon (p‐LTPS) and n‐type indium–gallium–zinc–oxide (n‐IGZO) thin‐film transistors (TFTs) has been successfully manufactured. New pixel and Gate‐on‐Array (GOA) circuits were designed and fabricated using this technology. GOA with CMOS inverter is realized by utilizing both IGZO and p‐LTPS. The hybrid backplane AMOLED panel can operate between 1 and 120 Hz, which enables both high refresh rate and low standby power display applications. Furthermore, the AMOLED panel lifetime has markedly enhanced by improving IGZO TFT's uniformity and reliability.

7‐1: Distinguished Paper: Reliability Improvement of IGZO‐TFT in Hybrid Process with LTPS

An AMOLED panel using hybrid backplane technology based on p‐type LTPS and n‐type oxide has been successfully manufactured. New pixel and Gate‐on‐Array (GOA) circuits were designed and fabricated using this technology. CMOS operation of the GOA is realized by utilizing both IGZO and p‐LTPS. The hybrid backplane AMOLED panel can operate between 1 Hz and 120 Hz, which enables both high refresh rate and low standby power display applications. Furthermore, the AMOLED panel lifetime has markedly enhanced by improving IGZO TFT's uniformity and reliability.

Design of low power, variation tolerant single bitline 9T SRAM cell in 16-nm technology in subthreshold region

The major design parameters of embedded cache memory (SRAM memory cell) are speed, power consumption, noise tolerance, and reliability. It is a challenging task to design an SRAM cell in the face of process, voltage, and temperature variations at low supply voltages. At scaled technology node the conventional 6T SRAM cell suffers from read and write failures as well as instability. Moreover, it is susceptible to multibit soft error rate since it does not support bit-interleaving architecture. This paper proposes a low-power robust single bitline 9T (nine transistor) SRAM (Static Random Access Memory) at a 16-nm technology node in the subthreshold region. The potency of the proposed cell is shown by comparing it with other recently published SRAM cells, namely, single-ended NTV 9T (SENTV9T), write and read enhanced 9T (WREN9T), and the conventional 6T (CONV6T) SRAM cells. The proposed cell provides 1.25×/1.96 × lower read current IREAD variability compared with WREN9T/SENTV9T. The proposed cell achieves 4.23 × higher noise tolerance capability (i.e., read static noise margin (RSNM)) during read operation compared with CONV6T due to the fact that it employs read decoupled operation. Moreover, SBL9T consumes lower standby power during hold state and dynamic power in the active state as compared with SENTV9T, WREN9T, and CONV6T. SBL9T also exhibits 10.01×/8.65×/11.47× narrower spread in standby power compared with CONV6T/WREN9T/SENTV9T. The dynamic power spread shows a similar trend with SBL9T providing 1.97×/1.02× narrower spread in dynamic power compared with WREN9T/SENTV9T. These benefits however are achieved by the SBL9T at the cost of 1.28×/0.71×/1.01× longer read delay compared with CONV6T/WREN9T/SENTV9T.

Design of a Memory Array Using Tail Transistor and Sleep Transistor Based 7T SRAM with Low Short Circuit and Standby Power

The display hardware concentrates on planning low power control gadgets due to the utilization of versatile battery-powered gadgets. Ultra low energy process of memory clusters has ended up undying due to its uses in low voltage calculation and communications. Stable SRAM process is valuable for the success of low-power due to parameter variations in scale-down technologies. In expansion to control utilization, the SRAM’s get to time is another complex parameter due to the inevitable exchanging exercises utilized for distinctive squares, say SRAM cell, get to NMOS transistors, NMOS preload transistors, a yield sense enhancer and both decoders. It has been appeared that the tail transistor-based 6T SRAM cluster comes up short to realize solid standby control and less delay process. The proposed inactive arbitrary get to memory (SRAM) plan gives an approach towards diminishing the standby control scattering. The design uses a sleep transistor which helps in limiting the standby power by preventing the whole cell from working for unwanted operations. It is eligible for low power applications due to the supply voltage being 1.8V. The designed SRAM cell has single-ended write and reads operations, which can also reduce the total power dissipation and the tail transistor reduces the short circuit energy consumption. The design is verified with Cadence (45nm) and the power estimated as 4.6789pW, which is 78.2% of ordinary 6T SRAM block.

Low-power LDO Design of High-efficiency Class AB OTA Based on Adaptive Biasing

This design proposes a new low-dropout linear regulator (LDO) with low input voltage and low standby power consumption. A new type of adaptive bias circuit is proposed, which uses a high-efficiency class AB OTA based on class AB differential input stage and local common mode feedback (LCMFB), which not only increases the gain bandwidth product (GBW), but also improves current efficiency, in addition, a dynamic charging transistor (DCT) is used to enhance the transient characteristics of the circuit. The circuit design uses 0.18μm standard CMOS technology to achieve a stable output of 1.0V after the power supply voltage is adjusted from 1.2V, and the maximum output current is 100mA. The quiescent current is only 2.3μA at no-load, when the load current is converted from 1mA to 100mA within 1μs, the overcharge voltage is less than 130mV, and the full range of load current stability from 1mA to 100mA is achieved under the maximum 100pF load capacitor.