Low-power Receiver Research Articles

Massive MIMO a Candidate Technology for Future Generation Wireless Communication System

The demands of wireless communication systems are continuously growing as users are increasing day-by-day. In our modern society, high data-rate, very low power consumption transmitter, simple transmitter and receiver, and very high quality of services are mostly needed. To meet above-mentioned demands massive multiple input multiple output (MIMO) is the only technology which may cater this demand as this technology is equipped with a large amount of base station (BS) antennas at the transmitter. It is only promising technology to offer higher data-rate in large coverage.

A 6-9 GHz 1.28 Gbps 76 mW Amplitude and Synchronized Time Shift Keying IR-UWB CMOS Transceiver for Brain Computer Interfaces.

This paper proposes a low-power, high-speed impulse radio-ultra-wideband (IR-UWB) transceiver for brain computer interfaces (BCIs) using amplitude and synchronized time shift keying technique (ASTSK). The proposed IR-UWB transmitter (Tx) generates two pulses (sync pulse and data pulse) per symbol rate. The time difference between two pulses is used for synchronized time shift keying and the amplitude of the two pulses is used for amplitude shift keying. The receiver (Rx) demodulates the time difference with a low power time-to-digital converter (TDC) and peak detector (PD) based amplitude demodulation is suggested to relax analog-to-digital converter (ADC) burden for low power receiver. Especially the Tx-based synchronized operation eliminates the need for complex clock circuitry such as phase-lock loop (PLL) and reference crystal oscillator. Therefore, it can achieve low power and high-speed operation. The prototype, fabricated in 65 nm CMOS, has a frequency range of 6-9 GHz, communication speed of 1.28 Gbps, and power consumption of 18 mW (Tx) and 58 mW (Rx). This work is a fully integrated RF transceiver adapted for high-order modulation and designed to include the receiver.

Toward Zero-Energy Devices: Waveform Design for Low-Power Receivers

The use of a low-power wake-up receiver (WUR) can significantly reduce the device’s energy consumption. To incorporate such WURs into existing communication systems, the waveform design needs to facilitate simple detection yet be compatible with the orthogonal frequency division multiplexing (OFDM) transmission. In this letter, we propose a novel phase design for the wake-up signal (WUS) so that the time-domain distortion of the WUS can be minimized. A majorization-minimization (MM) method is proposed to address the waveform design problem. Simulations show that the proposed scheme can achieve a near-optimal detection performance under different system parameters.

A Sub-GHz Low-Power Receiver Employing Resistive-Feedback-Tuned LNA With 2.1-dB NF and 106-dB Gain Tuning Range

This letter presents a configurable sub-GHz low-power receiver achieving a low noise figure (NF) and a large gain tuning range. An inverter-based low-noise amplifier (LNA) with a resistive-feedback-tuning technique is realized to achieve low power and optimize NF while tuning the gain level. Implemented in 130-nm CMOS technology, this receiver occupies an active area of 2.3 mm2. It achieves a low power of 3.63 mW over a large gain tuning range of 106 dB in 6 dB steps. It also achieves a low NF of 2.1 dB and an image rejection ratio (IRR) of over 37.1 dB.

Mid-wave infrared optical receiver based on an InAsSb-nBn photodetector using the barrier doping engineering technique for low-power satellite optical wireless communication.

This paper proposes a new nBn photodetector (nBn-PD) based on InAsSb with a barrier doping engineering technique [core-shell doped barrier (CSD-B) nBn-PD] for utilization as a low-power receiver in satellite optical wireless communication (Sat-OWC) systems. In the proposed structure, the absorber layer is selected from an I n A s 1-x S b x (x=0.17) ternary compound semiconductor. The difference between this structure and other nBn structures is the placement of the top and bottom contacts in the form of a PN junction, which increases the efficiency of the proposed device through the creation of a built-in electric field. Also, a barrier layer is placed from the AlSb binary compound. The presence of the CSD-B layer with the high conduction band offset and very low valence band offset improves the performance of the proposed device compared to conventional PN and avalanche photodiode detectors. By applying -0.1V bias at 125K, the dark current is demonstrated at 4.31×10-5 A/c m 2 by assuming high-level traps and defect conditions. Examining the figure of merit parameters under back-side illumination with a 50% cutoff wavelength of 4.6µm shows that at 150K, the responsivity of the CSD-B nBn-PD device reaches about 1.8A/W under 0.05W/c m 2 light intensity. Regarding the great importance of using low-noise receivers in Sat-OWC systems, the results indicate that the noise, noise equivalent power, and noise equivalent irradiance are calculated as 9.98×10-15 A H z -1/2, 9.21×10-15 W H z 1/2, and 1.02×10-9 W/c m 2, respectively, at -0.5V bias voltage and 4µm laser illumination with the influence of shot-thermal noise. Also, D ∗ obtains 3.26×1011 c m H z 1/2/W without using the anti-reflection coating layer. In addition, since the bit error rate (BER) plays an essential role in the Sat-OWC systems, the effect of different modulations on the BER sensitivity of the proposed receiver is investigated. The results represent that the pulse position modulation and return zero on-off keying modulations create the lowest BER. Attenuation is also investigated as a factor that significantly affects BER sensitivity. The results clearly express that the proposed detector provides the knowledge to achieve a high-quality Sat-OWC system.

SnapperGPS: Open Hardware for Energy-Efficient, Low-Cost Wildlife Location Tracking with Snapshot GNSS

Location tracking with global navigation satellite systems (GNSS), such as the GPS, is used in many applications, including the tracking of wild animals for research. Snapshot GNSS is a technique that only requires milliseconds of satellite signals to infer the position of a receiver. This is ideal for low-power applications such as animal tracking. However, there are few existing snapshot systems, none of which is open source. To address this, we developed SnapperGPS, a fully open-source, low-cost, and low-power location tracking system designed for wildlife tracking. SnapperGPS comprises three parts, all of which are open-source: (i) a small, low-cost, and low-power receiver; (ii) a web application to configure the receiver via USB; and (iii) a cloud-based platform for processing recorded data. This paper presents the hardware side of this project. The total component cost of the receiver is under $30, making it feasible for field work with restricted budgets and low recovery rates. The receiver records very short and low-resolution samples resulting in particularly low power consumption, outperforming existing systems. It can run for more than a year on a 40 mAh battery. We evaluated SnapperGPS in controlled static and dynamic tests in a semi-urban environment where it achieved median errors of 12 m. Additionally, SnapperGPS has already been deployed for two wildlife tracking studies on sea turtles and sea birds.

Interactive Effects of Receiver Power and Generator Status on Endorsement of Creative Ideas

Few studies have focused on how power influences an idea receiver's endorsement of creative ideas. By integrating associative evaluation theory with insights from the power literature, we identify power as an important receivers’ factor that accentuates the relation between an idea's creativity level and receivers’ endorsement. We contend that the idea generator's status is a boundary condition and, together with creativity level, the idea generator's status jointly influences the degree to which idea receivers’ power affects idea endorsement. We conducted four studies to test our hypotheses. Study 1 was a laboratory experiment. It found a two-way interaction of receiver power and creativity level, showing that compared to low-power receivers, high-power receivers expressed stronger endorsement of ideas with high levels of creativity. Study 2 was a field study in a manufacturing company. It replicated Study 1's findings and further found a three-way interaction showing that the moderating effect of receiver power was strengthened when the generator had higher rather than lower status. Studies 3 and 4 respectively replicated the two-way and three-way interactions using experiments and demonstrated positive associations as the theorized mediator, providing empirical support for the positive association account. We discuss implications of these studies and call for future research to deepen our understanding of how creative ideas are endorsed in the workplace.

A Novel 61.25 GHz Monostatic CMOS Interrogator for Batteryless Backscattering RFID Solutions

This article presents the analysis, design, and characterization of a 61.25 GHz radio frequency identification (RFID) interrogator. Monostatic RFID systems have to solve the challenge of the transmit (TX)-to-receive (RX) leakage, which could desensitize the interrogator. Instead of suppressing or canceling this leakage, the interference of the transmitted and incident waves is exploited to demodulate the incident signal. The structure can be inserted between the power amplifier (PA) and the antenna pad of existing transmitters. It has a lower insertion loss (IL) than other ON-chip isolation structures used in monostatic interrogators reported to date. The transceiver front-end was fabricated on a 22 nm fully depleted silicon on insulator (FD-SOI) technology, and has a simple structure, where the low-power receiver requires 0.022 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area. The die was mounted on a radio frequency (RF) printed circuit board (PCB) and a general circuit board was used for baseband processing in the measurements.

Link-Level Wideband Signal Shaping for Downlink Wireless Information and Energy Provision

In an indoor environment rich in scatterers, wideband signals sent by a transmitter create multiple resolvable transmission paths towards a low-power receiver. Therefore, spatial gains can be exploited for increasing the performance of wireless information and energy provision without implementing multiple antennas. The transmit signal shaping vector at the transmitter and the power splitting ratio at the receiver is jointly optimised for maximising the attainable information throughput, while satisfying the receiver’s requirement on the harvested direct current (DC). The numerical results demonstrate the advantage of our design over a time-reversal counterpart and a uniform counterpart.

CMOS-Driven VCSEL-Based Photonic Links: an Exploration of the Power-Sensitivity Trade-Off

This article explores the power-sensitivity trade-off in optical receivers aiming to improve the energy-efficiency of the overall link. Optical receivers with field-effect transistor (FET) front-ends (FEs) are usually designed for optimal noise performance by matching the circuit&#x2019;s input capacitance (<i>C_I</i>) to the total input parasitic capacitance (<i>C_D</i>). However, the receiver&#x2019;s power dissipation is also proportional to the input capacitance <i>C_I</i>. Therefore, this paper studies the feasibility of the capacitive matching rule in the context of minimizing the power dissipation of the overall link. For that purpose, design trade-offs for the receiver, transmitter, and the overall link are presented. Comparisons are made to study how much the receiver can be downsized, sacrificing optimal noise performance, before its power reduction is offset by the transmitter&#x2019;s increase in power. Simulation results show that energy-efficient links require low-power receivers with input capacitance much smaller than that required for noise-optimum performance. As an example, for a 25 Gb/s operation, an optical loss budget of 12.6 dB, and a receiver designed in 65 nm CMOS technology with <i>C_D</i> of 200 fF, the overall link dissipates 2.55 pJ/bit when the receiver&#x2019;s noise is minimized, leading to a receiver with <i>C_I</i>/<i>C_D</i> = 1.29. When optimized for overall link efficiency, the receiver size is significantly reduced to <i>C_I</i>/<i>C_D</i> = 0.38 and the link&#x2019;s energy-efficiency also improves to 1.41 pJ/bit. If the link budget or knowledge of the transmitter side is incomplete, our analysis indicates that maximizing gain with value of <i>C_I</i>/<i>C_D</i> = 0.5 is a reasonable choice.

2.4 GHz Low-power Receiver Front-end Employing I/Q Mixer with Current-reused Quadrature Transconductor for Bluetooth Low Energy Applications

In this paper, a 2.4 GHz Bluetooth low energy (BLE) receiver front-end with a new inphase/quadrature (I/Q) down-conversion active mixer employing a current-reused quadrature transconductor is presented for low-power low-voltage Internet of Things applications. In the proposed I/Q mixer, the current-bleeding circuit, whose main role is to reduce the flicker noise in the switching stage, enhances the overall transconductance and provides quadrature signals with the main quadrature transconductor. Consequently, it improves the conversion gain and noise figure of the mixer without additional power consumption. The proposed BLE receiver front-end consists of a current-reused push-pull low-noise amplifier and an I/Q mixer with a current-reused quadrature transconductor. Simulated in a 65 nm CMOS process, the designed receiver front-end achieves a noise figure of 3.3 dB, conversion gain of 37.6 dB, and input-referred third-order intercept point of -22.73 dBm. It draws a bias current of 1 mA from a nominal supply voltage of 1 V. The active die area is 0.5 mm².

A 20-Gb/s charge-steering equalizer utilizing highly-efficient charge-steering linear equalizer

The need for high-speed low-power receivers has grown due to the large increase in data rates and Internet-of-Things (IoT) applications. Equalizer-based receivers contain mainly two types of equalizers; Continuous-Time-Linear-Equalizers (CTLE) and non-linear equalizers implemented as Decision-Feedback-Equalizers (DFE). Many solutions have been introduced in the literature to enhance the power consumption of DFEs by using time interleaving or charge-steering. Still, the CTLE power consumption remains considerable a big portion of the overall power of the equalizer-based receivers. The CTLE function cannot be neglected as it equalizes the pre-cursors. This paper presents a low-power charge-steering based receiver that consists of a 1/8-rate charge-steering DFE integrated with a newly proposed Charge-Steering-Linear-Equalizer (CSLE). The proposed CSLE is explained qualitatively and quantitatively. The entire receiver chain consumes 2.9-mW running from a 0.9-V supply and can compensate for 14-dB channel loss at Nyquist-rate when processing 20-Gb/s data.

A 2.4 GHz receiver with a current-reused inductor-less noise-canceling balun LNA in 40 nm CMOS

A low power receiver is designed and implemented for 2.4 GHz Industrial-Scientific-Medical (ISM) band in a 40 nm CMOS process. To obtain good noise and linearity performance at low cost, a current-reused low power inductor-less balun low noise amplifier (LNA) structure is proposed without use of monolithic spiral inductors or transformers. The receiver adopts a zero-IF architecture and current mode mixing operation which avoid need of large voltage headroom for the radio frequency (RF) voltage swing under strong interferers. A third order active-RC low pass filter (LPF) with RC calibration and DC offset cancelation (DCOC) blocks are carefully designed. Current reusing technique and timing optimized asynchronous SAR logic are adopted in LNA and ADC design respectively, featuring high-power efficiency. The total receiver chain achieves maximum conversion gain of 80.32 dB, noise figure (NF) of 6.27 dB and input referred third-order intercept point (IIP3) of −0.6 dBm with 32.8 mW power consumption.

Instinctual Interference-Adaptive Low-Power Receiver With Combined Feedforward and Feedback Control

Highly adaptive, instinctively interference-tolerant radio frequency (RF) receivers are in high demand today. To achieve high-interference robustness at low average power, receivers need to be dynamically configured to operate in low-power mode in the absence of interference and a high-power interference-tolerant mode as an “instinctual” response to the blocker. In this letter, we present an interference-adaptive receiver with a control loop and on-board commercial off-the-shelf (COTS) components that adapt a 2–6-GHz low-noise amplifier (LNA) from a low-power mode (−10-dBm $P_{\text {1 dB,IN}}$ and $\approx 280$ -mW power) to high-linearity mode (1.5-dBm $P_{\text {1 dB,IN}}$ and $\approx 1.4$ -W power) where the linearity is increased by 11.5 dB ( $> 14\times $ ) with a $5\times $ increase in consumed power. With no interference, the control loop automatically brings the LNA back to the low-power mode.

A Dual-Mode Wi-Fi/BLE Wake-Up Receiver

This article presents a dual-mode wake-up receiver (WuRX) compatible with both Bluetooth-Low-Energy (BLE) and Wi-Fi transmitters. The proposed WuRX achieves the state-of-the-art power (as low as 4.4 μW through a latency-power duty-cycled tradeoff), sensitivity (as low as -92 dBm), and interference resilience (signal-to-interference ratio (SIR) =-67 dB) via a carefully architected frequency plan that supports BLE advertisement channel hopping or a proposed subcarrier-based within-channel Wi-Fi frequency hopping scheme, a carefully crafted frequency down-conversion plan that enables low-power receiver architecture via integer- N arithmetic, and an on-chip image rejection filter for full on-chip integration. The proposed design is implemented in a 65-nm CMOS process and operates from a 0.5-V supply.

A 130 nm-SiGe-BiCMOS Low-Power Receiver Based on Distributed Amplifier Techniques for Broadband Applications From 140 GHz to 200 GHz

This work presents a direct-conversion receiver for G-band applications formed by a cascaded single-stage distributed amplifier optimized for low noise, a single-balanced active mixer with inductive peaking and broadband RF matching, and a local oscillator (LO) driver. The receiver is optimized for reduced DC and LO power consumption, while practical levels of linearity and noise are retained. The complete receiver and of the stand-alone mixer are implemented in 0.62 mm2 and 0.39 mm2 of a 130 nm SiGe BiCMOS technology with 450 GHz maximum-oscillation frequency. The measured receiver saturated gain in LO compression is 17 dB with a 6 dB band of 60 GHz and a 3 dB band of 30 GHz, while the input power which compresses the gain by 1 dB ( $\text{P}_{in1dB}$ ) is −35 dBm. The simulated receiver double-sideband noise figure is 11 dB. Finally, the circuit requires an LO power of −17 dBm at 170 GHz and a DC power of 98 mW. The measured gain of the mixer is −13 dB with a 3 dB band of 70 GHz. The component $\text{P}_{in1dB}$ is −20 dBm for −18 dBm LO power and 53 mW DC power. These circuits offer one of the largest operation bandwidth together with one of the lowest DC and LO power consumption against the state of the art.

A 0.8V, 152 μW, 433 MHz Mixer-First Receiver with a Self-Adjusted Frequency Tracking Loop

This paper presents a 433 MHz low-power receiver utilizing an N-path filter technique and a self-frequency tracking mechanism. Without the front-end amplifier, the mixer-first architecture can reduce power consumption significantly. A self-adjusted frequency tracking loop (SA-FTL) adjusts local oscillator (LO) frequency to approach input RF frequency automatically, thereby enhancing conversion gain and lowering return loss. The receiver, implemented in a 0.18 μm CMOS process, achieves a sensitivity of -80 dBm at a bit error rate (BER) of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> and a data rate of 10 kb/s, while consuming 152 μW from a 0.8V voltage supply.

A 96-Gb/s PAM-4 Receiver Using Time-Interleaved Converters in 130-nm SiGe BiCMOS

This letter describes a 96-Gb/s PAM-4 receiver, suitable for silicon photonics application, designed and fabricated in a 130-nm SiGe BiCMOS technology. The low-power receiver includes a TIA and a VGA, two slices of time-interleaved track and hold amplifier and two-bit folding ADC circuits, and multiplexers to deliver full-rate decoded NRZ output signals. The track and hold amplifier is based on a switched emitter–follower topology optimized for low-power operation to sample at 24 GSample/s. Half-rate PAM-4 to NRZ converters are implemented as a bandwidth-enhanced two-bit folding ADC in order to consume less power compared to flash competitors. The receiver chip consumes 545 mW, leading to an energy efficiency of 5.67 mW/Gb/s, which is one of the best among the state-of-the-art works at this data-rate.

Design of radio frequency integrated circuit for RF to DC power converter for bio-medical application

In modern biomedical communication systems, high level integration using CMOS technologies plays an important role for low cost performance. For mobile biomedical communication systems, the low voltage and low power design issues are crucial due to the limitation of battery capacity. Therefore, the volume and weight of the transceivers can be further reduced using the low voltage and low power technique. As such, all the designs proposed here are realized with standard CMOS technology and they are suitable to be a building block in low voltage, low cost, compact size, high gain and low power receiver front end design owing to the superior performance. The most significant building blocks in the receiver front end are low noise amplifier (LNA),RF to DC rectifier(RFDC) , local oscillator (LO) and intermediate frequency (IF) amplifier. Here, the main emphasis is given on design of the RFDC rectifier, which is regarded as the main part of the receiver front end, as the total linearity of a system dependents on the linearity of the RFDC rectifier. In CMOS transceivers, the Gilbert cell RFDC rectifier is widely used as the down converter since they are broadband with good isolation, good conversion gain and high linearity, nevertheless with some drawbacks of high supply voltage and high power consumption. In this work, different integrated topologies are implemented to dissolve the trade-off problems in the RFDC rectifier design. The simulated results show significant improvements in the aforementioned parameters in comparison to recent approaches.

2.4-GHz CMOS Bluetooth RF Receiver With Improved IM2 Distortion Tolerance

A low-power CMOS sliding-IF RF receiver is presented for Bluetooth Low Energy (BLE) applications. It comprises an LNA, RF mixer, transconductance ( $g_{m}$ ) stage, IF mixer, transimpedance amplifier (TIA), and LO generation block. We present a comprehensive analysis of the second-order intermodulation (IM2) distortion that is induced by an in-band orthogonal frequency-division modulation (OFDM) blocker and its effects on the receiver input sensitivity. Based on the analysis, an in-band two-tone blocker tolerance test procedure is proposed, and an IM2 calibration circuit to enhance the receiver’s IM2 tolerance is presented. Furthermore, a conflict issue in the co-optimization of IM2 calibration at the IF mixer stage and dc offset calibration at the subsequent baseband amplifier stage is alleviated. This is achieved by employing a body bias control method for the dc offset calibration and a gate bias control method for the IM2 calibration. A BLE RF receiver integrated circuit was fabricated in a 65-nm RF CMOS process. Dissipating 3.55 mW from a 1-V supply, it achieves a gain control range from +2 to +62 dB, a minimum noise figure of 3 dB, and an out-of-band (OOB) single-tone blocker tolerance level of −10 dBm. Measurement results demonstrate that the proposed IM2 calibration circuit significantly improves the in-band two-tone blocker tolerance level by 7–12 dB, achieving its range from −41 to −31 dBm.