Low-power Mobile Applications Research Articles

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

A novel sub-5-nm node folded cascode structure using dual workfunction (WF) scheme was proposed using fully-calibrated TCAD. Feasible process flows of the cascode device were adopted from those of nanosheet FETs (NSFETs) and complementary FETs. Key process flows were depositing two different separate spacers and etching one spacer selectively, depositing oxide layer in between source/drain epitaxial growths for electrical isolation, and fill-CMP-etch back sequence for dual-WF. The folded cascode device consists of two or three FETs in series, designated as 2-CAS or 3-CAS respectively, under the same active area. Conventional three-stacked NSFETs have larger transconductance (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) than 2-CAS and 3-CAS, but the cascode devices have much larger output resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> ) by dual-WF scheme and thus achieve larger intrinsic gain (AV = G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> ). Smaller G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> and larger gate capacitance for the cascode devices decrease the cutoff frequency. But smaller gate-to-drain capacitance by shrunk drain epi along with large Ro increases the maximum frequency (F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ). Especially, 2-CAS has larger AV and F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> than conventional NSFETs for all the NS widths of 20, 30, and 40 nm and at all the operation voltages of 0.6, 0.7, and 0.8 V, promising for low power mobile applications.

Low Complexity, Hardware-Efficient Neighbor-Guided SGM Optical Flow for Low-Power Mobile Vision Applications

Accurate, low-latency, and energy-efficient optical flow estimation is a fundamental kernel function to enable several real-time vision applications on mobile platforms. This paper presents neighbor-guided semi-global matching (NG-fSGM), a new low-complexity optical flow algorithm tailored for low-power mobile applications. NG-fSGM obtains high accuracy optical flow by aggregating local matching costs over a semi-global region, successfully resolving local ambiguity in texture-less and occluded regions. The proposed NG-fSGM aggressively prunes the search space based on neighboring pixels’ information to significantly lower the algorithm complexity from the original fSGM. As a result, NG-fSGM achieves $17.9{\times}$ reduction in the number of computations and $8.37{\times}$ reduction in memory space compared to the original fSGM without compromising its algorithm accuracy. A multicore architecture for NG-fSGM is implemented in hardware to quantify algorithm complexity and power consumption. The proposed architecture realizes NG-fSGM with overlapping blocks processed in parallel to enhance throughput and to lower power consumption. The eight-core architecture achieves 20 M pixel/s (66 frames/s for VGA) throughput with 9.6 mm2 area at 679.2-mW power consumption in 28-nm node.

A Retrospective View on the Technology Evolution to Support Low Power Mobile Application

A Retrospective View on the Technology Evolution to Support Low Power Mobile Application

A 70 pJ/b configurable 64-QAM soft MIMO detector

An area and power efficient high-throughput VLSI implementation of a 4 × 4, 64-QAM soft multiple-input-multiple-output (MIMO) detector, that is suitable for high-order constellation schemes is presented. The proposed MIMO detector utilizes information contained in the discarded paths to improve the bit-error-rate (BER) performance, and then reduces computational complexity using three innovative improvement ideas. The proposed design is fabricated and fully tested in a 130 nm CMOS technology. Operating with a 270 MHz clock, the design achieves up to 655 Mbps throughput with 195 mW power dissipation at 1.32 V supply. Synthesis results in 65 nm CMOS technology shows that the proposed soft-output MIMO detector attains a peak coded data throughput of 2 Gbps. Furthermore, this detector is also suitable for low-power mobile applications that require high data rates, achieving a low decoding energy per bit of 70.3 pJ/bit at 1.1 V supply, while providing a data throughput of 640 Mbps in a 65 nm CMOS technology. The proposed design has the best throughput per unit area among all reported fabricated designs to-date.

SPIDER: Sizing-Priority-Based Application-Driven Memory for Mobile Video Applications

Recently, mobile devices such as smartphones and tablets have become the most important medium for delivering internet traffic, especially multimedia content, to end users. However, mobile embedded memory incurs large power consumption owing to the highly frequent access and extensive computation. This paper presents an sizing-priority-based application-driven memory (SPIDER) design methodology for low-power mobile video applications. We investigate the size dependent memory failure characteristics and effectively reduce the memory failure rate with low area overhead. Also, we develop a model for the influence of the memory failure on video output, connecting the hardware design process and application requirement. Based on this, we design the SPIDER algorithms for area-priority and quality-priority mobile video applications. During this process, we also consider the contribution of both Luma and Chroma to output quality, avoiding over-optimization issue. We also develop a hardware-based python-assisted SPIDER simulator to apply our proposed design in one leading edge video compression system, the H.264 decoder. Our simulation results in 45-nm CMOS technology show that SPIDER supports mobile videos successfully as voltage downs to 500 mV from 1 V, enabling over 70% power savings in memory arrays.

Statistical Trilateration With Skew-t Distributed Errors in LTE Networks

Localization accuracy of trilateration methods in long term evolution (LTE) cellular networks, which are based on time-of-arrival, may be highly degraded due to multipath and non-line of sight conditions in urban and indoor environments. Multipath mitigation techniques usually involve a high computational burden and require wideband signals to be effective, which limit their adoption in certain low-cost and low-power mobile applications using narrow-band signals. As an alternative to these conventional techniques, this paper analyzes an expectation maximization (EM) localization algorithm that considers the skewness introduced by multipath in the LTE ranging error distribution. The EM algorithm is extensively studied with realistic emulated LTE signals of 1.4-MHz bandwidth. The EM method is compared with a standard nonlinear least squares (NLS) algorithm under ideal simulated conditions and using realistic outdoor measurements from a laboratory testbed. The EM method outperforms the NLS method when the ranging errors in the training and test stages have similar distributions.

A water-induced high-k yttrium oxide dielectric for fully-solution-processed oxide thin-film transistors

In this work, we develop a simple and eco-friendly water-inducement method for high-k yttrium oxide (YOx) dielectric. To prepare YOx thin films at low temperature, yttrium nitrate and deionized water were used as the source materials. No toxic organic materials were required in the YOx coating process. The YOx thin film annealed at 350 °C showed a low leakage current density of 2 × 10−9 A/cm2 at 5MV/cm and a large areal-capacitance of 448 nF/cm2 at 1 kHz. On the basis of its implementation as the gate dielectric, the fully-water-induced In2O3 TFT based on YOx exhibited a high field-effect mobility of 15.98cm2/Vs, excellent subthreshold swing of 75mV/dec, an on/off current ratio of 6 × 106, and a negligible hysteresis of 50 mV. The as-fabricated TFT operated at a low voltage (∼1.5 V) and showed high drain current drive capability, enabling oxide TFT with a water-induced high-k dielectric for use in backplane electronics for low-power mobile display applications.

A novel design method for discrete time chaos based true random number generators

Discrete time chaos based true random number generators are lightweight cryptographic primitives that offer scalable performance for the emerging low power mobile applications. In this work, a novel design method for discrete time chaos based true random number generators is developed using skew tent map as a case study. Optimum parameter values yielding maximum randomness are calculated using a mathematical model of true random number generator. A practical information measure is used to determine the maximum allowable parameter variation limits. Appropriate mapping between dynamic system and circuit parameters is established and a current mode skew tent map circuit is designed to validate proposed method.

Silicon &amp; beyond CMOS: The Path of Advanced Electronic Structure Engineering for Low-Voltage Transistors

With the continuing growth of data bandwidth, next-generation information technology demands circuit and device scaling to meet performance, form-factor and cost needs. With increase performance and circuit density, reduction in power dissipation has become paramount for both high-performance and low-power applications. In the case of high-performance systems, heat dissipation becomes the thermal bottle neck. Limited by battery, low-power mobile applications ration energy to maintain user multimedia experience while on the move. Lowering supply voltage (Vdd) is becoming the major system enabler to manage the power challenges.

Probabilistic motion-compensated prediction in distributed video coding

Distributed video coding (DVC) constitutes an original coding framework to meet the stringent requirements imposed by uplink-oriented and low-power mobile video applications. The quality of the side information available to the decoder and the efficiency of the employed channel codes are primary factors determining the success of a DVC system. This contribution introduces two novel techniques for probabilistic motion compensation in order to generate side information at the Wyner-Ziv decoder. The employed DVC scheme uses a base layer, serving as a hash to facilitate overlapped block motion estimation at the decoder side. On top of the base layer, a supplementary Wyner-Ziv layer is coded in the DCT domain. Both proposed probabilistic motion compensation techniques are driven by the actual correlation channel statistics and reuse information contained in the hash. Experimental results report significant rate savings caused by the novel side information generation methods compared to previous techniques. Moreover, the compression performance of the presented DVC architecture, featuring the proposed side-information generation techniques, delivers state-of-the-art compression performance.

Asynchronous Pulse Transmitter for Power Reduction in Inductive-Coupling Link

An asynchronous pulse transmitter is proposed to achieve low power in inductive-coupling link. The conventional asynchronous transmitter, H-bridge inductive-coupling transmitter, consumes large static (DC) current consumption. Therefore the transmit power dissipation is dominant in the total inductive-coupling power dissipation. The proposed pulse inductive-coupling transmitter eliminates the static (DC) current consumption. It provides linear power scalability which significantly reduces the power consumption especially at low data rate operation for low-power mobile applications. To verify the proposed technique, we designed and fabricated test chips in TSMC 0.18 µm complementary metal oxide semiconductor (CMOS) technology. Both proposed pulsed transmitter and conventional H-bridge transmitter is implemented in the test chip for comparison. Power reduction to 1/4 at 1.5 Gbps and 1/60 at 100 Mbps is achieved compared to the conventional transmitter. Also a crosstalk immune inductive-coupling receiver is presented for low-power relayed transmission using the proposed pulse transmitter. Crosstalk guard circuit is implemented in the receiver to ignore crosstalk. Data is successfully transferred using relayed transmission with proposed transceiver at up to 400 Mbps.

P‐119: A New Charge Pump Pixel Circuit for Reflective Displays

AbstractA novel charge pump pixel circuit for reflective display requiring high voltage driving, which is more than 10 V, is proposed for low‐power mobile application. By adopting proposed low‐voltage frame inversion method, we can reduce input data voltage swing to almost half of driving voltage on a pixel electrode, so the power consumption on parasitic elements can be substantially reduced.The operation of the pixel circuit was confirmed through the prototype of 3.6″ polymer dispersed liquid crystal displays and the simulation results show that the proposed approach reduces the power consumption by 64.3%, compared with the conventional driving method.

Reconfigurable SRAM Architecture With Spatial Voltage Scaling for Low Power Mobile Multimedia Applications

This paper presents a dynamically reconfigurable SRAM array for low-power mobile multimedia application. The proposed structure use a lower voltage for cells storing low-order bits and a nominal voltage for cells storing higher order bits. The architecture allows reconfigure the number of bits in the low-voltage mode to change the error characteristics of the array in run-time. Simulations in predictive 70 nm nodes show that the proposed array can obtain 45% savings in memory power with a marginal (~10%) reduction in image quality.

A low-power MDDI-client architecture using on-off byte counter

This paper presents a Mobile Display Digital Interface (MDDI)-client architecture which is suitable for low-power, small-area, and low-cost mobile applications. Compared to the power dissipation of an MDDI client with a byte counter that has continuous transitions for all packet data, the proposed MDDI client reduces power consumption in state transitions up to 50% by using robust Finite State Machine (FSM) and on-off byte counter. The proposed scheme detects invalid data in packets and turns off the operation of the byte counter to minimize client's power dissipation. The MDDI-client architecture is implemented and verified on FPGA modules.

A broadband folded Gilbert cell CMOS mixer

A folded Gilbert cell mixer was implemented in 0.13 μm complementary metal oxide semiconductor (CMOS) technology. The downconversion mixer is designed for 5---6 GHz radio frequency (RF) band and an intermediate frequency (IF) of 500 MHz. A voltage conversion gain (CG) of 9 dB, a noise figure (NF) of 11 dB and an IIP3 of 2 dBm were demonstrated experimentally under very low power consumption conditions, only 4.2 mW for the mixer core. Considering the overall performance of the circuit, this paper shows that the folded mixer architecture is one of the most interesting frequency converter solutions for low-power mobile applications.

Reduction of the switching time of polymer-dispersed liquid crystal using field oriented addressing

Polymer dispersed liquid crystal (PDLC) is a promising liquid crystal for reflective displays in low power mobile applications. However, it is difficult to obtain full color PDLC displays. Color sequential PDLC is one solution but this requires short PDLC switching times. It is demonstrated that the PDLC switching times can be reduced to color sequential levels by changing the orientation of the electric field (field-oriented addressing). By choosing the right pixel geometry, this can be done at relatively low switching voltages compared to the classic addressing method which is based on changing the magnitude of the electric field.

RF circuits and advanced A/D converters

The fast growing demand for mobile communications has lead to numerous development efforts in chip technology for the RF front-end of these systems. Recent improvements in bipolar processing and dimension reduction have raised silicon operating frequency up to 2 GHz. Low power mobile applications present a good opportunity for submicron BiCMOS process. The first part of this presentation will describe some advanced BiCMOS RF architectures and present some experimental results. The A/D converter generally remains the most critical block of an integrated acquisition chain, as regards the whole channel performance and especially for low power applications. This presentation will be focused on the design of efficient submicron CMOS delta-sigma A/D converters dedicated to general purpose signal processing applications and some experimental results will also be discussed.