Abstract
A novel sub-5-nm node folded cascode structure using dual workfunction (WF) scheme was proposed using fully-calibrated TCAD. Feasible process flows of the cascode device were adopted from those of nanosheet FETs (NSFETs) and complementary FETs. Key process flows were depositing two different separate spacers and etching one spacer selectively, depositing oxide layer in between source/drain epitaxial growths for electrical isolation, and fill-CMP-etch back sequence for dual-WF. The folded cascode device consists of two or three FETs in series, designated as 2-CAS or 3-CAS respectively, under the same active area. Conventional three-stacked NSFETs have larger transconductance (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) than 2-CAS and 3-CAS, but the cascode devices have much larger output resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> ) by dual-WF scheme and thus achieve larger intrinsic gain (AV = G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> ). Smaller G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> and larger gate capacitance for the cascode devices decrease the cutoff frequency. But smaller gate-to-drain capacitance by shrunk drain epi along with large Ro increases the maximum frequency (F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ). Especially, 2-CAS has larger AV and F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> than conventional NSFETs for all the NS widths of 20, 30, and 40 nm and at all the operation voltages of 0.6, 0.7, and 0.8 V, promising for low power mobile applications.
Highlights
Silicon fin field-effect transistors (FinFETs) have been scaled down to 10-nm node [1], and further down to 5-nm node by full-fledged EUV and SiGe channel [2]
It is challenging to scale down the devices while maintaining analog/RF performances in order to contain all chipsets including longterm evolution and 5G bands within a small mobile device
Two different WFs are adopted for the cascode devices
Summary
Silicon fin field-effect transistors (FinFETs) have been scaled down to 10-nm node [1], and further down to 5-nm node by full-fledged EUV and SiGe channel [2]. RF devices have adopted fin structure to improve the gate electrostatics and to increase the current drivability for analog/RF applications [3]-[5]. It is challenging to scale down the devices while maintaining analog/RF performances in order to contain all chipsets including longterm evolution and 5G bands within a small mobile device. Planar MOSFETs adopting dual workfunction (WF) scheme, so called cascode MOSFETs, have been proposed to increase transconductance (Gm) and output resistance (Ro), eventually attaining high intrinsic gain (AV = GmRo) [6]-[8]. In this work, we present a novel cascode structure adopting nanosheet (NS) channels [9] and dual-WF for achieving excellent area scaling as well as analog/RF performances (AV, Ft, Fmax) using fully-calibrated TCAD
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