Low-power Memory Research Articles

Enhanced tunneling electroresistance effect in Pt/BiAlO3/Pt ferroelectric tunnel junctions by a graphene interlayer

Realizing a large tunneling electroresistance (TER) effect with a low ON-state resistance-area product (RAP) is essential for the applications of ferroelectric tunnel junctions (FTJs) in information storage. Herein, taking Pt/BiAlO3/Pt (Pt/BAO/Pt) FTJs as examples, we theoretically demonstrate that a giant TER ratio of about 1458%, which is comparable to most van der Waals tunnel junctions, can be achieved by switching the electric polarization of ferroelectric BAO(0001) barrier due to the reversible metallization of ferroelectric in conjunction with the Schottky barrier. More interestingly, with the effective modulation on barrier height and width via polarization reversal, an enhanced TER effect close to 104% can be obtained by inserting a graphene monolayer into right (or left) Pt/BAO interface of the FTJs and the writing endurance of the FTJ memories is expected to be significantly improved. Furthermore, the calculated ON-state RAPs in all three FTJ devices are not more than 100 Ω μm2. These fascinating findings suggest that the proposed BAO-based FTJs hold great potential for designing next-generation nanoscale high-density and low-power nonvolatile memories with excellent performance.

Sub-Nanosecond Switching of Si:HfO2 Ferroelectric Field-Effect Transistor.

The discovery of ferroelectric doped HfO2 enabled the emergence of scalable and CMOS-compatible ferroelectric field-effect transistor (FeFET) technology which has the potential to meet the growing need for fast, low-power, low-cost, and high-density nonvolatile memory, and neuromorphic devices. Although HfO2 FeFETs have been widely studied in the past few years, their fundamental switching speed is yet to be explored. Importantly, the shortest polarization time demonstrated to date in HfO2-based FeFET was ∼10 ns. Here, we report that a single subnanosecond pulse can fully switch HfO2-based FeFET. We also study the polarization switching kinetics across 11 orders of magnitude in time (300 ps to 8 s) and find a remarkably steep time-voltage relation, which is captured by the classical nucleation theory across this wide range of pulse widths. These results demonstrate the high-speed capabilities of FeFETs and help better understand their fundamental polarization switching speed limits and switching kinetics.

A carbon nano-tube field effect transistor based stable, low-power 8T static random access memory cell with improved write access time

Carbon nanotube field effect transistor (CNTFET) is swiftly becoming an alternative to conventional CMOS transistors due to superior transport properties, improved current handling characteristics, and better gate control. This work presents a new Carbon nanotube field effect transistor (CNTFET) based low power, stable static random access memory (SRAM) cell design with reduced write delay. The proposed eight-transistor (8T) CNTFET-based SRAM cell improves read/write static noise margin by 1.98×/1.25×, respectively, at 0.3 V compared to conventional 6T SRAM that uses similar CNTFET parameters. The write access time and leakage power of the proposed cell are improved by 1.90× and 2.14×, respectively, compared to the conventional 6T design. The proposed design parameters are also compared with two already presented 8T SRAM cells. The simulation is performed with the Cadence Virtuoso using the Stanford University 32 nm CNTFET Verilog model.

Disentanglement of intrinsic and extrinsic side-jump scattering induced spin Hall effect in N-implanted Pt

The rapidly evolving utilization of spin Hall effect (SHE) arising from spin-orbit coupling in 5d transition metals and alloys have made giant strides in the development of designing low-power, robust and non-volatile magnetic memory. Recent studies, on incorporating non-metallic lighter elements such as oxygen, nitrogen and sulfur into 5d transition metals, have shown an enhancement in damping-like torque efficiency {\theta}_DL due to the modified SHE, but the mechanism behind this enhancement is not clear. In this paper, we study {\theta}_DL at different temperatures (100-293 K) to disentangle the intrinsic and extrinsic side-jump scattering induced spin Hall effect in N-implanted Pt. We observe a crossover of intrinsic to extrinsic side-jump mechanism as the implantation dose increases from 2*10^16 ions/cm2 to 1*10^17 ions/cm2. A sudden decrease in the intrinsic spin Hall conductivity is counterbalanced by the increase in the side-jump induced SHE efficiency. These results conclude that studying {\theta}_DL as a function of implantation dose, and also as a function of temperature, is important to understand the physical mechanism contributing to SHE, which has so far been unexplored in incorporating non-metallic element in 5d transition metals.

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

Maintaining power consumption has become a critical hurdle in the manufacturing process as CMOS technologies continue to be downscaled. The longevity of portable gadgets is reduced as power usage increases. As a result, less-cost, high-density, less-power, and better-performance memory devices are in great demand in the electronics industry for a wide range of applications, including Internet of Things (IoT) and electronic devices like laptops and smartphones. All of the specifications for designing a non-volatile memory will benefit from the use of memristors. In addition to being non-volatile, memristive devices are also characterized by the high switching frequency, low wattage requirement, and compact size. Traditional transistors can be replaced by silicon substrate-based FinFETs, which are substantially more efficient in terms of area and power, to improve the design. As a result, the design of non-volatile SRAM cell in conjunction with silicon substrate-based FinFET and Metal Insulator Metal (MIM) based Memristor is proposed and compared to traditional SRAMs. The power consumption of the proposed hybrid design has outperformed the standard Silicon substrate FinFET design by 91.8% better. It has also been reported that the delay for the suggested design is actually quite a bit shorter, coming in at approximately 1.989 ps. The proposed architecture has been made significantly more practical for use as a low-power and high-speed memory system because of the incorporation of high-K insulation at the interface of metal regions. In addition, Monte Carlo (MC) simulations have been run for the reported 6T-SRAM designs in order to have a better understanding of the device stability.

CoFHE: Software and hardware Co-design for FHE-based machine learning as a service

Introduction: Privacy concerns arise whenever sensitive data is outsourced to untrusted Machine Learning as a Service (MLaaS) platforms. Fully Homomorphic Encryption (FHE) emerges one of the most promising solutions to implementing privacy-preserving MLaaS. But prior FHE-based MLaaS faces challenges from both software and hardware perspectives. First, FHE can be implemented by various schemes including BGV, BFV, and CKKS, which are good at different FHE operations, e.g., additions, multiplications, and rotations. Different neural network architectures require different numbers of FHE operations, thereby preferring different FHE schemes. However, state-of-the-art MLaaS just naïvely chooses one FHE scheme to build FHE-based neural networks without considering other FHE schemes. Second, state-of-the-art MLaaS uses power-hungry hardware accelerators to process FHE-based inferences. Typically, prior high-performance FHE accelerators consume >160 Watt, due to their huge capacity (e.g., 512 MB) on-chip SRAM scratchpad memories.Methods: In this paper, we propose a software and hardware co-designed FHE-based MLaaS framework, CoFHE. From the software perspective, we propose an FHE compiler to select the best FHE scheme for a network architecture. We also build a low-power and high-density NAND-SPIN and SRAM hybrid scratchpad memory system for FHE hardware accelerators.Results: On average, under the same security and accuracy constraints, on average, CoFHE accelerates various FHE-based inferences by 18%, and reduces the energy consumption of various FHE-based inferences by 26%.Discussion: CoFHE greatly improves the latency and energy efficiency of FHE-based MLaaS.

Voltage-gated spin-orbit torque switching in IrMn-based perpendicular magnetic tunnel junctions

In this work, IrMn-based perpendicular magnetic tunnel junctions (MTJs) are investigated. By inserting a thin W layer at an antiferromagnet/ferromagnet (AFM/FM) interface, we enhance the annealing temperature to 355 °C and obtain a high tunnel magnetoresistance ratio of 127%. Subsequently, field-free spin–orbit torque (SOT) switching of perpendicular MTJ is realized thanks to the in-plane exchange bias generated at the AFM/FM interface. Moreover, by applying a gate voltage, a coercive field is effectively decreased due to the voltage-controlled magnetic anisotropy (VCMA) effect. Finally, through the interplay of the SOT and VCMA effects, the critical switching current density is dramatically reduced by 73% (to 2.4 MA/cm2) and the total writing power consumption is decreased by 84% when a gate voltage of 0.76 V is applied. These findings pave the way for the practical applications of the IrMn-based perpendicular MTJs in low-power magnetic random-access memory.

Understanding the Effect of Oxygen Content on Ferroelectric Properties of Al-Doped HfO Thin Films

To satisfy the demand of high-speed and low-power memory in the field of integrated circuits, different elements doped HfO2 ferroelectric tunnel junctions have been developed. In this work, we investigate the annealing atmosphere effects on the ferroelectric property of the Al-doped HfO2 (HfAlO) ferroelectric tunnel junctions based on first-principles calculation and experiments. The ferroelectric layer/electrode interface has the obvious effect on ferroelectric property of the devices under different oxygen content annealing atmosphere, including 0%, 50% and 100% O2. The first-principle analysis verified that stable o-phase proportion in HfAlO film owing to the co-existence of the Al and oxygen vacancy is the key element to stable ferroelectric performance of device. This work could promote the development of HfAlO ferroelectric tunnel junctions for next-generation in-memory computing applications.

Performance Analysis Of SRAM and Dram in Low Power Application

All electronic systems must function quickly in the current environment, and 80 percent of electronic chips have memory components. SRAM (Static Random Access Memory) has thus become a major key component in many VLSI Chips in order to reduce the size of the memory chips, to increase the speed, to reduce leakage current, and to increase the power efficiency. Due to its high storage density and quick access time, it has also become a popular data storage device. SRAM has been given priority in the research community due to the recent sharp development in low power and low voltage memory devices. In this study, the design and performance of SRAM and DRAM cells were analyzed. This paper outlines the development and application of modified 6T SRAM cell with increased power efficiency.

A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh

We introduce a highly heterogeneous and programmable compute-in-memory (CIM) accelerator architecture for deep neural network (DNN) inference. This architecture combines spatially distributed CIM memory array “tiles” for weight-stationary, energy-efficient multiply–accumulate (MAC) operations, together with heterogeneous special-function compute cores for auxiliary digital computation. Massively parallel vectors of neuron activation data are exchanged over short distances using a dense and efficient circuit-switched 2-D mesh, offering full end-to-end support for a wide range of DNN workloads, including CNNs, long-short-term-memory (LSTM), and transformers. We discuss the design of the “analog fabric”—the 2-D grid of tiles and compute cores interconnected by the 2-D mesh—and address the efficiency in both mapping of DNNs onto the hardware and in pipelining of various DNN workloads across a range of batch sizes. We show, for the first time, system-level assessments using projected component parameters for a realistic “analog AI” system, based on dense crossbar arrays of low-power nonvolatile analog memory elements, while incorporating a single common analog fabric design that can scale to large networks by introducing data transport between multiple analog AI chips. Our performance estimates for several networks, including large LSTM and bidirectional encoder representations from transformers (BERT), show highly competitive throughput while offering <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$40\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$140\times $ </tex-math></inline-formula> higher energy efficiency than NVIDIA A100—thus illustrating the strong promise of analog AI and the proposed architecture for DNN inference applications.

Cleavable crystals, crystal structure, and magnetic properties of the NbFe1+xTe3 layered van der Waals telluride.

Transition metal-based two-dimensional nanomaterials with competing magnetic states are at the cutting edge of spintronic and low-power memory devices. In this paper, we present a Fe-rich NbFe1+xTe3 layered telluride (x ≈ 0.5), which shows an interplay of spin-glass and antiferromagnetic states below the Néel temperature of 179 K. The compound has a layered crystal structure, where the NbFeTe3 layers are terminated by the Te atoms and van der Waals gaps. Bulk single crystals grown by chemical vapor transport reactions possess the (1̄01) cleavage plane suitable for the exfoliation of two-dimensional nanomaterials. Combination of high-resolution transmission electron microscopy and powder X-ray diffraction reveals the zigzag ladders of Fe atoms inside the structural layers, as well as complementary zigzag chains of the partially occupied Fe positions in the interstitial region. Fe atoms carry large effective magnetic moment of 4.85(3)μB per atom in the paramagnetic state yielding intriguing magnetic properties of NbFe1+xTe3. They include frozen spin-glass state at low temperatures and spin-flop transition in high magnetic fields indicating promising flexibility of the magnetic system and its potential control by magnetic field or gate tuning in the spintronic devices and heterostructures.

Power-Delay Area-Efficient Processing-In-Memory Based on Nanocrystalline Hafnia Ferroelectric Field-Effect Transistors

Ferroelectric field-effect transistors (FeFETs) have attracted enormous attention for low-power and high-density nonvolatile memory devices in processing-in-memory (PIM). However, their small memory window (MW) and limited endurance severely degrade the area efficiency and reliability of PIM devices. Herein, we overcome such challenges using key approaches covering from the material to the device and array architecture. High ferroelectricity was successfully demonstrated considering the thermodynamics and kinetics, even in a relatively thick (≥30 nm) ferroelectric material that was unexplored so far. Moreover, we employed a metal-ferroelectric-metal-insulator-semiconductor architecture that enabled desirable voltage division between the ferroelectric and the metal-oxide-semiconductor FET, leading to a large MW (∼11 V), fast operation speed (<20 ns), and high endurance (∼1011 cycles) characteristics. Subsequently, reliable and energy-efficient multiply-and-accumulation (MAC) operations were verified using a fabricated FeFET-PIM array. Furthermore, a system-level simulation demonstrated the high energy efficiency of the FeFET-PIM array, which was attributed to charge-domain computing. Finally, the proposed signed weight MAC computation achieved high accuracy on the CIFAR-10 dataset using the VGG-8 network.

Multivalley Electron Conduction at the Indirect-Direct Crossover Point in Highly Tensile-Strained Germanium

For applications such as low-power tunneling transistors and memory, lasers, qubits, and spintronics, there is interest in using strain to enhance carrier mobility in semiconductors. This experimental and theoretical study investigates transport in highly strained germanium, in which multivalley electron conduction emerges. Surprisingly, all conduction occurs via the L valley in Ge for biaxial tensile strain below 1.6%, while above the contribution from the \ensuremath{\Gamma} valley increases, with negligible contributions from the underlying strain template.

Half-Metallic Heusler Alloy/MoS2 Based Magnetic Tunnel Junction.

Integration of half-metallic materials and 2D spacers into vertical magnetoresistive spin valves may pave the way for effective low-power consumption storage and memory technologies. Driven by the recent successful growth of graphene/half-metallic Co2Fe(Ge1/2Ga1/2) (CFGG) heterostructure, here we report a theoretical investigation of magnetic tunnel junction (MTJ) based on the ferromagnetic CFGG Heusler alloy and the MoS2 spacer of different thicknesses. Using ab initio approach, we demonstrate that the inherent ferromagnetism of CFGG is preserved at the interface, while its half-metallicity is recovering within few atomic layers. Ballistic transport in CFGG/MoS2/CFGG MTJ is studied within the nonequilibrium Green's function formalism, and a large magnetoresistance value up to ∼105% is observed. These findings support the idea of effective spintronics devices based on half-metallic Heusler alloys and highly diversified transition metal dichalcogenide family.

Write Disturb-Free Ferroelectric FETs With Non-Accumulative Switching Dynamics

HfO2 based ferroelectric field-effect transistors (FeFETs) are promising for low-power and high-speed non-volatile memories. However, FeFETs can be susceptible to write disturbs due to their accumulative switching behavior, which limits their application in large scale memory arrays. Here we show that FeFETs with a thin HfO2 based ferroelectric and SiNx interfacial layer are immune to pulsed write disturbs under both <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\textit {dd}}$ </tex-math></inline-formula> /2 and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\textit {dd}}$ </tex-math></inline-formula> /3 inhibit schemes, but not to continuous write disturb. This contrasts with previous reports which found no difference between pulsed and continuous write disturbs. Our findings suggest that accumulative polarization switching is not an intrinsic property of HfO2 based FeFETs, but might be related to charge trapping dynamics instead.

Mesoscopic-scale grain formation in HfO2-based ferroelectric thin films and its impact on electrical characteristics

Ferroelectric memory devices are expected for low-power and high-speed memory applications. HfO2-based ferroelectric is attracting attention for its CMOS-compatibility and high scalability. Mesoscopic-scale grains, of which size is almost comparable to device size, are formed in HfO2-based ferroelectric poly-crystalline thin films, which largely influences electrical characteristics in memory devices. It is important to study the impact of mesoscopic-scale grain formation on the electrical characteristics. In this work, first, we have studied the thickness dependence of the polarization switching kinetics in HfO2-based ferroelectric. While static low-frequency polarization is comparable for different thickness, dynamic polarization switching speed is slower in thin Hf0.5Zr0.5O2 (HZO) capacitors. Based on the analysis using the NLS model and physical characterization, thinner HZO contains smaller grains with orientation non-uniformity and more grain boundaries than thicker HZO, which can impede macroscopic polarization switching. We have also theoretically and experimentally studied the polar-axis alignment of a HfO2-based ferroelectric thin film. While in-plane polar orientation is stable in as-grown HZO, out-of-plane polarization can be dominant by applying electric field, which indicates the transition from in-plane polar to out-of-plane polar orientation in the ferroelectric phase grains. This is confirmed by calculating kinetic pathway using ab-initio calculation.

Dynamical Effects of Excess Carriers on SOI FeFET Memory Device Operations

We study the carrier dynamics of memory program (PGM) and readout operations for an n-type silicon-on-insulator (SOI) ferroelectric field-effect transistor (FeFET) through TCAD simulations. We found that gate-induced drain leakages (GIDL) during the PGM operation with large negative gate biases can result in excess hole concentrations as high as 7.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 10^{{20}}$ </tex-math></inline-formula> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-{3}}$ </tex-math></inline-formula> in the potential well formed in the SOI channel. The hole accumulation causes a large electric field across the ferroelectric (FE) layer and results in a polarization boost at a low PGM voltage. For a nano-scale SOI channel, the retention time of the excess holes can exceed microseconds according to our simulations. The outflow of the excess holes leads to a transient effect in the drain current during the readout operation, and we observed additional retention effects for the FeFET memory window due to the hole dynamic effects on the electrostatics and the FE polarizations. While the excess holes result in a ~100 ps delay in the readout phase before a large read margin can be detected, they have boosted the PGM speed and polarization window. The boosted polarization can be retained for milliseconds, and potentially beyond, resulting in an appreciable ON/OFF ratio during readout. Therefore, such effects can be utilized for low-power memory applications through proper SOI FeFET designs with the awareness of excess carrier dynamics.

Correlation between interface perpendicular magnetic anisotropy and interfacial Dzyaloshinskii–Moriya interactions in Pt/Pd(t Pd)/Co(t Co)/Au

The interfacial Dzyaloshinskii–Moriya interaction (iDMI) and perpendicular magnetic anisotropy (PMA) can be manipulated via interface engineering. Their strength determines the generation and the size of skyrmions, and the correlation between the iDMI and PMA allows them to be controlled simultaneously, thus choosing the material parameters for which skyrmions can be formed. This opens up the possibility of synthesizing suitable magnetic multilayers that are needed for low-power high-density memory and in logic applications. Vibrating sample magnetometry (VSM), Brillouin light scattering (BLS), and microstrip ferromagnetic resonance (MS-FMR) were used to investigate the correlation between the iDMI and the interface PMA. For this, Pt/Pd(t Pd)Co(t Co)/Au thin film structures with 0 ⩽ t Pd⩽1.2 nm and 1.2 nm ⩽ t Co⩽3 nm were grown by combined sputtering and e-beam evaporation on Si/SiO2 substrates. VSM measurements revealed a negligible magnetic dead layer and a Pd thickness-independent magnetization at saturation of around 1200 emu cm−3. MS-FMR and BLS allowed us to conclue that PMA results from weak volume and interfacial contributions induced by Pd/Co or Pt/Co and Co/Au interfaces. The interface anisotropy constants are found to be 0.65 mJ m−2 and 0.85 mJ m−2 for Pd/Co and for Pt/Co interfaces, respectively. The Pd thickness-dependence of surface iDMI (D s) and PMA (K s) constants follow an exponential decay with a characteristic thickness higher for PMA than the iDMI. The slower decrease of K s vs Pd thickness suggests a shorter range of the iDMI with respect to PMA and points out a strongly localized origin for the iDMI. This difference between the iDMI and PMA is most likely responsible for the nonlinear correlation between PMA and iDMI constants. The investigation of the Co thickness-dependence of the iDMI and PMA in Pd/Co/MgO/Ta systems allows us to conclude a zero iDMI constant of Co/Au and to determine the iDMI constants of Pd/Co and Co/MgO, estimated to be D s Pd/Co = −0.096 pJ m−1 and D s Co/MgO = −0.15 pJ m−1, respectively. The criterion of skyrmions stability, applied for our samples, revealed the possibility of the existence of stable skyrmions in some samples.

Charge-mediated voltage modulation of magnetism in Hf0.5Zr0.5O2/Co multiferroic heterojunction

We construct the Hall-bar device with the size of several hundred nanometers based on the HZO/Co multiferroic heterojunction. A remarkable voltage-controlled magnetism is observed in the device that possesses both ferroelectric property and perpendicular magnetic anisotropy (PMA). The nucleation field and coercivity can be modulated by voltage pulse while saturation field keeps stable. The non-volatile and reversible voltage-controlled magnetism is ascribable to interfacial charges caused by ferroelectric polarization. Meanwhile, the effective anisotropy energy density (K u) can also be controlled by voltage pulse, a decrease of 83% and increase of 28% in K u are realized under –3-V and 3-V pulses, respectively. Because the energy barrier is directly proportional to K u under a given volume, a decreased or enhanced energy barrier can be controlled by voltage pulse. Thus, it is an effective method to realize low-power and high-stability magneto-resistive random-access memory (MRAM).

Design and Demonstration of a Superconducting Field-Programmable Gate Array Using Adiabatic Quantum-Flux-Parametron Logic and Memory

Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient, high- performance information processing systems because it has significantly low power consumption due to the adiabatic switching of Josephson junctions. We are developing a high-performance field-programmable gate array (FPGA) using superconducting AQFP circuits to reduce its energy consumption. The all-AQFP FPGA consists of logic blocks, switch blocks, connection blocks, and memory using AQFP circuits. In particular, the memory is composed of AQFP buffer chains, enabling high-density and low-power memory. The switch blocks can perform data routing as well as several logic functions, including majority, <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">and</small> , and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">or</small> functions, which increases the design flexibility of the all-AQFP FPGA. We fabricated a one-unit all-AQFP FPGA and demonstrated its reconfigurable operation at low speed. It was found that much lower power consumption can be achieved in the new FPGA than in the other superconducting FPGAs.