Low-power Low-noise Amplifier Research Articles

A gm/ID-Based Low-Power LNA for Ka-Band Applications.

This article presents the design of a low-power low noise amplifier (LNA) implemented in 45 nm silicon-on-insulator (SOI) technology using the gm/ID methodology. The Ka-band LNA achieves a very low power consumption of only 1.98 mW andis the first time the gm/ID approach is applied at such a high frequency. The circuit is suitable for Ka-band applications with a central frequency of 28 GHz, as the circuit is intended to operate in the n257 frequency band defined by the 3GPP 5G new radio (NR) specification. The proposed cascode LNA uses the gm/ID methodology in an RF/MW scenario to exploit the advantages of moderate inversion region operation. The circuit occupies a total area of 1.23 mm2 excluding pads and draws 1.98 mW from a DC supply of 0.9 V. Post-layout simulation results reveal a total gain of 11.4 dB, a noise figure (NF) of 3.8 dB, and an input return loss (IRL) better than 12 dB. Compared to conventional circuits, this design obtains a remarkable figure of merit (FoM) as the LNA reports a gain and NF in line with other approaches with very low power consumption.

Design of a low power LNA circuit with noise canceling approach in 90 nm CMOS process

In this manuscript, a low noise amplifier (LNA) circuit with low power consumption of 5.3 mW for 3–12 GHz ultra-wideband (UWB) is designed in 90 nm standard CMOS process. A noise-canceling (NC) approach consisting of both common-gate (CG) and common-source (CS) as input stage, followed by the gm-boosted current-reused stage to enhance the gain performance, is used in the proposed design. After noise-canceling, the achieved noise-figure (NF) is ranging from 2.28 to 3.55 dB for 3.1–10.6 GHz and a maximum of 4.0 dB at 12 GHz. Input-reflection coefficient (S11) of < −12.57 dB is achieved from this CG-CS input-matching stage. With the use of parallel-series LC matching with series-peaking-inductor followed by the gm-boosting stage improves the gain-bandwidth and delivers a flat power-gain (S21) of 18.33 ± 0.76 dB over 3–12 GHz. The CG configuration at the input side provides a high reverse-isolation (S12) of less than −78.23 dB and common-drain configuration with NMOS load at the output side ensures less than −11.79 dB output-reflection coefficient (S22) over the proposed frequency range. The proposed LNA is operated with 0.7 V Vdd and the achieved intercept points for input (IIP3) and output (OIP3) are −11.1 dBm and +6.2 dBm, respectively.

Design of a Low Power Low-Noise Amplifier with Improved Gain/Noise Ratio

Design of a Low Power Low-Noise Amplifier with Improved Gain/Noise Ratio

An Ultra-wideband Low-power Low-noise Amplifier Linearized by Adjusted Derivative Superposition and Feedback Techniques

Ultra-wideband (UWB) applications require low-power and low-noise amplifiers (LNAs) that can operate over a wide frequency range. However, conventional LNAs often suffer from poor linearity and high-power consumption. This research work proposes a novel LNA design that uses the adjusted derivative superposition (DS) technique and feedback to improve the linearity and reduce the power consumption of UWB LNAs. The DS technique enhances the third-order intermodulation (IM3) cancellation by adjusting the bias currents of the transistors, whereas the feedback improves the stability and input matching of the LNA. The LNA is implemented using a degenerated common source topology in a 180 nm standard CMOS technology. The simulation results show that the LNA achieves a power gain of 10–12.2 dB, an input third-order intercept point (IIP3) of about 12 dBm, and a noise figure of less than 2.5 dB over the UWB frequency band of 3.1–10.6 GHz. The input reflection coefficient is less than -10 dB, and the power consumption is 11.6 mW with a 1.5 V power supply. The designed LNA offers a novel and innovative solution for UWB applications that significantly improve the performance and efficiency of UWB LNAs whereas reducing the cost and complexity of implementation.

A low-power low-noise amplifier with high CMRR for wearable healthcare applications

Low-noise and low-power operation are important parameters of amplifier intended for wearable healthcare applications. However, along with these parameters the amplifier must be able to deliver high Common Mode Rejection Ratio (CMRR) for mitigating the effect of 50/60 Hz interference. This paper reports capacitively coupled-capacitive feedback amplifier based on Self Cascode Current Mirror-II (SCCM-II) Operational Transconductance Amplifier (OTA). The obtained results for proposed SCCM-II OTA based amplifier shows gain of 39.79 dB, input referred noise of 2.64 μVrms, bandwidth of 0.794-343.4 Hz, area consumption of 0.154 μm2, power consumption of 2.54 μW with ±0.9 V supply. The noise efficiency factor and CMRR values for proposed amplifier are 3.87 and 122.1 dB, respectively. In-depth theoretical interpretations and mathematical modeling of amplifier are validated in 0.18μm standard CMOS process using BSIM3V3 MOS device models. The Gaussian distribution plots of proposed amplifier for 200 Monte-Carlo iterations infer mean values for gain and CMRR are 39.79 dB and 112.96 dB which are very close to their nominal values. The proposed amplifier has been compared with conventional approach as well as with literature and improvement in results is observed in terms of input referred noise, power and CMMR. These advantages of the proposed amplifier make it suitable for non-invasive wearable healthcare applications.

A 36 μW 2.8–3.4 dB Noise Figure Impedance Boosted and Noise Attenuated LNA for NB-IoT

This paper describes an ultra-low-power low-noise amplifier (LNA) targeting the 617-652 MHz narrowband-IoT (NB-IoT) frequency band. The design breaks the trade-off in practice between the input matching, minimum required DC current, and minimum NF by using a step-down transformer with an equivalent turns ratio of less than 1, resulting in input impedance boosting and noise attenuation of the main transistor. A local feedback loop is also employed to use the LNA current source transconductance to further attenuate the main transistor noise without additional power cost. The LNA power consumption scales efficiently with the required overall transconductance without being limited to the input matching condition, in practice, while enabling a sub-3dB minimum NF, making it a suitable option for a wide range of applications. A comparison between the proposed, conventional, and state-of-the-art low-power LNA structures is presented with both analytical and simulation models, while measurement results of a prototype designed in a 65 nm technology show a sub-3dB minimum noise figure (NF), −8.8 dBm IIP3, 15 dB gain, and a state-of-the-art FoM of 39.74 dB while consuming only 36 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> from a 0.55 V supply.

A low-power low-noise neural recording amplifier with an improved recycling telescopic-cascode OTA

In this paper, a fully-differential low-power low-noise neural recording amplifier with a novel recycling telescopic-cascode (RTC) operational transconductance amplifier (OTA) is presented. In the proposed RTC OTA, the current recycling and cross-coupled transistors with local positive feedback are utilized to significantly improve the OTA’s parameters like small-signal DC gain and unity-gain bandwidth. The gain enhancement also improves the linearity in the closed-loop structure. Extensive analytical calculations and simulation results using TSMC 0.18-µm CMOS process are provided to examine the usefulness of the proposed OTA. The simulated neural recording amplifier achieves 3.55 µVrms input-referred noise over 1 Hz-10 kHz bandwidth with 3.03 and 1.22 noise efficiency factor for local field potential (LFP) and action potential (AP) bands, respectively. The total harmonic distortion (THD) is −41.7 dB for a 1 mVpp, 1 kHz sinusoidal input signal. The total power consumption is 1.70 µW from a single 1.8-V power supply.

A 5.5–7.5‐GHz band‐configurable wake‐up receiver fully integrated in 45‐nm RF‐SOI CMOS

This work investigates a 5.5–7.5-GHz band-configurable duty-cycled wake-up receiver (WuRX) fully implemented in a 45-nm radio-frequency (RF) silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) technology. Based on an uncertain intermediate frequency (IF) super-heterodyne receiver (RX) topology, the WuRX analogue front-end (AFE) incorporates a 5.5–7.5-GHz band-tunable low-power low-noise amplifier, a low-power Gilbert mixer, a digitally controlled oscillator (DCO), a 100-MHz IF band-pass filter (BPF), an envelope detector, a comparator, a pulse generator and a current reference. By application of duty cycling with a low duty cycle below 1%, the power consumption of the AFE was significantly reduced. In addition, the on-chip digital bank-end consists of a frequency divider, a phase corrector, a 31-bit correlator and a serial peripheral interface. A proof-of-concept WuRX circuit occupying an area of 1200 μm by 900 μm has been fabricated in a GlobalFoundries 45-nm RF-SOI CMOS technology. Measurement results show that at a data rate of 64 bps, the entire WuRX consumes only 2.3 μW. Tested at 8 operation bands covering 5.5–7.7 GHz, the WuRX has a measured sensitivity between −67.5 dBm and −72.4 dBm at a wake-up error rate of 10−3. With the sensitivity unchanged, the data rate of the WuRX can be scaled up to 8.2 kbps. To the authors' best knowledge, this work offers the largest RF bandwidth from 5.5 to 7.5 GHz, the most operation channels (≥8) and the fastest settling time (<115 ns) among the WuRXs reported to date.

A 2.4 GHz 87 μW low-noise amplifier in 65 nm CMOS for IoT applications

As the Bluetooth devices for the internet of things require extremely low-power dissipation to maintain longer battery life, a low-noise amplifier (LNA) as the main power-consuming part in the circuit needs more current-efficient topologies on power saving. This paper proposes a low-noise transconductance amplifier that combines the techniques of passive impendence transformation, [Formula: see text]-boosting technique, and current reuse, leading to a low power under the 1.2 V power supply. The transformer-based [Formula: see text]-boosted structure is applied in the four-transistor-stacked current-reuse topology leading to a [Formula: see text] power saving. The proposed LNA simulated in 65 nm CMOS shows the NF of 3.3 dB and the IIP3 of −8 dBm, respectively, while dissipating 87 [Formula: see text]W dc power. Compared to the previous low-power LNA, this design has fairly low-power consumption and low NF while other performance metrics remain competitive.

A D-Band High-Gain and Low-Power LNA in 65-nm CMOS by Adopting Simultaneous Noise- and Input-Matched G max-Core

This article proposes a high-gain and low-power low-noise amplifier (LNA) by adopting a simultaneous noise- and input-matched (SNIM) maximum achievable gain ( G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) core. The G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> -core is implemented by adjusting the infinite combinations of embedding networks with three passive elements. Based on the proposed two-port noise analysis for implementing the G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> -core, the input stage G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> -core can achieve a simultaneous power gain and noise matching. The adoption of the G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> -core in the input stage can maximize the amount of gain per stage, leading to higher total power gain and lower noise figure (NF). The two-stage 150-GHz LNA adopting the SNIM G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> -core is implemented in a 65-nm CMOS process. The measurement results show a peak gain of 17.9 dB at 152.2 GHz, 3-dB bandwidth of 11 GHz, NF of 4.7 and 6.2 dB at 148 and 150 GHz, respectively, and a peak power added efficiency (PAE) of 7.7% while dissipating only 13.73 mW. This work shows the highest gain per stage and the lowest NF with the lowest dc power consumption among other reported CMOS D-band amplifiers.

A 24 GHz Direct Conversion Receiver for FMCW Ranging Radar Based on Low Flicker Noise Mixer

In this paper, a 24 GHz direct conversion receiver (DCR) for frequency-modulated continuous-wave (FMCW) ranging radar based on low flicker noise mixer in 90 nm silicon-on-insulator (SOI) CMOS technology is presented. A low-noise and low-power low-noise-amplifier (LNA) adopting simultaneous noise and input matching (SNIM) method is designed. Neutralized technology and boost inductor are introduced to improve performance. The measurement results of standalone LNA show that the peak gain is 17.2 dB at 23.8 GHz and the −3 dB bandwidth is around 2.2 GHz from 22.8 GHz to 25 GHz. The LNA achieves an average 3 dB NF within the 24 GHz band. A current-bleeding mixer is used to lower noise and the factors influencing flicker noise have been discussed. Proper element values and local oscillator (LO) power have been chosen to make the mixer low-noise. Measurement results illustrate that the receiver exhibits 20.3 dB peak gain, 7 dB SSB noise figure (NF) and −22 dBm IP1dB. Flicker noise of the mixer and the receiver are measured respectively and the noise knee-point of receiver is observed 60 kHz. The receiver consumes only 16 mW with chip area of 0.65 mm2 including pads. The results demonstrate that the proposed receiver can be a promising candidate for FMCW ranging radar.

A high linearity low power low-noise amplifier designed for ultra-wide-band receivers

This paper presents a new ultra-wide band (UWB) CMOS low noise amplifier (LNA) with very high linearity and low power consumption for UWB wireless communication applications, where linearity is a big challenge, due to presence of interference and blocker signals, as well as the in-band harmonics of the desired signal components in the lower part of UWB band. The proposed LNA uses a new combination of saturated NMOS and PMOS transistors to improve both of second order and third order nonlinearities, meanwhile improving the noise performance and DC power consumption. In our design two techniques are integrated in a novel approach: Improved Complementary Derivative Superposition (ICDS) technique and Forward Body Bias (FBB) to reduce the threshold voltage of MOSFET, and hence, lowering the DC power. By utilizing a high-pass filter and common source stage in cascode form, wideband impedance matching and optimal noise figure (NF) have been obtained in the proposed UWB–LNA. The Post-layout simulation of the linearized LNA in a 180 nm RF CMOS process shows NF between 2.5 and 4 dB, gain of 10.8 ± 0.5 dB, and S11 less than −10 dB in the entire 3.1–10.6 GHz band. Total DC power consumption is only 6 mW with 1.2 V supply voltage. The average and the maximum of IIP3 in the UWB band are + 3.84 dBm and + 7.27 dBm, respectively, a superior linearity performance compared to the reported UWB ones. The chip area is 926 mm × 1075 mm, including the supply and ESD ring and the pads.

Optimization of a low noise amplifier with two technology nodes using an interactive evolutionary approach

Nowadays, wireless communications at frequencies of gigahertz have an increasing demand due to the ever-increasing number of electronic devices that uses this type of communication. However, the design of Radio Frequency (RF) circuits is difficult, time-consuming and based on designer knowledge and experience. This work proposes an interactive evolutionary approach based on genetic algorithm, implemented in the in-house iMTGSPICE optimization tool, to perform the optimization process of a Low-Power Low Noise Amplifier (LNA) dedicated to Wireless Sensor Networks (WSN), which is robust through the corner and Monte Carlo analyses and implemented in two Bulk CMOS technology nodes: 130 nm and 65 nm. Regarding each technology node, we performed two experimental studies to optimize the LNA. The first one used the conventional non-interactive approach of iMTGSPICE, which was not assisted by a designer during the optimization process. The second one used the interactive approach of iMTGSPICE, which was monitored and assisted by a beginner designer during the optimization process. The obtained results demonstrated that the interactive approach of iMTGSPICE performed the optimization process of the robust LNA from 16 to 94% faster than the non-interactive evolutionary approach. The design regarding the technology node of 130 nm took 341 min for the non-interactive and 20 min for the interactive optimization process, whereas the design in the 65 nm took 537 min for the non-interactive and 454 min for the interactive approach.

Designing a Low-Power LNA and Filter for Portable EEG Acquisition Applications

A circuit with a low-power low-noise amplifier and a Gm-C ultra-low-power filter is proposed in this paper for portable electroencephalogram (EEG) acquisition applications. The proposed circuit contains a two-stage chopper-stabilized fully recycling folded cascode (TSRFC) amplifier and a second-order continuous-time Gm-C low pass filter (LPF) with ultra-low-power consumption. The noise and input offset are reduced using the chopper-stabilized technique. A two-stage amplifier that consists of composite transistors and a recycling structure is proposed for the amplifier. Compared to a typical folded cascode CMOS amplifier, the proposed design has higher DC gain and slew rate as well as lower input-referred noise. This circuit has an adjustable second-order Gm-C LPF with very low power consumption. The amplifier achieves a midband gain of 70 dB and a −3dB bandwidth in the range 0.1–212 Hz. Moreover, the amplifier is designed in 0.18- $\mu \text{m}$ CMOS process and the chip area of the proposed circuit with pads is $450\times 450\,\,\mu \text{m}^{2}$ . The adjustable LPF has a 100 Hz cut-off frequency. The proposed circuit has an input-referred noise of $0.7~\mu $ Vrms, (0.1 ~ 100Hz) and a power consumption of 380 nW at 1 V supply.

Design, Analysis and Measurement Results of a Fully-Integrated Low-power LNA Presenting Faults

We present in this paper the analysis, design and measurement results of a low noise amplifier (LNA) operating in the ISM band at 2.45 GHz. The circuit topology adopted was based on a current reuse technique to minimize the power consumption. A prototype was fabricated in a 0.18-μm standard CMOS technology and the measured power consumption was 1.1 mW. The measured input reflection coefficient was below -10 dB and the reverse isolation was higher than 20 dB. The measured insertion gain and noise figure were 5.6 dB and 4.8 dB respectively, with divergences from the simulated values of 5 dB and 2 dB, respectively. To explain these discrepancies, we devised an analysis on the circuit, including sources of uncertainties. Moreover, we characterized a transistor included in the LNA die, that helped to explain part of the disagreements. After including the uncertainty sources, we wereaable to explain a deviation of 3.9 dB in the insertion gain with respect to the simulated result.

A 20-GHz 1.9-mW LNA Using g m-Boost and Current-Reuse Techniques in 65-nm CMOS for Satellite Communications

A 20-GHz low-power low-noise amplifier (LNA) in 65-nm CMOS is presented. The LNA is cascaded with a single-ended $g_{\mathrm {m}}$ -boosted common-gate (CG) stage and a differential neutralized common-source (CS) stage. Current-reuse technique is employed to save the power consumption with little deterioration in gain and noise figure (NF). The transformer-based $g_{\mathrm {m}}$ -boost technique in the CG stage and neutralization technique in CS stage further enhances the RF performances. Inter-stage magnetically coupled resonator (MCR) extends the bandwidth. An elaborate analysis of the current-reused CG–CS LNA using a transformer-based $g_{\mathrm {m}}$ -boost technique and transformer-based MCR is proposed. Fabricated in 65-nm CMOS technology, the LNA achieves a measured power gain of 14.9 dB at 21 GHz with a −3-dB bandwidth of 4.8 GHz. The lowest NF is 3.3 dB at 19.5 GHz and is below 4 dB from 17 to 21 GHz. The LNA consumes 1.9 mW from a 1-V supply, with a chip area of 600 $\mu \text{m}\,\,\times $ 700 $\mu \text{m}$ .

A sub-1V dual-path noise and distortion canceling CMOS LNA for low power wireless applications

This paper presents a 0.8 ​V supply voltage low noise amplifier (LNA) with high linearity for low power wireless applications. To reduce both second- and third-order intermodulation components (IM2 and IM3), the proposed structure creates equal common-mode (CM) currents with the opposite sign by cascading two differential pairs with a cross-connected output and improves linearity. Using resistive feedback together with noise and distortion canceling technique mutually cancel noise and nonlinearity of both main and auxiliary amplifiers. Combining transformer-based gm-boosting and current reuse techniques makes the presented LNA a superior candidate for low power radios. Detailed analysis and simulations are provided to show the effectiveness of the proposed LNA structure. Simulation results using 65 ​nm CMOS process reveal that the linearized low power LNA achieves over 25 ​dB voltage gain, 2.7 ​dB NF, +10.1 dBm IIP3, and average IIP2 of more than +57 dBm while consuming 870 ​μW.

Design of Low-Power Low-noise CMOS ECG Amplifier for Smart Wearable Device

The artificial intelligence health care devices have focused on the portability and accuracy and the most trending area of wearable biomedical application has become the electrocardiogram (ECG) recording device. The ECG signals have the characteristic of low amplitude, prone to be influenced by Power Line Interference (PLI), so it is essential to achieve high gain and high common-mode rejection ratio (CMRR),while the input-referred noise and power consumption need to be low to realize the cardiac screening system on chip (Soc).In this paper, a low-noise low-power analog front end (AFE) amplifier which based on Driven-Right-Leg circuit(DRL) has been proposed. It was implemented in CMOS 180 nm with bias current and supply voltage of 12µA and 0.7V, respectively. The simulation results showed that this front-end circuit can achieve a low input referred noise of 4.11µV/Hz and high common mode rejection ratio of 135dB. It also gave voltage gain of 41.8 dB with the bandwidth from 0.1Hz to 100Hz and the total power consumption was 4.32µW. Compared with recently relevant whole circuit design, we believe that it is suitable to be used in smart wearable device.

A Submilliwatt K-Band Low-Noise Amplifier for Next Generation Radio Astronomical Receivers in 65-nm CMOS Process

An ultralow-power <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band low-noise amplifier (LNA) for next generation radio astronomical receivers fabricated in 65-nm CMOS technology is presented in this letter. A gate–source transformer feedback is utilized for the simultaneous noise and impedance matching. In order to achieve high gain with limited dc power consumption ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {dc}}$ </tex-math></inline-formula> ), a single-ended neutralization technique is applied to the circuit. According to measurement, the proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band LNA achieves a 19.1-dB small signal gain with 2.8-GHz 3-dB bandwidth (21.2–24 GHz) and noise figure of 3.6 dB with only 0.99 mW <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {dc}}$ </tex-math></inline-formula> . To the best of author’s knowledge, this LNA shows the highest figure of merit (FoM), which is 7071 1/W, among published <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band low-power LNAs.

A fabrication of a low-power low-noise neural recording amplifier based on flipped voltage follower

In this work, a fabrication of low-voltage low-power and low-noise neural recording amplifiers are presented. An operational transconductance amplifier (OTA) was built using the flipped voltage follower (FVF). The low noise operation is achieved without increasing the bias current of the input transistors or decreasing the aspect ratio of the output transistors, which leads to large overdrive voltage.This proposed OTA is used to build a biopotential amplifier using AC coupling technique to achieve one of the lowest noise efficiency factor (NEF) of 2.13. This bioamplifier is fabricated using UMC 130 ​nm CMOS process and the measurement results are obtained. The proposed OTA is also used to design a second biopotential amplifier using active low-frequency suppression technique to achieve one of the lowest occupied area of 0.047 ​mm2 while maintaining a reasonable Noise efficiency factor (NEF) of 4.27. The active low-frequency suppression technique is used to reject the DC offset voltage while preserving high input impedance and small area. The first bioamplifier consumes 2.2 ​μA from 1 ​V supply voltage. The input-referred noise is 3.7 μVrms. The bandwidth (BW) ranges from 25 ​Hz to 9.9 ​kHz. The achieved noise efficiency factor (NEF) is 2.13. The dynamic range is 55 ​dB. It occupies a silicon area of 0.112 ​mm2. The second bioamplifier consumes 5.2 ​μW from 1 ​V supply voltage. The input-referred noise is 4.7 μVrms. The BW ranges from 110 ​Hz to 9.7 ​kHz. The achieved NEF is 4.27. It occupies an area of 0.047 ​mm2.