Low Power Characteristics Research Articles

SiGNN: A spike-induced graph neural network for dynamic graph representation learning

In the domain of dynamic graph representation learning (DGRL), capturing the temporal evolution within real-world networks is of paramount importance. Spiking Neural Networks (SNNs), renowned for their temporal dynamics and low-power characteristics, provide an efficient solution for temporal processing in DGRL tasks. However, due to the spike-based information encoding mechanism of SNNs, existing DGRL methods that employ SNNs face significant limitations in their representational capacity. To address this issue, we propose an innovative framework named Spike-induced Graph Neural Network (SiGNN) for learning enhanced spatiotemporal representations on dynamic graphs. Specifically, we achieve a harmonious integration of SNNs and GNNs through a novel Temporal Activation (TA) mechanism. This mechanism enables SiGNN to effectively harness the temporal dynamics of SNNs while circumventing the representational constraints imposed by the binary nature of spikes. Furthermore, leveraging the inherent adaptability of SNNs, SiGNN incorporates an in-depth analysis of evolutionary patterns within graphs across multiple time granularities, thereby facilitating the acquisition of multiscale temporal node representations. Extensive experiments on various real-world dynamic graph datasets demonstrate the superior performance of SiGNN in the node classification task. Our code is publicly available at https://github.com/CharliedoD/SiGNN.

Layered Structure Modification of Sodium Vanadate through Ca/F Co‐Doping for Enhanced Energy Storage Performance

AbstractVanadate materials are promising for sodium‐ion batteries (SIBs) due to their low cost, high capacity, and high power characteristics enabled by vanadium's multiple oxidation states. However, their development is hindered by poor conductivity, suboptimal high‐rate performance, and limited cycle life. In this work, a layered structure modification strategy involving Ca/F co‐doping in sodium vanadate Na2CaV2O6F (CVF) is proposed to address these issues. Through a combination of experiments and density functional theory calculations, it is demonstrated that Ca/F synergies enhance the Na layer spacing in CVF, resulting in reduced crystal water content and volume shrinkage compared to Na2V2O6 (NVO). Additionally, Ca/F incorporation significantly mitigates the diffusion potential of Na+ within the material framework. The unmodified CVF sample exhibits a high reversible capacity of 220 mAh g−1 at 10 mA g−1 and an excellent rate capacity of 65.78 mAh g−1 at 400 mA g−1. Furthermore, the cathode material maintains a capacity of up to 138 mAh g−1 at 200 mA g−1 and retains 104.88 mAh g−1 after 100 cycles within the voltage range of 1.5−4.0 V. These findings enhance the understanding of the crystal structure of NVO cathode materials and pave the way for the rational design of high‐quality vanadate cathodes for SIBs.

STCSNN: High energy efficiency spike-train level spiking neural networks with spatio-temporal conversion

Brain-inspired spiking neuron networks (SNNs) have attracted widespread research interest due to their low power features, high biological plausibility, and strong spatiotemporal information processing capability. Although adopting a surrogate gradient (SG) makes the non-differentiability SNN trainable, achieving comparable accuracy for ANNs and keeping low-power features simultaneously is still tricky. In this paper, we proposed an energy-efficient spike-train level spiking neural network with spatio-temporal conversion, which has low computational cost and high accuracy. In the STCSNN, spatio-temporal conversion blocks (STCBs) are proposed to keep the low power features of SNNs and improve accuracy. However, STCSNN cannot adopt backpropagation algorithms directly due to the non-differentiability nature of spike trains. We proposed a suitable learning rule for STCSNNs by deducing the equivalent gradient of STCB. We evaluate the proposed STCSNN on static and neuromorphic datasets, including Fashion-Mnist, Cifar10, Cifar100, TinyImageNet, and DVS-Cifar10. The experiment results show that our proposed STCSNN outperforms the state-of-the-art accuracy on nearly all datasets, using fewer time steps and being highly energy-efficient.

Design analysis of a low-power, high-speed 8 T SRAM cell using dual-threshold CNTFETs

Recently, carbon nanotube field-effect transistors (CNTFETs) have garnered significant attention from VLSI engineers due to their exceptional electrical properties. This paper proposes a novel high-speed, low-power eight-transistor (8 T) static random-access memory (SRAM) cell based on 32-nm CNTFET technology. The SRAM cell was simulated using the HSPICE tool with a VDD of 0.9 V. The high-speed and low-power characteristics of the SRAM design are attributed to the high subthreshold slope and high carrier mobility of metal-oxide-semiconductor field-effect transistor (MOSFET)-like CNTFETs utilized in the simulations. The implementation of dual threshold transistors, coupled with a transmission gate for bitline access, contributes to the enhanced performance. Key performance metrics such as noise margins, power consumption, delay, and SRAM electrical quality metric (SEQM) of the proposed SRAM have been evaluated and compared with existing CNTFET-based SRAM designs. The proposed cell demonstrates reductions of 73.73%, 43.18%, and 58.70% in read power, write power, and hold power, respectively, compared to the lowest respective power values of other examined SRAM designs. The proposed SRAM ranks second, third, and second in write static noise margin (WSNM), hold static noise margin (HSNM), and read static noise margin (RSNM), respectively, among other designs. Additionally, the proposed SRAM exhibits the least sensitivity to parametric variations compared to other designs. The SEQM, which provides a comprehensive assessment of access times, noise margins, and power usage for the SRAM cell, has been calculated. The SEQM of the proposed SRAM is 10.6, 1.89, 13.15, and 1.82 times higher than that of C6T, BLP8T, Mani’s 10 T, and LP8T, respectively.

Modeling end-to-end delays in TSCH wireless sensor networks using queuing theory and combinatorics

Wireless communication offers significant advantages in terms of flexibility, coverage and maintenance compared to wired solutions and is being actively deployed in the industry. IEEE 802.15.4 standardizes the Physical and the Medium Access Control (MAC) layer for Low Power and Lossy Networks (LLNs) and features Timeslotted Channel Hopping (TSCH) for reliable, low-latency communication with scheduling capabilities. Multiple scheduling schemes were proposed to address Quality of Service (QoS) in challenging scenarios. However, most of them are evaluated through simulations and experiments, which are often time-consuming and may be difficult to reproduce. Analytical modeling of TSCH performance is lacking, as only one-hop communication with simplified traffic patterns is considered in state-of-the-art. This work proposes a new framework based on queuing theory and combinatorics to evaluate end-to-end delays in multihop TSCH networks of arbitrary topology, traffic and link conditions. The framework is validated in simulations using OMNeT++ and shows below 6% root-mean-square error (RMSE), providing quick and reliable latency estimation tool to support decision-making and enable formalized comparison of existing scheduling solutions.

Low-Power Magnetic Displacement Sensor Based on RISC-V Embedded System.

With the emergence of RISC-V architecture in embedded devices, its inherent low-power features have propelled its extensive adoption across various industrial settings. Displacement sensors leveraging Hall sensors and magnetic flux measurement present notable benefits including cost-effectiveness and compact design. This study undertakes the porting of Hall sensors onto RISC-V architecture embedded devices, validating their functionality within displacement sensors. Empirical investigations substantiate that the ported system consistently delivers comparable outcomes to those obtained from x86 architecture systems employing PM-MFM methods, affirming its reliability and performance in practical applications.

Dynamic performance and control analysis of supercritical CO2 brayton cycle for solid oxide fuel cell waste heat recovery

Due to the high-temperature operation of solid oxide fuel cell, recovering its exhaust waste heat is worthwhile. The supercritical CO2 cycle features low compression power consumption and high thermal efficiency, making it a promising power cycle. Therefore, this paper adopts the supercritical CO2 recompression cycle as the bottom cycle, combined with solid oxide fuel cell to form a joint system, further improving energy utilization. Given the long temperature response time of the solid oxide fuel cell and the variability of its exhaust waste heat with load changes, this paper innovatively proposes establishing an integrated dynamic model of the joint system, instead of directly providing heat source flow and temperature changes as in traditional research, to more accurately study the dynamic response of the cycle during solid oxide fuel cell startup and load variations. Based on this, a control strategy utilizing inventory control is proposed, and the feasibility of the control effect is verified. The research results indicate that the uncontrolled cycle may lead to safety issues with a significant increase in turbine inlet temperature when solid oxide fuel cell load increases. Under the control strategy, the turbine inlet temperature and main compressor inlet temperature are rapidly stabilized at the target values. The controlled cycle achieves higher efficiency compared to the uncontrolled cycle, particularly prominent during solid oxide fuel cell load reduction, with an efficiency increase of approximately 5.23%.

DAM SRAM CORE: An Efficient High-Speed and Low-Power CIM SRAM CORE Design for Feature Extraction Convolutional Layers in Binary Neural Networks.

This article proposes a novel design for an in-memory computing SRAM, the DAM SRAM CORE, which integrates storage and computational functionality within a unified 11T SRAM cell and enables the performance of large-scale parallel Multiply-Accumulate (MAC) operations within the SRAM array. This design not only improves the area efficiency of the individual cells but also realizes a compact layout. A key highlight of this design is its employment of a dynamic aXNOR-based computation mode, which significantly reduces the consumption of both dynamic and static power during the computational process within the array. Additionally, the design innovatively incorporates a self-stabilizing voltage gradient quantization circuit, which enhances the computational accuracy of the overall system. The 64 × 64 bit DAM SRAM CORE in-memory computing core was fabricated using the 55 nm CMOS logic process and validated via simulations. The experimental results show that this core can deliver 5-bit output results with 1-bit input feature data and 1-bit weight data, while maintaining a static power consumption of 0.48 mW/mm2 and a computational power consumption of 11.367 mW/mm2. This showcases its excellent low-power characteristics. Furthermore, the core achieves a data throughput of 109.75 GOPS and exhibits an impressive energy efficiency of 21.95 TOPS/W, which robustly validate the effectiveness and advanced nature of the proposed in-memory computing core design.

BEANet: An Energy-efficient BLE Solution for High-capacity Equipment Area Network

The digital transformation of factories has greatly increased the number of peripherals that need to connect to a network for sensing or control, resulting in a growing demand for a new network category known as the Equipment Area Network (EAN). The EAN is characterized by its cable-free, high-capacity, low-latency, and low-power features. To meet these expectations, we present BEANet , a novel solution designed specifically for EAN that combines a two-stage synchronization mechanism with a time division protocol. We implemented the system using commercially available Bluetooth Low Energy (BLE) modules and evaluated its performance. Our results show that the network can support up to 150 peripherals with a packet reception rate of 95.4%, which is only 0.9% lower than collision-free BLE transmission. When the cycle time is set to 2 s, the average transmission latency for all peripherals is 0.1 s, while the power consumption is 18.9 μW, which is only half that of systems using LLDN or TSCH. Simulation results also demonstrate that BEANet has the potential to accommodate over 30,000 peripherals under certain configurations.

Electrolyte‐Gated Vertical Transistor Charge Transport Enables Photo‐Switching

AbstractProposals for new architectures that shorten the length of the transistor channel without the need for high‐end techniques are the focus of very recent breakthrough research. Although vertical and electrolyte‐gate transistors are previously developed separately, recent advances have introduced electrolytes into vertical transistors, resulting in electrolyte‐gated vertical field‐effect transistors (EGVFETs), which feature lower power consumption and higher capacitance. Here, EGVFETs are employed to study the charge transport mechanism of spray‐pyrolyzed zinc oxide (ZnO) films to develop a new photosensitive switch concept. The EGVFET's diode cell revealed a current‐voltage relationship arising from space‐charge‐limited current (SCLC), whereas its capacitor cell provided the field‐effect role in charge accumulation in the device's source perforations. The findings elucidate how the field effect causes a continuous shift in SCLC regimes, impacting the switching dynamics of the transistor. It is found ultraviolet light may mimic the field effect, i.e., a pioneering demonstration of current switching as a function of irradiance in an EGVFET. The research provides valuable insights into the charge transport characterization of spray‐pyrolyzed ZnO‐based transistors, paving the way for future nano‐ and optoelectronic applications.

HDS: Heterogeneity-aware dual-interface scheduling for energy-efficient delay-constrained data collection in IoT

With the advancements in low-power and miniature electronics, various smart devices are deployed and interconnected as the Internet of Things (IoT), collecting a massive amount of data from surrounding environments. Despite the popularity of ZigBee for low-power communications in IoT, WiFi has recently been recommended for data collection in IoT for its high data rate, high reliability, native IP compatibility, and vastly-deployed infrastructures. However, it is well known that WiFi is energy-consuming. Although many schemes have been designed to reduce WiFi energy consumption, they usually suffer from the dilemma that a longer (shorter) sleep of WiFi gives a lower (higher) energy consumption but a larger (smaller) latency, hindering the use of WiFi in a wide range of IoT applications that require a certain level of quality of service (QoS). To this end, we propose a Heterogeneity-aware Dual-interface Scheduling (HDS) scheme to fully exploit the heterogeneity between ZigBee and WiFi to realize energy-efficient and delay-constrained data collection in a tree-based IoT network, where each device is equipped with a ZigBee and a WiFi interface. The low-power feature of ZigBee is utilized as much as possible for high energy efficiency, while the high-reliability advantage of WiFi is leveraged when the ZigBee link quality is low for delay guarantee. Under network dynamics, HDS jointly allocates ZigBee and WiFi schedules to strike a balance between energy and delay for optimized performance. A prototype system is built atop an IoT platform integrated with commercial off-the-shelf ZigBee and WiFi modules. Experiment results show that the energy consumption of HDS is 80.3% and 43.6% lower than the standard power saving protocol and a state-of-the-art dual-interface scheme, respectively, under a moderate delay constraint. Additionally, the percentage of data packets that satisfy the delay constraint is above 98.6%.

Compact high-[formula omitted] Slot Loaded Dielectric Resonator Filtering Antenna for LoRa applications

High-Q antennas are highly sought after for their narrow bandwidth and compact size, enabling them to occupy minimal volume in a given structure. In this paper, we present a new ultra-narrow band filter/antenna designed for LoRa applications. The filter/antenna consists of an elliptical slot loaded with a high permittivity rectangular dielectric resonator, excited by a coupled microstrip line. The proposed antenna serves not only as a radiating element but also as a filter, offering the significant benefit of eliminating loss between the filter and the antenna. To assess the influence of the SMA power cable on miniature antennas, we conducted a comparison of the antenna with and without a radio frequency (RF) module, focusing on radiation pattern. Our proposed filter/antenna provides a compact profile of 25 × 40 mm2 (λ/13×λ/8), an omnidirectional radiation pattern, and remarkable rejection in the stop-band. The validity of the proposed design is accomplished by comparing the electromagnetic simulation with fabrication and measurement results, achieving a high level of agreement between simulation and measurement. Thanks to its exceptional performance, small size, low cost, and low-power characteristics, this innovative structure is suitable for IoT applications at UHF band with a stop-band outside this frequency to avoid potential interference from adjacent bands.

Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process

Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process

Flexible SnO2–MoS2 based memristive device exhibiting stable and enhanced memory phenomenon

Flexible non-volatile memory devices have been gaining interest in expanding the digital data storage world. Due to the burgeoning advancement in the healthcare industry, the Internet of Things, and wearable electronics, the demand for ultra-thin, low-power, and flexible memory is increasing. Further, the advancement of synthesis procedures for two-dimensional nanomaterials having better optical, electrical, and mechanical strength with flexibility has fuelled the flexible memory device area, as commonly used flash memory is approaching its physical limit. In this context, the present work reports the flexible resistive switching memory device based on pure molybdenum disulfide (MoS2) and tin oxide (SnO2) based nanocomposite powder synthesized using the simple hydrothermal process. The nanocomposite formation was characterized using x-ray diffraction and Raman spectroscopic techniques. The memory device was fabricated by spin-coating the pure MoS2, pure SnO2, and MoS2–SnO2 nanocomposite film over the ITO-PET flexible substrate. The device was completed by thermally evaporating the thin Al layer through a shadow mask. It was found that MoS2–SnO2 based memory devices exhibited improved switching performance having a higher I ON/I OFF ratio, and lower switching voltage in comparison to pure MoS2 and pure SnO2-based devices (I ON/I OFF ratio ∼100, V = 0.5 V). Furthermore, to check the stability and cyclic performance of the fabricated device, the retention and endurance test was also performed, and the MoS2–SnO2 device retained the HRS and LRS states up to 2 × 103s and showed stable performance up to 100 switching cycles without much degradation, respectively. It should be mentioned that the presently proposed ReRAM device based on SnO2 and MoS2 with flexible and low-power features had excellent potential for use in the wearable device industry.

A two-stage spiking meta-learning method for few-shot classification

In recent years, deep spiking neural networks (SNNs) have demonstrated promising performance across various applications, owing to their low-power characteristics. Research on SNN meta-learning has enabled SNNs to reduce both label cost and computational power consumption in few-shot classification tasks. However, current SNN meta-learning methods still lag behind traditional artificial neural networks (ANNs) in terms of accuracy. In this work, we explore a two-stage metric-based SNN meta-learning framework that achieves the highest accuracy performance in SNN. This framework comprises a pre-training stage and a meta-training stage. During pre-training, a classification embedding SNN model (CESM) is trained to extract image features. Subsequently, in the meta-training stage, the meta embedding SNN model (MESM) employs the centered kernel alignment (CKA) method to measure the similarity between these learned features for meta-learning. We conduct extensive experiments on the Omniglot, tieredImageNet, and miniImageNet datasets, evaluating both CESM and MESM models. Experimental results demonstrate that the proposed framework improves performance by 5% on average compared to previous SNN meta-learning approaches. The proposed method surpasses the early classical ANN methods and further closes the gap with ANN state-of-the-art methods.

High performance self-powered photodetector based on van der Waals heterojunction

Self-powered photodetectors that do not require external power support are expected to play a key role in future photodetectors due to their low power characteristics, but achieving high responsivity remains a challenge. 2D van der Waals heterojunctions are a promising technology for high-performance self-powered photodetectors due to their excellent optical and electrical properties. Here, we fabricate a self-powered photodetector based on In2Se3/WSe2/ReS2 van der Waals heterojunction self-powered photodetector. Due to the presence of ReS2 layer, photocurrent is enhanced as a result of the increase in light absorption efficiency and the effective region for generating photogenerated carriers. The built-in electric field is enhanced by a negative ‘back-gate voltage’ along the p–n junction vertical direction generated by the electrons in the photo-generated electrons accumulation layer. Accordingly, the optical responsivity and the photoresponse speed of this heterojunction self-powered photodetector are greatly boosted. The proposed self-powered photodetector based on the In2Se3/WSe2/ReS2 heterojunction exhibits a high responsivity of 438 mA W−1, which is 17 times higher compared to the In2Se3/WSe2 photodetector, a self-powered current (1.1 nA) that is an order of magnitude higher than that of the In2Se3/WSe2 photodetector, and a fast response time that is 250% faster. Thus the self-powered photodetector with a stronger built-in electric field and a wider depletion zone can provide a new technological support for the fabrication of high responsivity, low power consumption and high speed self-powered photodetectors based on van der Waals heterojunctions.

Optical Electric Current Transformer for Monitoring Its Performance in the Substation

The optical electric current transformer (OECT) is an important measuring and protection equipment in the power system. Its accuracy and reliability are vital to the power system’s safe, reliable, and economical operation. Because the energy supply of a high-voltage side data acquisition system is the biggest obstacle in developing this kind of transformer, a low-power data acquisition system of OECT is designed from cost, reliability, accuracy, and practicability. In the design process, the low-power microcontroller MSP430 produced by TI company is used for control. Its rich on-chip and off-chip function modules and ultra-low power performance meet the system’s requirements. The 16-bit low-power high-speed chip ADS8325 is used as an A/D converter to ensure the instantaneity and accuracy of data acquisition and the low-power characteristics of the system. The optical fiber digital transmission system is utilized to achieve high/low voltage electrical isolation, and the low-power optical fiber transmission drive circuit is devised. After the main hardware design is completed, the software is adjusted and used in the electric energy monitoring of the substation. The test shows that the error of three-phase current and three-phase voltage is less than 2%. After setting the voltage amplitude, current amplitude, and power factor, the error of its active and reactive power is less than 2% after electric energy monitoring. After multiple harmonic tests, the measurement errors of voltage harmonics and current harmonics are smaller than 5%, that is, the measurement results of each index achieve high measurement accuracy.

Surface acoustic wave-tuned plasmonic resonances in liquid crystal-covered gold nanostructures

In this work, we propose an acoustically tunable plasmonic device based on liquid crystal (LC)-covered gold nanostructures. By utilizing the standing surface acoustic waves (SSAWs) to realign LC molecules, one can effectively tune the effective refractive index of LCs, and subsequently tune localized surface plasmon resonances (LSPRs) of the gold nanostructures. A 15 nm blue shift of the LSPR peak with the driving voltage of 400 mVpp is experimentally observed. Upon removal of the applied SSAWs, the LC molecules can return to their original orientation, and so does the LSPR peak. Besides the excellent reversibility, this active plasmonic device also features low power consumption and easy integration, which could find many potential applications including switches, modulators, and couplers.

Hybrid Nanoparticle/DNAzyme Electrochemical Biosensor for the Detection of Divalent Heavy Metal Ions and Cr3.

A hybrid noble nanoparticle/DNAzyme electrochemical biosensor is proposed for the detection of Pb2+, Cd2+, and Cr3+. The sensor takes advantage of a well-studied material that is known for its selective interaction with heavy metal ions (i.e., DNAzymes), which is combined with metallic nanoparticles. The double-helix structure of DNAzymes is known to dissociate into smaller fragments in the presence of specific heavy metal ions; this results in a measurable change in device resistance due to the collapse of conductive inter-nanoparticle DNAzyme bridging. The paper discusses the effect of DNAzyme anchoring groups (i.e., thiol and amino functionalization groups) on device performance and reports on the successful detection of all three target ions in concentrations that are well below their maximum permitted levels in tap water. While the use of DNAzymes for the detection of lead in particular and, to some extent, cadmium has been studied extensively, this is one of the few reports on the successful detection of chromium (III) via a sensor incorporating DNAzymes. The sensor showed great potential for its future integration in autonomous and remote sensing systems due to its low power characteristics, simple and cost-effective fabrication, and easy automation and measurement.

Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier

With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product.