Low-power Dynamic Comparator Research Articles

Design of low power dynamic comparator with reduced kickback noise technique for bio-medical applications

The latched comparator is an essential element found in all analogue-to-digital converter (ADC) architectures. The present study aims to develop a latched comparator with the objective of mitigating kickback noise. The present study presents an analysis of a low-power dynamic comparator specifically designed for biomedical applications, with a voltage operation of 1 V. This study presents the implementation of a dynamic latched comparator utilising the sampling switch technique to mitigate kick-back noise. The comparator is designed to minimise power consumption while maintaining the integrity of the signal by mitigating the impact of noise. The comparator employs CMOS technology with a feature size of 45 nm. The comparator that is recommended exhibits superior performance compared to existing state-of-the-art comparators.

Low Power Dynamic Comparator design in 90nm technology

Low Power Dynamic Comparator design in 90nm technology

A 180 nA Quiescent Current Digital Control Dual-Mode Buck Converter With a Pulse-Skipping Load Detector for Long-Range Applications

A digitally controlled dual-mode buck converter using low quiescent current is proposed in this work. In particular, the proposed dual pulse-skipping mode adopts a pulse-skipping adaptive on-time (PSAOT) mode for heavy load; and a pulse-skipping asynchronous mode (PSAM) for light and ultra-light loads to achieve a 100,000X wide load range for the Long-range (LoRa) application. Specifically, the pulse-skipping mode selector adopts a digital logic circuit to realize the 180nA low quiescent current. In addition, a low-power dynamic comparator with an adjustable offset is used to accelerate the transient response. The proposed converter is fabricated in a TSMC 350 nm CMOS process and results in an output voltage of 3.3 V from 5V to 4.2 V input voltage range. These results show that the overall system achieves 92.9 % peak eficiency at 8 mA output load and a figure of merit (FoM) of 2.29.

Design of Low Power Low Offset Dynamic latch Comparator using DTMOS Technique

Analog to Digital converters plays an essential role in signal processing and medical applications. SAR ADC is best suited for biomedical applications because of its low power and medium resolution. Low power dynamic comparators are essentially desired in the design of SAR ADC. In this paper, a low power dynamic type latch comparator is designed which is based on Dynamic Threshold Metal Oxide Semiconductor (DTMOS ) technique to reduce the power dissipation which is achieved by reducing the supply voltage. The circuit has been implemented at the supply voltage of 0.8 V. The simulations for this comparator are carried out in CADENCE SPECTRE using 45nm CMOS technology. The simulation outcomes validate that the designed dynamic latch comparator with DTMOS techniques is 20% more power saving in comparison to the conventional comparator. The total power consumption is as low as 156.18nW which makes it suitable for low-power bio-medical applications.

A 10 bit 1 MS/s SAR ADC with one LSB common-mode shift energy-efficient switching scheme for image sensor

A 10 bit 1 MS/s SAR ADC with one LSB common-mode shift energy-efficient switching scheme for image sensor is presented. Based on the two sub-capacitor arrays architecture and the common-mode technique, the proposed switching scheme achieves 98.45% less switching energy over the conventional architecture with common-mode shift in one LSB. The comparator uses a low power dynamic comparator. The sampling switch adopts a bootstrap circuit with low sampling error. SAR logic is composed of Bit-Slice circuit with low power consumption and few transistors. Simulated in 180 nm CMOS process and 1 MS/s sampling rate, the ADC achieves the 60.06 dB SNDR, the 75.43 dB SFDR and the 10.45 μW power consumption.

A 0.2-V 1.2 nW 1-KS/s SAR ADC with a novel comparator structure for biomedical applications

In this paper, a modified successive-approximation-register analog-to-digital converter (SAR ADC) with a novel low power dynamic comparator at 0.2 V supply voltage is presented. The power consumption of SAR ADC has been reduced by 70% with design of proposed low-power comparator and using power reduction techniques such as power gating and reducing the supply voltage. Also, by custom design for unit capacitor in the SAR ADC, the area has been reduced by 46% compared to the conventional structure. The proposed ADC with a sampling frequency of 1 kS/s and power consumption of only 1.21 nW for biomedical applications has been designed and simulated in a TSMC 65 nm CMOS technology and occupies an area of 0.013 mm2. The proposed biomedical ADC is verified using analog electroencephalogram (EEG) and electrocardiogram (ECG) inputs which demonstrate it is proper to quantize these biosignals. The figure-of-merit (FOM) of the proposed converter is 3.2 fJ/conversion-step.

Design and Analysis of CMOS Dynamic Comparator for High-Speed Low-Power Applications Using Charge Sharing Technique

Analog–digital converters (ADCs) are electronic circuits that convert continuous time signals into digital signals (binary data) for analyzing, estimation, and transmission. Transceivers use ADC in the baseband stage of receiver to convert the analog signals to digital form for further signal processing. At high-frequency applications, like millimeter wave applications, the ADC consumes more power due to the high sampling rate with respect to the increased bandwidth. In this article, a novel dynamic comparator is presented with delay and power analysis for the design. The expression is derived for all operational regions of the transistor. The new design is proposed for low-power consumption and reduced delay of the circuit. The novel design overcomes the drawbacks of the less operating frequency range, high latency, and more power dissipation of existing comparator designs. The proposed low-power dynamic comparator is simulated with 45 nm CMOS technology that provides total power dissipation of 33.92 µW, delay of 19.71 ps, and energy per conversion of 0.19 fJ/conv. with a supply voltage of 1 V.

The High-Speed Low-Power Dynamic Comparator

This paper comments on four works for the optimization of comparator design. Today, with the development of integrated circuits, the requirements for comparators about low power, low delay, few offset voltage, and low noise are highly desirable. Specifically, these works made progress in the conventional comparator, which comprises a preamplifier and a latch. They also solved some problems, such as decreasing power and delay. Some works employ a positive feedback cross-coupled pares to provide a larger gain in the preamplifier, use PMOS switch transistors to accelerate the definition phase, or a double-tail architecture to increase the latch regeneration speed. Other work designs a charge pump to improve speed.

Design and Implementation of Low-Power Dynamic Comparator

Dynamic comparators are highly utilized in design of high-speed digital circuits. More precisely, Low power and high-speed dynamic comparators are the key elements in manufacturing of CPUs in many electronic devices. These CPUs consist of many comparison circuits known as comparators. This journal paper presents a low voltage thereby a low power Double Tail Dynamic Comparator (DTDC) with relatively less power consumption when compared to existing designs. In this journal paper, various types of dynamic comparators are discussed and compared with the proposed design. Dynamic comparators based on Double Tail technique, floating inverter amplifier technique and regenerative latch technique etc., are compared to the proposed design. This design is simulated using 250nm technology with the aid of Tanner EDA simulation tool. The pre-amplification process in this proposed design is implemented using Self-biasing technique. Self-biasing technique produces low kick back noise during the operation of this proposed design. The simulated results are mentioned below.

Analysis of Low Power Dynamic Comparator

Low power consumption, high performance dynamic comparators are widely used in high-speed Analog to Digital Converters (ADCs) and advanced input/output circuits. Mostly unique comparators utilize the latching stage thorough cross-coupled inverters, which gives a solid positive feedback, to fasten the comparison and reduce the static- power dissipation. In this paper, the analysis of dynamic comparators having best performance parameters in terms of power dissipation is presented. This is achieved by adopting low power techniques like adding transistors and sizing them to get efficient circuit. The proposed circuits are able to reduce power dissipation from 40-50%.

LOW-POWER DYNAMIC COMPARATOR WITH HIGH PRECISION FOR SAR ADC

In this work, low-power dynamic comparator is presented with auto-zeroing technique for successive approximation register (SAR) analogue-to-digital converter (ADC). The comparator designed with DTMOS technique operates in subthreshold region. The designed circuit consumes low power with high gain. The dynamic range of the comparator is increased with a new biasing technique for DTMOS transistors. The core design consumes 6.01µW power and overall design consumes 17.06µW. The design is realized with two different supply voltage with 600mV (core design) and 1.8V (biasing circuit). The comparator has been simulated with 0.18µm TSMC process in Cadence environment.

Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The simulation result show that the proposed comparator circuit achieved significant reduction of power consumption and delay during worst case condition compared to dynamic comparator proposed from previous researchers.

A Low-Power 1-V Supply Dynamic Comparator

This letter presents a low-power dynamic comparator for ultralow power applications. The prototype is designed in a 65-nm CMOS process with a supply voltage of 1 V and is compared against the widely used double tail latch comparator in terms of power consumption and input referred rms noise. The addition of cross-coupled devices to the input differential pair prevents the comparator internal nodes from fully discharging to ground in contrast to the conventional architecture. This reduces the power consumption while achieving similar noise levels. Measurements demonstrate that the proposed comparator achieves an input referred rms noise voltage of 220 $\mu \text{V}$ against 210 $\mu \text{V}$ for the conventional comparator with a 30% reduction in power. The proposed circuit consumes 0.19-pJ energy per comparison.

A novel high-speed low-power dynamic comparator with complementary differential input in 65 nm CMOS technology

The demand for high-performance analog-to-digital converters is pushing toward the utilization of small dynamic comparators with low power consumption, low offset voltage, high speed, and independent input common-mode voltage. In this paper, a new high-speed dynamic comparator is presented, which its delay time is decreased compared to conventional dynamic comparators. In the suggested comparator, a complementary differential pair is utilized in the input to improve the offset voltage and comparison speed. The equations related to the delay time and input referred offset voltage of the proposed structure are derived, and the effective parameters to reduce them are identified. The post-layout simulation results in 65 nm CMOS technology demonstrate that the clock frequency of the proposed comparator can be 6 GHz while the delay time is 42.7 ps. The power consumption is 381 μW when the proposed comparator is supplied with 1.2 V. Also, the occupied area is 141.7 μm2.

A low-power dynamic comparator for low-offset applications

In this paper, a low-power method for double-tail comparators is introduced. Using the proposed method, the power consumption of the pre-amplifier which is the dominant part is reduced considerably. Thanks to this method, the pre-amplifier is not able to draw more than required amount of power, therefore, the power is saved. Post layout and corner simulation results show the power consumption is reduced by about 40%. Moreover, several Monte-Carlo (M) simulations suggest the proposed method results in about 20% offset reduction at the cost of 5% area and 10% speed degradation.

A 10-bit 110 MHz SAR ADC with asynchronous trimming in 65-nm CMOS**Project supported by the Science and Technology on Analog Integrated Circuit Laboratory (No. 9140C090105140C09041).

A 10-bit 110 MHz SAR ADC with asynchronous trimming is presented. In this paper, a high linearity sampling switch is used to produce a constant parasitical barrier capacitance which would not change with the range of input signals. As a result, the linearity of the SAR ADC will increase with high linearity sampled signals. Farther more, a high-speed and low-power dynamic comparator is proposed which would reduce the comparison time and save power consumption at the same time compared to existing technology. Additionally, the proposed comparator provides a better performance with the decreasing of power supply. Moreover, a highspeed successive approximation register is exhibited to speed up the conversion time and will reduce about 50% register delay. Lastly, an asynchronous trimming method is provided to make the capacitive-DAC settle up completely instead of using the redundant cycle which would prolong the whole conversion period. This SAR ADC is implemented in 65-nm CMOS technology the core occupies an active area of only 0.025 mm and consumes 1.8 mW. The SAR ADC achieves SFDR > 68 dB and SNDR > 57 dB, resulting in the FOM of 28 fJ/conversion-step. From the test results, the presented SAR ADC provides a better FOM compared to previous research and is suitable for a kind of ADC IP in the design SOC.

A low-power low-offset dynamic comparator for analog to digital converters

A comparator comprises a cross coupled circuit which produces a positive feedback. In conventional comparators, the mismatch between the cross coupled circuits determines the trade-off between the speed, offset and the power consumption of the comparator. A new low-offset low-power dynamic comparator for analog-to-digital converters is introduced. The comparator benefits from two stages and two operational phases to reduce the offset voltage caused by the mismatch effect inside the positive feedback circuit. Rigorous statistical analysis yields the input referred offset voltage and the delay of the comparator based on the circuit random parameters. The derivations are verified with exhaustive Monte-Carlo simulations at various corner cases of the process. A comparison between typical comparator and the proposed comparator in 180nm and 90nm has been made. The power consumption of the proposed comparator is about 44% of the conventional and its offset voltage is at least one-third of other mentioned conventional comparators.