Design of low power dynamic comparator with reduced kickback noise technique for bio-medical applications

Abstract

The latched comparator is an essential element found in all analogue-to-digital converter (ADC) architectures. The present study aims to develop a latched comparator with the objective of mitigating kickback noise. The present study presents an analysis of a low-power dynamic comparator specifically designed for biomedical applications, with a voltage operation of 1 V. This study presents the implementation of a dynamic latched comparator utilising the sampling switch technique to mitigate kick-back noise. The comparator is designed to minimise power consumption while maintaining the integrity of the signal by mitigating the impact of noise. The comparator employs CMOS technology with a feature size of 45 nm. The comparator that is recommended exhibits superior performance compared to existing state-of-the-art comparators.