Low-power Digital Signal Processor Research Articles

The Reconfigurable Instruction Cell Array

This paper presents a novel instruction cell-based reconfigurable computing architecture for low-power applications, thereafter referred to as the reconfigurable instruction cell array (RICA). For the development of the RICA, a top-down software driven approach was taken and revealed as one of the key design decisions for a flexible, easy to program, low-power architecture. These features make RICA an architecture that inherently solves the main design requirements of modern low-power devices. Results show that it delivers considerably less power consumption when compared to leading VLIW and low-power digital signal processors, but still maintaining their throughput performance.

Study of an adaptive frame size predictor to enhance energy conservation in wireless sensor networks

Technological advances in low-power digital signal processors, radio frequency (RF) circuits, and micromechanical systems (MEMS) have led to the emergence of wirelessly interconnected sensor nodes. The new technological possibilities emerge when a large number of tiny intelligent wireless sensor nodes are combined. The sensor nodes are typically battery operated and, therefore, energy constrained. Hence, energy conservation is one of the foremost priorities in design of wireless sensor networks (WSNs) protocols. Limited power resources and bursty nature of the wireless channel are the biggest challenges in WSNs. Link adaptation techniques improve the link quality by adjusting medium access control (MAC) parameters such as frame size, data rate, and sleep time, thereby improving energy efficiency. In This work, our study emphasizes optimizing WSNs by building a reliable and adaptive MAC without compromising fairness and performance. Here, we present link adaptation techniques at MAC layer to enhance energy efficiency of the sensor nodes. The proposed MAC uses a variable frame size instead of a fixed frame size for transmitting data. In order to get accurate estimations, as well as reducing the computation complexity, we utilize the extended Kalman filter to predict the optimal frame size for improving energy efficiency and goodput, while minimizing the sensor memory requirement. Next, we designed and verified different network models to evaluate and analyze the proposed link adaptation schemes. The correctness of the proposed theoretical models have been verified by conducting extensive simulations. We also prototype the proposed scheme with the MAC protocol on Berkeley Motes. Both prototype and simulation results show that the proposed algorithms improve the energy efficiency by up to 15%.

Design optimization of low-power high-performance DSP building blocks

In recent years, power dissipation along with silicon area has become the key figure in chip design. The increasing demands on system performance require high-performance digital signal processing (DSP) systems to include dedicated number-crunching units as individually optimized building blocks. The various design methodologies in use stress one of the following figures: power dissipation, throughput, or silicon area. This paper presents a design methodology reducing any combination of cost drivers subject to a specified throughput. As a basic principle, the underlying optimization regards the existing interactions within the design space of a building block. Crucial in such optimization is the proper dimensioning of device sizes in contrast to the common use of minimal dimensions in low-power implementations. Taking the design space of an FIR filter as an example, the different steps of the design process are highlighted resulting in a low-power high-throughput filter implementation. It is part of an industrial read-write channel chip for hard disks with a worst case throughput of 1.6 GSamples/s at 23 mW in a 0.13-/spl mu/m CMOS technology. This filter requires less silicon area than other state-of-the-art filter implementations, and it disrupts the average trend of power dissipation by a factor of 6.

Reliable low-power digital signal processing via reduced precision redundancy

In this paper, we present a novel algorithmic noise-tolerance (ANT) technique referred to as reduced precision redundancy (RPR). RPR requires a reduced precision replica whose output can be employed as the corrected output in case the original system computes erroneously. When combined with voltage overscaling (VOS), the resulting soft digital signal processing system achieves up to 60% and 44% energy savings with no loss in the signal-to-noise ratio (SNR) for receive filtering in a QPSK system and the butterfly of fast Fourier transform (FFT) in a WLAN OFDM system, respectively. These energy savings are with respect to optimally scaled (i.e., the supply voltage equals the critical voltage V/sub dd-crit/) present day systems. Further, we show that the RPR technique is able to maintain the output SNR for error rates of up to 0.09/sample and 0.06/sample in an finite impulse response filter and a FFT block, respectively.

CADRE: An Asynchronous Embedded DSP for Mobile Phone Applications

Asynchronous design techniques have a number of compelling features that make them suited for complex system on chip designs. However, it is necessary to develop practical and efficient design techniques to overcome the present shortage of commercial design tools. This paper describes the development of CADRE (Configurable Asynchronous DSP for Reduced Energy), a 750K transistor, high performance, low-power digital signal processor IP block intended for digital mobile phone chipsets. A short time period was available for the project, and so a methodology was developed that allowed high-level simulation of the design at the earliest possible stage within the conventional schematic entry environment and simulation tools used for later circuit-level performance and power consumption assessment. Initial modeling was based on C behavioral models of the various data and control components, with the many asynchronous control circuits required automatically generated from their specifications. This has enabled design options to be explored and unusual features of the design, such as the Register Bank which is designed to exploit data access patterns, are presented along with the power and performance results of the processor as a whole.

44.6% processing cycles reduction in GSM voice coding by low-power reconfigurable co-processor architecture

A reconfigurable architecture oriented to low-power digital signal processing is presented, synthesised and tested on ETSI-GSM voice coding algorithms. An overall reduction of 44.6% cycles with respect to standard RISC processors is obtained. Such improvement together with locality and temporal correlation allows a reduction of power consumption.

A novel approach to high-level switching activity modeling with applications to low-power DSP system synthesis

We address high-level synthesis of low-power digital signal processing (DSP) systems by using efficient switching activity models. We present a technology-independent hierarchical scheme that can be easily integrated into current communications/DSP CAD tools for comparing the relative power/performance of two competing DSP designs without specific knowledge of transistor-level details. The basic building blocks considered for such systems are a full adder, a half adder, and a one-bit delay. Estimates of the switching activity at the output of these primitives are used to model the activity in more complex building blocks of DSP systems. The presented hierarchical method is very fast and simple. The accuracy of estimates obtained using the proposed approach is shown to be within 4% of the results obtained using extensive bit-level simulations. Our approach shows that the choice of multiplier/multiplicand is important when using array multipliers in a datapath. If the input signal with smaller mean square value is chosen as the multiplicand, almost 20% savings in switching activity can be achieved. This observation is verified by an analog simulation using a 16 /spl times/ 16 bit array multiplier implemented in a 0.6-/spl mu/ process with 3.3 V supply voltage.

Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System

In this paper, we first present a reconfigurable architecture template for low-power digital signal processing, and then an energy conscious design methodology to bridge the algorithm to architecture gap. The energy efficiency of such an architecture and the effectiveness of the methodology are demonstrated in case study implementations targeting baseband voice processing and digital signal processing.

A 660-/spl mu/W 50-Mops 1-V DSP for a hearing aid chip set

This article presents the flow and techniques used to design a low-power digital signal processor chip used in a hearing aid system implementing multiband compression in 20 bands, pattern recognition, adaptive filtering, and finescale noise cancellation. The pad limited 20 mm/sup 2/ chip contains 1.3 M transistors and operates at 2.5 MHz under 1.05-V supply voltage. Under these conditions, the DSP consumes 660 /spl mu/W and performs 50 million 22-bit operations per second, therefore achieving 0.013 mW/Mops (milli-watts per million operations), which is a factor of seven better than prior results achieved in this field. The chip has been manufactured using a 0.25-/spl mu/m 5-metal 1-poly process with normal threshold voltages. This low-power application-specific integrated circuit (ASIC) relies on an automated algorithm to silicon flow, low-voltage operation, massive clock gating, LP/LV libraries, and low-power-oriented architectural choices.

A low-power DSP core-based software radio architecture

This paper describes an approach to developing a low-power digital signal processor (DSP) subsystem architecture for advanced software radio platforms. The architecture is intended to support next-generation wide-band spread-spectrum military waveforms. The methodology illustrates how a next-generation programmable DSP core forms the basis for an application-specific integrated circuit (ASIC). It also shows how semiconductor technologies can be integrated into such chips to achieve algorithm performance while minimizing subsystem power consumption. The ASIC is run-time configurable to maintain high flexibility. The range of RF channel modulation (waveforms) and air interfaces is intended to include both wide-band and traditional narrow-band waveforms. Estimated gate counts and power-consumption estimates are presented. DSP circuit-design and power-management strategies necessary to achieve low-power operation are presented. While the architecture discussion focuses on military waveforms, the approach is also applicable to commercial waveforms.

Multimedia processors

This paper describes large-scale-integration programmable processors designed for multimedia processing such as real-time compression and decompression of audio and video as well as the generation of computer graphics. As the target of these processors is to handle audio and video in real time, the processing capability must be increased tenfold compared to that of conventional microprocessors, which were designed to handle mainly texts, figures, tables, and photographs. To clarify the advantages of a high-speed multimedia processing capability, we define these chips as multimedia processors. General-purpose microprocessors for workstations and personal computers (PCs) use special built-in hardware for multimedia processing, so the multimedia processors described include these modified general-purpose microprocessors. After reviewing the history of programmable processors, we classify multimedia processors into five categories depending on their basic architecture. The categories are reduced instruction set computer (RISC) microprocessors for workstations, complex instruction set computer microprocessors for PCs, embedded RISCs, low-power digital signal processors (DSPs), which are mainly used for mobile communications devices, and media processors that support PCs for multimedia applications. These five classes are then grouped into two: microprocessors with a multimedia instruction set and highly parallel DSPs. An architectural comparison between these two groups on the basis of Moving Picture Experts Group decoding applications is made, and the advantages and disadvantages of each class are clarified. Future processors, including system on a chip, and their applications are also discussed.

Highly sensitive motion detection with a combined microwave-ultrasonic sensor

High sensitivity to motion along with maximum robustness against false alarms are necessary requirements for a motion detector in an intruder-alarm sensor system. To achieve this goal, a combination of a microwave and an ultrasonic motion detector is considered. This solution is based on the fact that microwave and ultrasonic signals reflected from moving targets are modulated with coherent Doppler frequencies, whilst distortions affect both waves in a random way. Two alternative algorithms for the evaluation of the Doppler frequency coincidence are presented, based on the evaluation of the Doppler phase shift and the cross-correlation between the microwave and ultrasonic Doppler signals. Necessary conditions for an optimum motion detection and processing algorithms to minimize the false-alarm probability are developed. Results from measurements with a combined alarm sensor using 24 GHz c.w. radar and 40 kHz c.w. ultrasound are given and a cost-effective processing scheme with minimum hardware requirements, implemented on a low-power digital signal processor, is described.

A low power DSP engine for wireless communications

This paper describes the architecture and the performance of a new programmable 16-bit digital signal processor (DSP) engine. It is developed specifically for next generation wireless digital systems and speech applications. Besides providing a basic instruction set, similar to current day 16-bit DSPs, it contains extra architectural features and unique instructions, which make the engine highly efficient for compute-intensive tasks such as vector quantization and Viterbi operations. The datapath contains two multiply-accumulate units and one ALU. The external memory bandwidth is kept to two data buses and two corresponding address buses. Still, the internal bus network is designed such that all three units are operating in parallel. This parallelism is reflected in the performance benchmarks. For example, an FIR filter of N taps will take N/2 instruction cycles compared to N for a general purpose 16-bit DSP, and it requires only half the number of memory accesses of a general purpose DSP.

Activity measures for fast relative power estimation directed numerical transformation for low power DSP synthesis

In this paper, we propose a method for optimizing digital signal processing (DSP) systems for both power and circuit area. The optimization involves application of numerical transformations to the matrices of a linear system. A greedy search algorithm is used, along with fast and efficient activity estimator to synthesize low power systems. The method is applicable to bit-serial, nibble-serial as well as fully word-parallel architectures. In this paper we focus primarily on bit-serial architectures and show that up to 35 percent savings in power and hardware may be obtained.

KISS-16V2: a one-chip ASIC DSP solution for GSM

Outlines the requirements for the various digital signal processing functions of the pan-European digital mobile cellular telephone system in terms of computational power and RAM and ROM capacities, and describes a digital signal processor (DSP) solution which is able to integrate all of these digital baseband functions for a hand-held terminal onto one VLSI chip. The KISS-16V2 processor, a low-power CMOS 16-b DSP, is optimized for digital telecommunications, especially for Groupe Speciale Mobile (GSM). A power-down mode together with the capability of memory and multiplier standby operation make this DSP well suited for handheld devices. A design strategy based on the extensive use of cell compilers and synthesis tools reduces the design of further DSP derivations to a minimum. >

Novel dynamic merged load technology

Two new device concepts for dynamic ratioless inverter logic circuits are presented. Very high circuit density is achieved by replacing the traditional MOS dynamic load transistor with a novel load element which is merged with the switching transistor. Both device types can be implemented with a relatively standard double polysilicon CMOS process and are ideally suited for very low-power digital signal processors, serial memories and correlators, and digital image processors.