Abstract
In this paper, we propose a method for optimizing digital signal processing (DSP) systems for both power and circuit area. The optimization involves application of numerical transformations to the matrices of a linear system. A greedy search algorithm is used, along with fast and efficient activity estimator to synthesize low power systems. The method is applicable to bit-serial, nibble-serial as well as fully word-parallel architectures. In this paper we focus primarily on bit-serial architectures and show that up to 35 percent savings in power and hardware may be obtained.
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