Low-power Design Research Articles

Design of Low Power Thinned Smart Antenna for 6G Sky Connection

To improve radio access capability, sky connections relying on satellites or unmanned aerial vehicles (UAV), as well as high-altitude platforms (HAP) will be exploited in 6G wireless communication systems, complementing terrestrial networks. For long-distance communication, a large smart antenna will be used that is characterized by high amounts of power consumed by digital beamformers. This paper focuses on reducing power consumption by relying on a thinned smart antenna (TSA). The performance of TSA is investigated in the sub-6 GHz band. The differential evolution (DE) algorithm is used to optimize excitation weights of the individual dipoles in the antenna array and these excitation weights are then used in TSA for beamforming, with signal processing algorithms deployed. The DE technique is used with the least mean square, recursive least square and sample matrix inversion algorithms. The proposed method offers almost the same directivity, simultaneously ensuring lower side lobes (SLL) and reduced power consumption. For a TSA of 20, 31, and 64 dipoles, the power savings are 20%, 19.4%, and 17.2%, respectively. SLL reductions achieved, in turn, vary from 5.2 dB to 8.1 dB.

Comparison between Power Dissipation and Propagation Delay on 6T SRAM Cell Design Using GDI Logic with Transmission Gate VMSA and Voltage Divider

The rapid evolution of the semiconductor industry has witnessed shrinking portable and mobile devices alongside an increasing demand for extended battery life. Addressing the critical challenges of speed and battery life in digital devices, this paper investigated the effectiveness of innovative low-power design techniques. Focusing on the Gate Diffusion Input (GDI) approach, a recent advancement in the field, a comprehensive analysis revealed its significant potential for reducing power consumption in digital circuits. Additionally, a comparative analysis was conducted to evaluate the performance of conventional 6T GDI SRAM cells and their Modified 6T GDI SRAM with Voltage Divider, considering the influence of Sense Amplifiers. Simulation data demonstrated that Modified 6T SRAM designs, particularly the Voltage Divider and TGVMSA variants, achieved significantly lower power dissipation and delay despite having a larger cell area. Remarkably, the proposed design substantially improved power dissipation and propagation delay, achieving 1.3 ps, and 889.41mV at 1.8V shows that the suggested design enhances power dissipation and propagation delay. These findings suggest that the proposed design offers a promising strategy for enhancing power efficiency and performance in digital devices, thereby mitigating the limitations of battery life and speed in the modern technological landscape.

ISLPED 2023: International Symposium on Low-Power Electronics and Design

ISLPED 2023: International Symposium on Low-Power Electronics and Design

Advancements In Low-Power Technologies: Clock-Gated Circuits and Beyond

With the continuous advancement of the integrated circuit industry, there has been a steady rise in the level of integration and circuit scale. This inevitably leads to an escalation in power consumption by electronic devices, underscoring the growing significance of low-power technology. This comprehensive review initiates by elucidating the fundamental concept of low power, followed by an exploration of optimization measures utilizing clock-gated circuits as a prime example. Subsequently, it outlines the current challenges and prospects associated with low-power technologies. The core focus of this review revolves around the utilization of clock tree structures and triggers, which constitute the primary contributors to dynamic power consumption. These methodologies are presently the most prevalent and efficacious means to curtail power consumption through clock gating. The methodologies expounded in this review adeptly fulfill the objective of power reduction, ensuring that both present and future integrated circuits remain highly efficient. Thus, underscoring the critical role of low-power design in the realm of integrated circuit design.

Analysis of a Low-Power OTA-Based Neural Amplifier Design for EEG Signal Acquisition

This paper presents the design of an efficient operational transconductance amplifier (OTA) to be explicitly used for electroencephalogram (EEG) signal acquisition in neural amplifiers (NAs). The central objective of this study revolves around addressing the fundamental compromise between noise and power in the design of NAs. The overarching goal is to effectively mitigate this trade-off by introducing novel approaches. The proposed design’s novelty lies in utilizing an adaptive biasing technique instead of the traditional current mirror biasing technique. Furthermore, the conventional input differential pair of the OTA is modified to employ a self cascode flipped voltage follower (SCFVF), which eventually reduces power consumption of the NA to 0.822 [Formula: see text]W. Additionally, notable improvements in noise performance are achieved and found to be 624.9 nV/[Formula: see text] at 1 Hz. The gain and bandwidth range of the input low-noise amplifier is 54.2 dB and 2.8 Hz–207 Hz, respectively, which effectively amplifies low-amplitude noisy incoming signals, addressing the specific requirements of EEG signal acquisition.

Design and Analysis of Ultra-low Power Voltage Controlled Oscillator in Nanoscale Technologies

In latest wired and wireless communication equipment, VCO (voltage-controlled oscillator) is the major building block and particularly used as the stable high frequency clock generator. VCO performance is measured through frequency range, power supply used, area occupied, power consumption, delay, and phase noise. VCO is the cascaded of odd number of inverter stages in a ring format, hence it is also articulated as a ring oscillator. Today’s portable communication devices are battery operated. Hence, low power and area efficient designs play a key role in battery life enhancement and device size reduction. Device scaling improves the effective silicon area utilization, but it leads to more leakages. Therefore, low power techniques along with the technology scaling is the best way of low power designs. In this article, discussed various low power schemes. The ring oscillator designs are carried out in various nano meter scaled technologies such as 180nm, 90nm,65nm and 45nm. A 5-stage ring oscillator is implemented in each technology along with low power schemes, simulated in Cadence virtuoso, and noted power, delay, and area. Observed that the proposed ring oscillator with sleepy keeper technique generated a stable frequency of oscillations in the range of 1GHz-2GHz. A control voltage of 1.8V to 0.4V is applied and targeted the power less than 30mW and delay in 0.25p sec.

Design and Implementation of Low Power, Area Crosstalk Reduction Using Static Timing Analysis

Design and Implementation of Low Power, Area Crosstalk Reduction Using Static Timing Analysis

Sustainability by Efficiency: Energy Considerations in IoT Device Development

The widespread use of Internet of Things (IoT) devices has brought about an unparalleled level of connectedness, revolutionizing several sectors and everyday existence. However, there are serious worries over the energy usage and environmental effect of these devices due to their increasing deployment. The urgent problem of improving energy efficiency in Internet of Things devices is explored in this study abstract. Acknowledging the complex issues, we examine the condition of IoT device architecture at the moment, focusing on elements that lead to excessive energy usage. We examine cutting-edge techniques via an extensive examination, such as advanced computing paradigms like edge and fog computing, low-power hardware design, and energy-efficient communication protocols. The study also looks at case studies and tests conducted in the real world, providing concrete proof of the efficacy of various energy-saving strategies. Even with significant progress, issues with security, privacy, and scalability still exist. We address the trade-offs between performance and energy efficiency, highlighting the necessity of standardizing solutions. Promising future prospects are outlined in our article, such as the incorporation of block chain applications, revolutionary developments in battery technology, and renewable energy sources. The purpose of this study abstract is to direct researchers, industry practitioners, and policymakers towards sustainable solutions for reducing the energy footprint of Internet of Things devices by offering a thorough view of the present scenario and forward-looking tactics.

Performance and analysis of different adder topologies

This paper gives an overview of area, power, delay for four different 64-bit adders. The design metrics in VLSI are low area and delay alongside low power designs. Adder is one of the necessary components of almost every kind of digital and high- performance systems such as FIR filters, digital signal processors and microprocessors etc. Different types of adders are carry tree adder, carry save adder, carry look ahead adder and carry select adder. In this work we have designed, simulated and synthesized these adder topologies and compared the results in cadence tool.

Capacitively Coupled Near-Threshold Biasing: Low-Power Design Based on Metal Oxide TFTs for IoT Applications

Capacitively Coupled Near-Threshold Biasing: Low-Power Design Based on Metal Oxide TFTs for IoT Applications

Low-Power Design Techniques for Internet of Things (IoT) Devices: Current Trends and Future Directions

Low-Power Design Techniques for Internet of Things (IoT) Devices: Current Trends and Future Directions

A Wireless Multimodal Physiological Monitoring ASIC for Animal Health Monitoring Injectable Devices.

Utilizing injectable devices for monitoring animal health offers several advantages over traditional wearable devices, including improved signal-to-noise ratio (SNR) and enhanced immunity to motion artifacts. We present a wireless application-specific integrated circuit (ASIC) for injectable devices. The ASIC has multiple physiological sensing modalities including body temperature monitoring, electrocardiography (ECG), and photoplethysmography (PPG). The ASIC fabricated using the CMOS 180 nm process is sized to fit into an injectable microchip implant. The ASIC features a low-power design, drawing an average DC power of 155.3 µW, enabling the ASIC to be wirelessly powered through an inductive link. To capture the ECG signal, we designed the ECG analog frontend (AFE) with 0.3 Hz low cut-off frequency and 45-79 dB adjustable midband gain. To measure PPG, we employ an energy-efficient and safe switched-capacitor-based (SC) light emitting diode (LED) driver to illuminate an LED with milliampere-level current pulses. A SC integrator-based AFE converts the current of photodiode with a programmable transimpedance gain. A resistor-based Wheatstone Bridge (WhB) temperature sensor followed by an instrumentation amplifier (IA) provides 27-47 °C sensing range with 0.02 °C inaccuracy. Recorded physiological signals are sequentially sampled and quantized by a 10-bit analog-to-digital converter (ADC) with the successive approximation register (SAR) architecture. The SAR ADC features an energy-efficient switching scheme and achieves a 57.5 dB signal-to-noise-and-distortion ratio (SNDR) within 1 kHz bandwidth. Then, a back data telemetry transmits the baseband data via a backscatter scheme with intermediate-frequency assistance. The ASIC's overall functionality and performance has been evaluated through an invivo experiment.

Design of Low Power SAR ADC with Novel Regenerative Comparator

This paper introduces two low-power design techniques for a successive approximation register (SAR) analog-to-digital converter (ADC) used in transmitting physiological signals. The first technique is called dual split switching, involving the use of a one-sided charge-scaling digital-to-analog converter (DAC) to minimize switching energy by reducing leakage in a dual transmission gate. The second technique, known as the set and reset phase, determines the amplification and comparison phases of the comparator. This approach reduces the delay time of the comparator through the use of a folded cascode pre-amplifier and a regenerative latch. The design includes a Serial-in-Parallel-Out (SIPO) N-bit register and SAR, implemented using negative edge-triggered D flip-flops (DFFs). To optimize power consumption, the supply voltage of the SAR ADC is set to 500 mV. The concept of a variable threshold is utilized throughout the design to enable operation with this lower supply voltage. The SAR ADC is designed to support a sampling rate of up to 1 Msps (mega-samples per second). The circuit is implemented using standard UMC180nm technology. According to the test results, the power consumption of the SAR ADC is only 29.06 uW, and the achieved sampling rate is 5 Ksps (kilo-samples per second). The maximum differential non-linearity (DNL) is measured to be +0.9/−0.82 least significant bits (LSBs).

Source of IC power consumption and low power design

In these years, with the continuous development of 14nm and 7nm chip processes and the increasing popularity of computers, cell phones, and smart homes, the growing market of electronic products and ultra-fine research for the reliability of the chip requirements gradually increased. The method of reducing power consumption in the new context of new technology is called the chip field die-cut concern. This paper mainly summarizes two aspects of power consumption sources and methods to reduce power consumption, to provide a reference basis for future research directions: First, the major sources of power consumption are static power consumption and dynamic power consumption. The primary sources of static power consumption are sub-threshold leakage and gate leakage current. This paper also mentions some other leakage currents, such as reverse bias PN junction current and induced leakage current, which can be more carefully considered when exploring methods to reduce power consumption. A more comprehensive consideration when exploring ways to reduce power consumption. Dynamic power consumption is mainly divided into Switching power and Internal power and short-circuit power. Then we summarize the existing methods which can reduce power consumption: Clock gating (including Clock gating without a latch and Clock gating with a latch), Dynamic voltage and frequency scaling, multi-supply and multi-voltage technology, Power gating and multi-threshold voltage. These methods are from a proprietary perspective to reduce power consumption.

Preface

The purpose of the three-day 2023 3rd International Conference on Electronic Communication, Computer Science and Technology (ECCST 2023), held via hybrid form on September 15th to 17th, 2023 in Shanghai, China, was to create a timely forum for multi-disciplinary discussions related to the recent developments on electronic communication, computer science and technology.As usual, the program of the meeting mainly consisted of keynote speeches, oral presentations and poster presentations, with the former including speeches delivered by six sophisticated professors from different countries and regions. The keynote speeches covered six main topics, including the one Network AI: Enabling 6G Pervasive Intelligence given by Prof. Yang Yang (The Hong Kong University of Science and Technology (Guangzhou), China). In this presentation, he first coined the concept of Service Requirement Zone (SRZ) on the user side to characterize and visualize the integrated service requirements and preferences of specific tasks of individual users. Then, he proposed a network Artificial Intelligence (AI) architecture with integrated network resources and pervasive AI capabilities for supporting customized services with guaranteed QoEs. Finally, extensive simulations show that the proposed network AI architecture can consistently offer a higher USR performance than the cloud AI and edge AI architectures with respect to different task scheduling algorithms, random service requirements, and dynamic network conditions.In the framework of experimental and theoretical approaches, the Conference gathered about 80 delegates from all over the world and addressed a number of highly relevant aspects of electronic communication, computer science and technology. Covering Nonlinear Circuits and Systems, Low Power Design and VLSI Physical Design, Electromagnetic Compatibility, Computer and Data Communication, Computer Programming, etc., the selected contributions of this special issue provide guidance for future interdisciplinary developments. In this way, the multi-scale aspects of electronic communication, computer science and technology should be considered.We received various manuscripts of invited papers and contributions presented at the Conference. All of these have been peer reviewed and are collected in this volume. We would like to thank all the anonymous colleagues who have acted as referees to assess the suitability of the various articles for publication in Journal of Physics: Conference Series. We are confident that the high quality of both invited and contributed papers contained in this Proceedings will be appreciated by electronic and computer communities.We would like to express our thanks to all the authors for their time and genuine efforts, and to the reviewers for their fruitful comments during the preparation of this volume. We also acknowledge the support provided in various ways by Shanghai Pudong New Area Association For Computer and Donghua University.The Committee of ECCST 2023List of Committee Member is available in this Pdf.

A low-power anti-interference parallel downlink communication system design

The Internet of Things (IoT) has seen rapid advancements and widespread deployment of wireless devices recently. To pursue the long-term deployment goal of the Internet of Things, a lot of work in recent years has focused on low-power devices, such as backscatter systems. However, they face two key challenges, unequal uplink and downlink communication range, and weak end devices’ inability to handle downlink conflicts and networking. In this paper, we propose a µW-level downlink receiving system, which enhances the anti-interference and anti-conflict capabilities of low-power end devices. We also present a state machine model for networking capabilities. We implemented the prototype system using discrete components and FPGA and conducted experiments. The result shows that our system achieves a downlink communication range of over 250m at a 1kbps data rate with 1% BER and increased by more than 10 times compared to conventional backscatter receivers. The power consumption is 73.6 µW.

Fabrication of YSZ ceramic thin films with sol-gel method for mixed potential-type zirconia-based NO2 sensor

In this work, yttria-stabilized zirconia (YSZ) thin films were prepared by sol-gel and spin-coating methods, which are simple and inexpensive, with good film quality and excellent electrical conductivity. Using this film, a YSZ film mixed-potential type NO2 gas sensor with NiO as the sensitive electrode material was fabricated. The films had the best dielectric properties when spin-coated four times, and the sensors had the highest response (48 mV–100 ppm NO2) as well as the best sensitivity (14.8 mV/decade for 5–20 ppm NO2 and 42 mV/decade for 20–500 ppm NO2). The YSZ thin-film gas sensor operates at a lower temperature, with an optimum operating temperature of 550 °C, and the power consumption of the sensor has been reduced by approximately 46 % or more compared to conventional bulk YSZ NO2 gas sensors. This provides a very effective direction for the low-power design of high-temperature devices such as the YSZ gas sensor. In addition, thin-film devices are more conducive to integrating sensors into microelectronic circuits, greatly improving the application scenarios for such devices. This sensor has excellent repeatability, very good selectivity, and outstanding long-term stability over 30 days of continuous measurement. In conclusion, based on the excellent sensing performance and low power consumption of the YSZ thin-film gas sensor, the sensor has a promising future for in-situ monitoring of NOx.

Review on Reversible Logic Gates

Abstract: Reversible logic gates have emerged as a pivotal area of research in the field of digital circuit design, offering the promise of ultra-low power consumption. This survey paper comprehensively explores the foundations and practical applications of reversible logic gates. Beginning with an introduction to the fundamental principles of reversibility, it delves into the design of reversible gates, covering CNOT, Feynman, Toffoli, Peres, Fredkin gates, and beyond. The paper offers a systematic review of state-of-the-art research in the field, discussing various optimization techniques and quantum-inspired reversible circuits. It also investigates real-world applications, ranging from low-power VLSI design to quantum computing. By summarizing the key findings, challenges, and potential future directions in reversible logic gate design, this survey paper provides a valuable resource for researchers, engineers, and enthusiasts seeking a comprehensive understanding of this transformative technology

Design Guidelines for Low Power Embedded Systems using Low Power Electronics

The design of Low Power Embedded Systems (LPES) and IoT products may include a variety of power management techniques, or they may incorporate sophisticated on-chip capabilities that assist in reduced power usage. The power management and low power consumption of embedded systems are also enabled by complex algorithms, and every Low Power System (LPS) may require a mix of approaches to avoid using extra battery power. There are several strategies we may use when creating an LPES that must be extremely power efficient while simultaneously offering the necessary degree of computational capability. It all depends on the design specifications that must be met. Then, if at all feasible, choose the appropriate low-power components from Low Power Electronics (LPE). After studying and reviewing multiple LPES real-time projects, we compiled a list of a few strategies we may use to approach low-power design and consumption for embedded systems. Following the analysis of numerous LPES real-time projects, we came up with a list of a few approaches to low-power design for embedded systems using LPE. There are additional benefits of LPES design. Less heat is generated through LPES, which is better for the environment. For 1000 LPES devices, one watt of power saved per device equals one KWH i.e. we can save 1 unit of electricity. Design with low power increases the component and system reliability. The embedded system's operating life is enhanced. In many instances, LPES designs may result in a reduction in production costs. The LPE components chosen are more affordable and inexpensive. Hence, the low-wattage power supply, LPES design is easier and less expensive.

A Low Threshold Voltage Ultradynamic Voltage Scaling SRAM Write Assist Technique for High-Speed Applications

With the percentage of embedded SRAM increasing in SoC chips, low-power design such as the near-threshold SRAM technique are getting increasing attention to reduce the entire chip energy consumption. However, the descending operating voltage will lead to longer write latency and a higher failure rate. In this paper, we present a novel low Vth ultradynamic voltage scaling (UDVS) 9T subthreshold SRAM cell to improve the write ability of SRAM cells. The proposed Low Vth UDVS SRAM cell is demonstrated with a low threshold voltage speed-up transistor and an ultradynamic voltage scaling circuit implemented in 16 nm low-leakage CMOS technology. This wide supply range was made possible by a combination of circuits optimized for both subthreshold and abovethreshold regimes. This write assist technique can be operated selectively to provide write capability at very low voltage levels while avoiding excessive power overhead. The simulation findings reveal that with 16 nm technology, the write ability is improved by 33% over the normal case at 0.9 V supply voltage.