Low-power Complementary Metal Oxide Research Articles

A Rail-To-Rail and Low Offset Novel Strongarm Comparator Circuit for Low Power Data Converter Architectures

With the rapid improvements in the design of advanced high performance communication receivers, hand-held electronic devices are in widespread usage for some time. These devices facilitate high speed and secured access to internet data. The demand for realizing a smart and better usage experience puts forth strict requirements on the design aspects of next-generation high speed low power complementary metal oxide semiconductor (CMOS) receiver design. One of the major modules in the implementation of high speed low power CMOS receiver device is the analog to digital converter (ADC) architecture. In the process of conversion from analog to digital signals, Quantization and sampling operations are vital and are realized using comparator circuits. The comparator design has a significant role in the design of data converter architecture. Several comparator architectures exist, but StrongARM topology is discussed and implemented in this work due to its negligible static power dissipation and rail to rail output voltages. The proposed novel comparator architecture is designed and simulated in 90nm CMOS process using Cadence Virtuoso tool and operated at supply voltage of VDD=1.5V, a clock frequency of 250MHz. Compared to the previous designs, the energy delay product was reduced by 8% which is an important observation to be observed for use in wireless sensor node applications.

Impact of temperature on radio frequency/linearity and harmonic distortion characteristics of Ge multi‐channel fin shaped field‐effect transistor

This dissertation demonstrates the reliability issues associated with the temperature of Ge multi-channel fin shaped field-effect transistor (Mch-FinFET). Temperature dependence on short channel effectss such as threshold voltage (Vth), sub-threshold swing (SS), and switching ratio are observed. The variation in temperature on various important radio frequency (RE)/analog, linearity, and harmonic distortion characteristics are studied and analyzed over a wide range of temperatures (300–500 K). The simulation study revealed that Mch-FinFET devices exhibit 61.6% improvement in ION with minimum SS value. The improvement of SS, switching ratio and Vth can be observed with temperature fall. The enhancement in performance of various RF/analog attributes such transconductance, device efficiency, transconductance frequency product, gain frequency product, cut-off frequency, and intrinsic gain with lowering of temperature. However, Mch-FinFET device provides a significant improvement of higher-order current and voltage intercept points such as IIP3, VIP2, VIP3, and 1 dB compression point with lesser harmonic distortion such as HD2, HD3, and THD at elevated temperature. The superior efficiency of DC and RF/analog attributes, greater linearity, and minor harmonic distortion performance of Mch-FinFET make it more considerable to design low power Complementary metal–oxide–semiconductor (CMOS) circuits.

Optimized Design of Low Power Complementary Metal Oxide Semiconductor Low Noise Amplifier for Zigbee Application

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.

A Low Power High Gain CMOS LNA with Multiple-Feedback Network for Low Voltage UWB Receiver

In this paper, a high gain low voltage low power Complementary Metal Oxide Semiconductor (CMOS) Low-noise Amplifier (LNA) using Chartered 0.18[Formula: see text][Formula: see text]m CMOS process for Ultra-wideband (UWB) receiver applications is presented. A novel multiple-feedback network constructed by the shunt feedback resistor with a transformer is adopted to realize desirable bandwidth extension and less chip area occupation in the common-source stage. All the cascaded transistors are configured by current-reuse structure and adjusted by forward body bias technique to further reduce supply voltage and power dissipation. The post-layout simulation results demonstrate that the proposed 3.4–10.1[Formula: see text]GHz UWB LNA accomplishes a maximum gain of 14.26[Formula: see text]dB with only 2.33[Formula: see text]mW power consumption at 0.8[Formula: see text]V supply voltage, while Noise Figure (NF) is 1.49–3.41[Formula: see text]dB and the chip area is 0.46[Formula: see text]mm2 including test pads (core area is 0.23[Formula: see text]mm2).

Low power consumption high speed CMOS dual-modulus 15/16 prescaler for optical and wireless communications

Frequency synthesizer is an important part of optical and wireless communication system. Low power comsumption prescaler is one of the most critical unit of frequency synthesizer. For the frequency divider, it must be programmable for channel selection in multi-channel communication systems. A dual-modulus prescaler (DMP) is needed to provide variable division ratios. DMP is considered as a critical power dissipative block since it always operates at full speed. This paper introduces a high speed and low power complementary metal oxide semiconductor (CMOS) 15/16 DMP based on true single-phase-clock (TSPC) and transmission gates (TGs) cell. A conventional TSPC is optimized in terms of devices size, and it is resimulated. The TSPC is used in the synchronous and asynchronous counter. TGs are used in the control logic. The DMP circuit is implemented in 0.18 μm CMOS process. The simulation results are provided. The results show wide operating frequency range from 7.143 MHz to 4.76 GHz and it comsumes 3.625 mW under 1.8 V power supply voltage at 4.76 GHz.

Shallow trench isolation stress modification by optimal shallow trench isolation process for sub-65-nm low power complementary metal oxide semiconductor technology

Shallow trench isolation (STI) induced mechanical stress affects the device behavior in the advanced complementary metal oxide semiconductor (CMOS) technology. This article presents how to use an optimal STI process to reduce transistor mismatch and leakage current induced standby current in static random access memory (SRAM). The STI induced mechanical stress affects the device behavior in the advanced CMOS technology. The optimized STI process can reduce junction and bulk leakage that occurs on the STI sidewall due to STI compressive stress enhancing boron diffusion and increasing junction electric field of STI sidewall resulting in band-to-band-tunneling (BTBT) degradation. An obvious decrease in BTBT occurs on STI edge sidewall that is observed by using the optimized STI process. Meanwhile, the optimized STI process has better length of diffusion effect. Moreover, the optimized STI process can improve the parasitic device at STI edge because of smaller divot. Since random fluctuation of channel dopant and process induced device mismatch are major considerations in SRAM cell, we examine STI sidewall boron dopant diffusion effect on SRAM due to BTBT increasing exponentially with increasing doping concentration in the P-well of negative metal oxide semiconductor field effect transistor. The mismatch of passing gate of SRAM and Vcc_min can also be improved by leakage reduction from the optimized STI process due to improved random dopant fluctuation.

Improved Poly Gate Engineering for 65 nm Low Power CMOS Technology

A design for the polycrystalline gate is developed for low power complementary metal oxide semiconductor (CMOS) technology. Using the poly deposition, a less poly depletion effect and a decrease in the electrical gate dielectric thickness can be obtained. Also, the poly deposition successfully reduces the roughness of the poly surface and produces a smaller poly grain size after subsequent rapid thermal processing steps. Meanwhile, the poly deposition can suppress the short channel effect and can reduce off-state leakage current. The poly deposition results in better voltage ramp dielectric breakdown and uniformity on a specific test vehicle. The asymmetry characteristics of the device are also improved by the poly deposition. The of the cell size 6T-static random access memory using the poly deposition is also improved due to leakage current reduction and well asymmetry.

The BRITE space telescope: Using a nanosatellite constellation to measure stellar variability in the most luminous stars

The BRIght Target Explorer (BRITE)-Constellation is a group of Canadian/Austrian nanosatellites that will examine the apparently brightest stars in the sky for variability using precise differential photometry. The constellation consists of four low Earth-orbiting nanosatellites, divided into pairs, with each member of a pair having a different optical filter. Each BRITE satellite will observe a region of interest for up to 100 days or longer, allowing the measurement of stellar oscillations on the order of hours to months. Each BRITE satellite utilizes a number of new, innovative technologies including reaction wheels, star tracker and optical telescope, all sized and designed around space flight laboratory's 5-kg, 20 × 20 × 20 cm 3 CanX nanosatellite bus. The BRITE science instrument is a low power complementary metal oxide semiconductor (CMOS) detector coupled with a custom lens system designed to provide a telecentric, slightly defocused image optimized for observing stellar intensity with an accuracy of 1 mmag per data point per orbit down to a visual magnitude of + 3.5 . Photometric measurements will have an error amplitude spectrum no greater than 20 ppm over measurement periods longer than a month. The optics will have a small (30 mm) aperture and a maximum length of 100 mm in order to fit within the nanosatellite bus.

Effect of the forward biasing the source-substrate junction in n-metal–oxide–semiconductor transistors for possible low power complementary metal–oxide–semiconductor integrated circuits’ applications

The use of forward biasing the source-substrate junction in metal–oxide–semiconductor transistors, to reduce its threshold voltage is a simple method to realize low power complementary metal–oxide–semiconductor integrated circuits. A 2 μm long n-metal–oxide–semiconductor field effect transistor was used as the device under test. The threshold voltage was measured in the temperature range of 300–77 K, using two different methods. The classic long channel threshold voltage model was fitted by optimization to the experimental data of the reverse-biased substrate, and the model with the fitted parameters was used to calculate the threshold voltage under forward-biased substrate conditions. The agreement between the fitted and extrapolated threshold voltage with the experimental values demonstrated the validity of this classic model for a substrate forward bias up to 0.5 V, and for a wide temperature range.

Digital GaAs Autocorrelator Developed for Space Borne Submillimeter Astronomy

We present the development of a correlator module intended for space borne high resolution heterodyne spectroscopy. Our attention has been focused on power consumption reduction (few mW per channel needed), while looking for a high clock frequency (few hundreds of MHz) to cover wide bandwidths. The module proposed, which may be the base of an hybrid analog/digital spectrometer, is composed of two full custom Very Low Scale Integration (VLSI) circuits using two different technologies: a high speed MEtal Semiconductor Field Effect Transistor (MESFET) on Gallium Arsenide substrate (GaAs) and a low power Complementary Metal Oxide Semiconductor (CMOS) on Silicon substrate (Si). A 0.8 μm GaAs prototype circuit has been built and tested. It shows a correct global operation up to 242 MHz – and for marginal functions up to 611 MHz –, and a power consumption as expected by the simulations (less than 2 W). Expected improvements of the technology, together with some modifications developed here, demonstrate that a high frequency correlator module, meeting spatial requirements (many hundreds of channels and few mW per resolution point), should be feasible.