Low-power Complementary Metal Oxide Semiconductor Research Articles

Ultra-low-power CMOS ring oscillator with minimum power consumption of 2.9 pW using low-voltage biasing technique

Abstract The need for low-power low-voltage circuit so lutions increases significantly with the rapid spread of wireless sensor network (WSN) and energy harvesting applications. The design of Complementary Metal-Oxide Semiconductor (CMOS) oscillators in sub-threshold region is challenged by the limits of the minimum start-up sup ply voltage, the power available from the harvester, die area, the demand of fully integrated CMOS circuits, and the additional auxiliary circuits that are needed to stabilize the frequency vs a supply voltage V DD. In this work, low-power CMOS oscillator with a simplified design is proposed in order to overcome the aforementioned obstacles. The circuit is designed using 2.5 µm 2-polySi 2-metal CMOS technology from IMB–CNM (CSIC) [1] with a threshold voltage of n-channel metal oxide semiconductor NMOS and p-channel metal oxide semiconductor PMOS transistors of 0.86 and −1.52 V, respectively. The suggested oscillator is capable to start up even in the deep sub-threshold region at V DD of 0.25 V. Accordingly, the minimum power consumption is 2.9 pW with an oscillation frequency of 2 Hz. The circuit can produce a P–P voltage of the oscillation signal equal to the supply voltage within a power supply range of 0.25–1.25 V.

A Rail-To-Rail and Low Offset Novel Strongarm Comparator Circuit for Low Power Data Converter Architectures

With the rapid improvements in the design of advanced high performance communication receivers, hand-held electronic devices are in widespread usage for some time. These devices facilitate high speed and secured access to internet data. The demand for realizing a smart and better usage experience puts forth strict requirements on the design aspects of next-generation high speed low power complementary metal oxide semiconductor (CMOS) receiver design. One of the major modules in the implementation of high speed low power CMOS receiver device is the analog to digital converter (ADC) architecture. In the process of conversion from analog to digital signals, Quantization and sampling operations are vital and are realized using comparator circuits. The comparator design has a significant role in the design of data converter architecture. Several comparator architectures exist, but StrongARM topology is discussed and implemented in this work due to its negligible static power dissipation and rail to rail output voltages. The proposed novel comparator architecture is designed and simulated in 90nm CMOS process using Cadence Virtuoso tool and operated at supply voltage of VDD=1.5V, a clock frequency of 250MHz. Compared to the previous designs, the energy delay product was reduced by 8% which is an important observation to be observed for use in wireless sensor node applications.

Passive frustrated nanomagnet reservoir computing

Reservoir computing (RC) has received recent interest because reservoir weights do not need to be trained, enabling extremely low-resource consumption implementations, which could have a transformative impact on edge computing and in-situ learning where resources are severely constrained. Ideally, a natural hardware reservoir should be passive, minimal, expressive, and feasible; to date, proposed hardware reservoirs have had difficulty meeting all of these criteria. We, therefore, propose a reservoir that meets all of these criteria by leveraging the passive interactions of dipole-coupled, frustrated nanomagnets. The frustration significantly increases the number of stable reservoir states, enriching reservoir dynamics, and as such these frustrated nanomagnets fulfill all of the criteria for a natural hardware reservoir. We likewise propose a complete frustrated nanomagnet reservoir computing (NMRC) system with low-power complementary metal-oxide semiconductor (CMOS) circuitry to interface with the reservoir, and initial experimental results demonstrate the reservoir’s feasibility. The reservoir is verified with micromagnetic simulations on three separate tasks demonstrating expressivity. The proposed system is compared with a CMOS echo state network (ESN), demonstrating an overall resource decrease by a factor of over 10,000,000, demonstrating that because NMRC is naturally passive and minimal it has the potential to be extremely resource efficient.

Low Leakage CMOS Design Technique with Stable State Retention

In this research, a new hybrid design technique for low-power complementary metal–oxide semiconductor (CMOS) circuits is proposed which utilizes the advantages of multiple design methodologies such as sleep-transistors, forced-stack, and variable-threshold CMOS (VTCMOS), and is integrated with a buffer circuit. Based on the proposed technique, the CMOS inverter and two-input NAND circuits are simulated in LTspice software using 16 nm high-performance (HP) and low-power (LP) predictive technology models (PTM). Upon comparison with available leakage reduction techniques, the proposed approach demonstrates considerably low power, delay and power delay product (PDP) while maintaining output-logic integrity. The impact of the process parameter, voltage, and temperature (PVT) variations are observed through Monte Carlo simulations, which depict that the proposed model provides uniform sensitivity in terms of the performance metrics within ±3σ statistical variations from the mean. The circuit area of the proposed technique is also estimated and compared with existing methods using the Cadence Virtuoso platform.

Design of K-Band Power Amplifier with 180-Degree Phase- Shift Function Using Low-Power CMOS Process

In this study, a K-band complementary metal oxide semiconductor (CMOS) power amplifier was designed using a low-power (LP) process to improve the integration of the beamforming system. In order to reduce the overall system size, a 180° phase-shift function was mounted. It was designed in a four-stage structure to secure sufficient gain. In addition, we propose a way to secure wideband characteristics by utilizing the gains of each of the four stages. The power amplifier was designed with a 40-nm LP CMOS process to verify the feasibility of the proposed technique. The measured P1dB for 0° and 180° phase-shift modes were 15.25 dBm and 14.30 dBm, respectively, at the operating frequency of 25.0 GHz. The measured phase difference between the two modes was 217° at the 25.0 GHz.

Highly Miniaturized, Low-Power CMOS ASIC Chip for Long-Term Continuous Glucose Monitoring.

The objective of this work is to develop a highly miniaturized, low-power, biosensing platform for continuous glucose monitoring (CGM). This platform is based on an application-specific integrated circuit (ASIC) chip that interfaces with an amperometric glucose-sensing element. To reduce both size and power requirements, this custom ASIC chip was implemented using 65-nm complementary metal oxide semiconductor (CMOS) technology node. Interfacing this chip to a frequency-counting microprocessor with storage capabilities, a miniaturized transcutaneous CGM system can be constructed for small laboratory animals, with long battery life. A 0.45 mm × 1.12 mm custom ASIC chip was first designed and implemented using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS technology node. This ASIC chip was then interfaced with a multi-layer amperometric glucose-sensing element and a frequency-counting microprocessor with storage capabilities. Variation in glucose levels generates a linear increase in frequency response of this ASIC chip. In vivo experiments were conducted in healthy Sprague Dawley rats. This highly miniaturized, 65-nm custom ASIC chip has an overall power consumption of circa 36 µW. In vitro testing shows that this ASIC chip produces a linear (R2 = 99.5) frequency response to varying glucose levels (from 2 to 25 mM), with a sensitivity of 1278 Hz/mM. In vivo testing in unrestrained healthy rats demonstrated long-term CGM (six days/per charge) with rapid glucose response to glycemic variations induced by isoflurane anesthesia and tail vein injection. The miniature footprint of the biosensor platform, together with its low-power consumption, renders this CMOS ASIC chip a versatile platform for a variety of highly miniaturized devices, intended to improve the quality of life of patients with type 1 and type 2 diabetes.

(Invited) Achieving Lower Power Logic Using P-Type Metal Oxide Thin Film Transistors

Thin film transistors (TFTs) have enabled the active matrix displays that are a ubiquitous part of everyday life, from mobile phones and tablets through to desktop monitors and home televisions. They are used in the circuit at each pixel over the display as they can be fabricated for relatively low cost with excellent uniformity at low temperatures over large areas on glass substrates. These pixel circuits only require either n-channel or p-channel enhancement mode TFTs. However, there has long been a desire to integrate the display driver electronics onto the display panel as an alternative to connecting silicon-based integrated circuits using complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) to displays. More recently, there has been an increasing interest in producing other logic circuits using TFTs on glass and plastic substrates as this could enable a new generation of products with embedded electronics. However, both of these applications need low power logic circuits. CMOS is an inherently low power technology, but it requires both n-channel and p-channel transistors. Whilst this can be realised in silicon CMOS FETs, it has not yet been achieved using TFTs because it has proved difficult to realise both n-channel and p-channel devices using one material system at low cost. For example, hydrogenated amorphous silicon can be used to make reasonable n-type material but not p-type.Thin film oxide semiconductors such as amorphous indium gallium zinc oxide have been successfully commercialised in the pixel circuits of active matrix displays as they possess high field effect mobility, low threshold voltage, low off-state current and a high switching ratio. There is therefore a lot of interest in finding a suitable complementary p-type metal oxide thin film material to allow CMOS-type logic to be realised using this material system.Cuprous oxide is one such promising candidate material as the top of the valence band is dominated by states which form as a result of hybridisation of the completely filled Cu 3d orbitals and the O 2p orbitals. These hybridised states are less localised and have a higher dispersion with a resulting decrease in the effective mass of holes in these states and a higher carrier mobility. The results of an extensive study of this material shows that the grain structure is of critical importance with [100] oriented films resulting in a higher mobility. Furthermore, the impact of grain boundaries on conduction must be controlled. Although this allows TFTs with reasonable on-state current to be fabricated, it is found that there is a significant residual off-state current which is a result of electron accumulation in the channel. This is consistent with the high off-state current that has been observed widely in TFTs using p-type metal oxide thin film materials.The low off-state current in silicon MOSFETs means that the geometric transistor design in low power CMOS logic circuits only needs to focus on the effect of the on-state current in the p-channel and n-channel transistors. However, in TFTs, the much larger off-state current also becomes important as it can end up being a significant parameter when calculating the power consumption of CMOS logic circuits. An alternative geometric design parameter for TFT logic circuits is presented. This compares the maximum switching current with the static currents allowing optimisation based on both the noise margin and static power consumption. The result is improved performance of TFT-based CMOS logic circuits using the n- and p-type thin film oxide semiconductors that are currently available.

Optimisation of geometric aspect ratio of thin film transistors for low-cost flexible CMOS inverters and its practical implementation

A low-cost, flexible processor is essential to realise affordable flexible electronic systems and transform everyday objects into smart-objects. Thin film transistors (TFTs) based on metal-oxides (or organics) are ideal candidates as they can be manufactured at low processing temperatures and low-cost per unit area, unlike traditional silicon devices. The development of complementary metal–oxide–semiconductor (CMOS) technology based on these materials remains challenging due to differences in performance between n- and p-type TFTs. Existing geometric rules typically compensate the lower mobility of the metal-oxide p-type TFT by scaling up the width-to-length (W/L) ratio but fail to take into account the significant off-state leakage current. Here we propose the concept of an optimal geometric aspect ratio which maximises the inverter efficiency represented by the average switching current divided by the static currents. This universal method is especially useful for the design of low-power CMOS inverters based on metal-oxides, where the large off-current of the p-type TFT dominates the static power consumption of the inverter. We model the inverter efficiency and noise margins of metal-oxide CMOS inverters with different geometric aspect ratios and compare the performance to different inverter configurations. The modelling results are verified experimentally by fabricating CMOS inverter configurations consisting of n-type indium-silicon-oxide (ISO) TFTs and p-type tin monoxide (SnO) TFTs. Notably, our results show that reducing W/L of metal-oxide p-type TFTs increases the inverter efficiency while reducing the area compared to simply scaling up W/L inversely with mobility. We anticipate this work provides a straightforward method to geometrically optimise flexible CMOS inverters, which will remain relevant even as the performance of TFTs continues to evolve.

Low-voltage Low-power Bulk-driven CMOS Op-Amp Using Negative Miller Compensation for ECG

Two bulk-driven CMOS (Complementary Metal Oxide Semiconductor) operational amplifier (op-amp) designs for electrocardiogram (ECG) application are presented and compared in this paper. Both op-amps are based on two-stage amplification, where bulk-driven differential input is the first stage, while additional DC gain is the second stage. Different compensation techniques were integrated in each op-amp design. Standard Miller compensation was used for the first op-amp parallel with the second stage. The novelty of the second op-amp is that it utilizes negative Miller compensation between the bulk-driven input node and the output node of the first stag, while standard Miller compensation was used in the second stage. The purpose of this work was to compare DC gain, phase margin (PM) and unit gain frequency (UGF) obtained through different simulated compensation strategies and test results. The op-amps were simulated using 0.25 μm CMOS technology. The simulation results are presented using the standard model libraries from Tanner EDA tools, operating on a single rail +0.8V power supply.

0.4-V Bulk Driven Logarithmic Amplifier for Ultra-Low-Power Biomedical Applications

This paper presents a design and simulation of a low-noise, low-voltage, and low-power complementary metal oxide semiconductor (CMOS) logarithmic amplifier for biomedical applications like digital hearing aid applications. The amplifier block of analog front end is used as a logarithmic amplifier, based on the progressive-compression parallel-summation architecture with DC offset cancelation by adding an off-chip coupling capacitor at each stage. A fully nontailed differential limiting amplifier with bulk-driven input pair is used to achieve larger voltage gain and low voltage operation. The proposed logarithmic amplifier was designed and simulated with process parameters variation in standard 0.18-[Formula: see text]m CMOS technology. The circuit operates with a single 0.4-V power supply voltage and dissipates 0.832[Formula: see text][Formula: see text]W. The simulated input dynamic range is about 60[Formula: see text]dB, which covers the input amplitudes ranging from 1[Formula: see text][Formula: see text]V to 10[Formula: see text]mV, and the [Formula: see text]3-dB bandwidth of the amplifier is from 400[Formula: see text]Hz to 8.27[Formula: see text]kHz with simulated total input-referred noise is 0.731[Formula: see text][Formula: see text]V@8 kHz.

저전력 24-GHz CMOS 믹서 설계

This paper proposes a low-power 24-GHz CMOS down-conversion mixer for the automotive radar. This circuit operates at the operation frequency of 24 GHz, and it contains low-power circuit technique. The proposed circuit is also fabricated using 65-nm RF CMOS(radio frequeny complementary metal-oxide-semiconductor) process. The circuit is powered using a 1.2-V supply with the bias voltage of 0.8 V for the low-power technique. This circuit also has fully-differential scheme to reduce RF noise, and harmonic distortions. The proposed mixer showed lower power dissipation of 6.5 mW with a high conversion gain and very small chip area of 0.01 mm2 as compared to conventional research results.

Impact of temperature on radio frequency/linearity and harmonic distortion characteristics of Ge multi‐channel fin shaped field‐effect transistor

This dissertation demonstrates the reliability issues associated with the temperature of Ge multi-channel fin shaped field-effect transistor (Mch-FinFET). Temperature dependence on short channel effectss such as threshold voltage (Vth), sub-threshold swing (SS), and switching ratio are observed. The variation in temperature on various important radio frequency (RE)/analog, linearity, and harmonic distortion characteristics are studied and analyzed over a wide range of temperatures (300–500 K). The simulation study revealed that Mch-FinFET devices exhibit 61.6% improvement in ION with minimum SS value. The improvement of SS, switching ratio and Vth can be observed with temperature fall. The enhancement in performance of various RF/analog attributes such transconductance, device efficiency, transconductance frequency product, gain frequency product, cut-off frequency, and intrinsic gain with lowering of temperature. However, Mch-FinFET device provides a significant improvement of higher-order current and voltage intercept points such as IIP3, VIP2, VIP3, and 1 dB compression point with lesser harmonic distortion such as HD2, HD3, and THD at elevated temperature. The superior efficiency of DC and RF/analog attributes, greater linearity, and minor harmonic distortion performance of Mch-FinFET make it more considerable to design low power Complementary metal–oxide–semiconductor (CMOS) circuits.

K-Band Hetero-Stacked Differential Cascode Power Amplifier with High Psat and Efficiency in 65 nm LP CMOS Technology

A K-band complementary metal-oxide-semiconductor (CMOS) differential cascode power amplifier is designed with the thin-oxide field effect transistor (FET) common source (CS) stage and thick-oxide FET common gate (CG) stage. Use of the thick-oxide CG stage affords the high supply voltage to 3.7 V and enables the high output power. Additionally, simple analysis shows that the gain degradation due to the low cut-off frequency of the thick-oxide CG FET can be compensated by the high output resistance of the thick-oxide FET if the inter-stage node is neutralized. The measured results of the proposed power amplifier demonstrate the saturated output power of the 23.3 dBm with the 31.3% peak power added efficiency (PAE) at 24 GHz frequency. The chip is fabricated in 65-nm low power (LP) CMOS technology and the chip size including all pads is 700 μm × 630 μm.

A Low-Power CMOS Current Reference for Piezoelectric Energy Harvesters

This article proposes a nanoscale complementary metal-oxide-semiconductor (CMOS) current reference design for low power analog and digital devices. A self-biased circuit is developed within the current reference. The current reference can compensate for temperature changes and voltage fluctuations. Simulation results showed a low current around 12 nA. The design is capable of working in a broad range of power supply voltages. In the interface with 0.35 μm fabrication process, a bias voltage is generated with currents in the nanoampere range. The present current reference is qualified to be used in digital-analog circuits, such as operational amplifiers or oscillators, and is designed to be suitable for energy harvesting interfaces, because of the high efficiency and low power consumption.

On-Array Compressive Acquisition in CMOS Image Sensors Using Accumulated Spatial Gradients

A compressive acquisition technique for on-array image compression is proposed in this paper. It capitalizes on representation ability of accumulated spatial gradients of the acquired scene. The local variations inferred from strength of the accumulated gradients are used as cues to vary number of samples read through the image sensor readout. Such sampling enables the reconstruction using traditional interpolation techniques with desired quality. The proposed method is first verified using MATLAB simulations, where on an average, a compression of 87% is achieved, for a threshold of 40 intensity levels. The images are reconstructed using nearest neighbour interpolation (NNI) method which results in a mean peak signal to noise ratio (PSNR) value of 29.09 dB. The reconstructed images are further enhanced using deep convolutional neural network, which improves the PSNR to 32.46 dB. The biggest advantage of the proposed technique is low-complex hardware design. As a proof of concept, a hardware implementation of the technique is performed using discrete components. Pixel intensity values of standard images are converted into analog voltages using a data acquisition system and mapped in the input voltage range of 1.5 V −5.5 V. For a threshold of 3.8 V, the compression of 81% - 83% is observed for the considered images. The proposed technique is simple and effective, and is suitable for low-power complementary metal oxide semiconductor (CMOS) image sensors.

Novel Optimum Parity-Preserving Reversible Multiplier Circuits

Reversible logic is considered as a basic requirement for designing quantum computers. Reversible circuits do not waste energy. The use of this logic in low-power complementary metal–oxide–semiconductor circuits, quantum computing, and DNA computing has rendered reversible logic integral in today’s technology. Multiplication is regarded as a major operation in the arithmetic. Herein, four optimized parity-preserving reversible signed and unsigned multiplier circuits are presented to reduce the QUANTUM COST of the circuits. The designs can be expanded to an N × N dimension. We prove that these multiplier circuits have lower QUANTUM COST, CONSTANT INPUTs, and GARBAGE OUTPUTs compared with previous studies.

Simulation of High-Speed and Low-Power CMOS Binary Image Sensor Based on Gate/Body-Tied PMOSFET-Type Photodetector Using Double-Tail Comparator

In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for highspeed and low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a body that amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltage and returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superior over those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the output voltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low power consumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard 0.18 μm CMOS process.

RETRACTED ARTICLE: Memristor based high speed and low power consumption memory design using deep search method

The demand for low-power devices in today’s world is increasing, and the reason behind this is scaling CMOS technology. Due to scaling, the size of the chip decreases and the number of transistors in System-On-Chip increases. However, transistor miniaturization also introduces many new challenges in circuit design for very large scale integrated circuits. Therefore in this work is introduced a memristor based memory design, the memristor breaks the scaling limitations of CMOS technology and prevails over emerging semiconductor devices. The memristor is forced to the Nano scale design of the invention, and successful fabrication begins to take into account the range of conventional metal oxide semiconductor field effect transistors or more specifically the use of transistors as a whole. The memristor has a history mechanism that allows the memory operation to be combined with the inherent bipolar resistance switching characteristics. Different types of existing mathematical models have been derived from shapes that can be further implemented and tested in a prototype with some crucial parameters thus determined and how they differ from conventional transistor-based designs for a suitable circuit memristor. In this work, low-power complementary metal oxide semiconductor (CMOS) flip-flops have been proposed with deep search pattern method and some key parameters such as delay, power, gate count and other memristor calculations are carried out. The simulations are carried out using Verilog-analog mixed signal. The proposed system is considered as potential devices for building memories because they are very dense, non-volatile scalable devices with faster switching times and low power dissipation and are also compatible with the existing CMOS-technology.

An efficient Verilog-A memristor model implementation: simulation and application

Complementary metal–oxide–semiconductor (CMOS) technology is reaching its limits due to the continuous shrinking process, which has an impact on various aspects including device size, performance, and power consumption. The memristor is one of the promising devices under investigation for use with deep-nanometer CMOS, having applicability in several fields due to its nonlinear behavior, nonvolatility, low power consumption, high density, and CMOS compatibility. Several models for memristors have been developed to date, but there is a requirement for compact models that are both flexible and sufficiently accurate. A general memristor model generated in Verilog-A is discussed herein to confirm its behavior in the one-transistor one-resistor (1T1R) oxide-based random-access memory (OxRAM) configuration, and validated at circuit level. The results of the model correlate well with experimental characterization data for the HfO2-based OxRAM memristor device, describing the characteristics of both its bipolar and unipolar memristor behaviors. The 1T1R structure is analyzed using the Spectre circuit simulator. Two cases are considered, using the cell as either programmable read-only memory (PROM) or electrically erasable programmable read-only memory (EEPROM). The simulation results confirm the desired nonlinear memristor characteristic, and the applicability of the model to fit and simulate different switching behaviors. The results are verified against both electrical and experimental characterization data, suggesting that the Verilog-A model is suitable for low-power and high-density logic circuit applications at the industrial level.

Highly Scaled Strained Silicon-On-Insulator Technology for the 5G Era: Impact of Geometry and Annealing on Strain Retention and Device Performance of nMOSFETs

Strained silicon-on-insulator (SSOI) is a promising platform for 5G, which will require both high-performance and low-power complementary metal–oxide–semiconductor (CMOS) devices. Hence, it is important to understand the behavior of strain in SSOI at deeply scaled dimensions. We thus present a simulation study of SSOI technology, where the strain profiles of “fins” with different dimensions and layer thicknesses are analyzed. We discover, for the first time, that a buried oxide (BOX) as thin as 10–15 nm is able to effectively memorize the strain. It is also able to retain the strain under annealing up to 1000 °C, a result verified by the Raman measurements. Such a thin BOX enables a good back-gate control for dynamic threshold voltage ( ${V}_{\text{t}}$ ) tuning of SSOI transistors. The ability to have a good performance enhancement (from strain), and dynamic ${V}_{\text{t}}$ tunability (from thin BOX) makes SSOI favorable for 5G mixed-signal applications.