Low Power Arithmetic Research Articles

Design of Low Power Arithmetic logic unit using SHE assisted STT / MTJ

Design of Low Power Arithmetic logic unit using SHE assisted STT / MTJ

Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning

Approximate computing provides an emerging approach to design high performance and low power arithmetic circuits. The logarithmic multiplier (LM) converts multiplication into addition and has inherent approximate characteristics. In this article, dynamic range approximate LMs (DR-ALMs) for machine learning applications are proposed; they use Mitchell’s approximation and a dynamic range operand truncation scheme. The worst case (absolute and relative) errors for the proposed DR-ALMs are analyzed. The accuracy and the hardware overhead of these designs are provided to select the best approximate scheme according to different metrics. The proposed DR-ALMs are compared with the conventional LM with exact operands and previous approximate multipliers; the results show that the power-delay product (PDP) of the best proposed DR-ALM (DR-ALM-6) are decreased by up to 54.07 percent with the mean relative error distance (MRED) decreasing by 21.30 percent compared with 16-bit conventional design. Case studies for three machine learning applications show the viability of the proposed DR-ALMs. Compared with the exact multiplier and its conventional counterpart, the back-propagation classifier with DR-ALMs with a truncation length larger than 4 has a similar classification result for the three datasets; the K-means clustering application with all DR-ALMs has a similar clustering result for four datasets; and the handwritten digit recognition application with DR-ALM-5 or DR-ALM-6 for LeNet-5 achieves similar or even slightly higher recognition rate.

Reversible Realization of N-bit Arithmetic Circuit for Low Power Loss ALU Applications

Today, low loss efficient digital calculating systems are among the key focus of researchers. Fast and efficient processing parts are in the concrete demands of this era. Reversible digital design approach is directed towards this need of efficient electronic system design. Arithmetic circuits are considered as the main part of any digital calculating system. Designing of these arithmetic subsystems using reversible design approach leads to the generation of low power loss efficient electronic systems. In this paper, we have proposed a novel approach to design n-bit arithmetic circuit with reversible design approach. This proposed design is compared with existing designs on the basis of some selected performance parameters. Comparison and analysis of these designs show that proposed design is the most optimized approach for reversible realization of arithmetic circuit for low power Arithmetic logic unit (ALU) circuit applications. The proposed model can be used for reversible design of digital computing systems for low power ALU designs.

Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications

Approximate/inexact computing has become an attractive approach for designing high performance and low power arithmetic circuits. Floating-point (FLP) arithmetic is required in many applications, such as digital signal processing, image processing and machine learning. Approximate FLP multipliers with variable accuracy are proposed in this paper; the accuracy and the circuit requirements of these designs are analyzed and assessed according to different metrics. It is shown that the proposed approximate FLP multiplier designs further reduce delay, area, power consumption and power-delay product (PDP) while incurring about half of the normalized mean error distance (NMED) compared with the previous designs. The proposed IFLPM24–15 is the most efficient design when considering both PDP and NMED. Case studies with three error-tolerant applications show the validity of the proposed approximate designs.

SSTL IO Standard Based Low Power Arithmetic Design Using Calana Kalanabhyam on FPGA

Vedic mathematics consists of 16 formulas. Calanakalanabhyam is a Sanskrit word meaning “Sequential motion”. Using this Vedic technique, we will find the roots of the equation in few seconds. We have tried to make an energy efficient Calanakalanabhyam Vedic formula based root finder with 4 inputs and 2 outputs. We have taken different SSTL Input/Output Standards and have done Study of Power by varying frequencies. SSTL Input/Output Standards used in this paper are SSTL15, SSTL18_II, SSTL135, SSTL12, SSTL18_I. The code has been implemented on 28nm FPGA platform, XC7K160T device, FBG676 package and -3 speed grade. With our proposed technique, we have 41-60% achieved reduction in total consumption of power with frequency scaling.

Design of Low Power and Area Efficient 4-bit Arithmetic and Logic Unit using Nanoscale FinFET

In order to strive in VLSI Technology, we have to keep up with the Moore’s law which states that in every 18 month number of transistors gets doubled on a chip. But as we scale down the transistor size problems like Short Channel Effects (SCE), Sub-threshold voltage variation, Drain Induced Barrier Lowering (DIBL), Gate oxide tunnelling leakage etc., comes into the account. To overcome the above problems we moved towards the FinFET based transistor. In this paper we have proposed the “Design of Low power 4-bit arithmetic & logic unit using nanoscale FinFET”. Arithmetic Logic Unit (ALU) is the backbone of any processor, we have performed the logical operations like AND, OR, Inverter, 2’s complement of the number etc. & Arithmetic operation like addition, subtraction, multiplication, parity generation etc. Different techniques are used to achieve the low power on different modules in the design.

Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

Clock Gating Aware Low Power ALU Design and Implementation on FPGA

This paper deals with the design and implementation of a Clock Gating Aware Low Power Arithmetic and Logic Unit that has been developed as part of low power processor design in the platform Xilinx ISE 14.2 and synthesized on 90nm Spartan-3 FPGA. Clock power contributes 45-60 percent of total dynamic power. Hence, clock power reduction is necessary in low power design. In this paper, we analyze theoretical 93.75% clock power reduction in ALU using clock gating techniques. On simulator, we achieved 88.23% clock power reduction using latch based clock gating and 70.58% clock power reduction using latch free clock gating. Index Terms—Clock gate, ALU, FPGA, LUT, clock power, register transfer level, dynamic power, leakage power

Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications

Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications

HW/SW CO-DESIGN FOR LOW POWER ARITHMETIC AND LOGIC UNITS

As many embedded microprocessors are battery driven, low power design is becoming increasingly necessary. In this paper, we proposed hardware-software co-design architecture for low power arithmetic and logic units. By including multiple functional units with the same functions and different speeds, we provide instruction implementations at various power prices. Then, with an assembler level scheduler, we identify and create situations whereby the low-power slow functional units can be utilized. The overall performance is not compromised as no additional stalls are introduced. Simulations show 10%~35% power saving in typical addition operations.