Low-pass Delta-sigma Modulator Research Articles

A Systematic Method for Scaling Coefficients of the Continuous-Time Low-Pass ΣΔ Modulator Using a Simulink-Based Toolbox

The sigma-delta modulator (SDM) is one of the well-established data converter architectures. It is well-known for achieving a high signal-to-noise ratio (SNR). In the SDM, the integrators in the loop filter could suffer from overloading if the signal swing exceeds its maximum level, which leads to performance and SNR degradation. Thus, scaling the system coefficients is needed, such that there is no overloading for the integrators. In this work, we present a systematic general method that could be used for scaling the signal swings in the continuous-time low-pass sigma-delta modulator (SDM). The proposed method can be applied to any continuous-time low-pass SDM architecture, and it includes the scaling of all the possible combinations of the system coefficients. Moreover, an open-source Simulink-based toolbox that includes the systematic method is presented. This toolbox could help the designer to execute the scaling process and the simulations in an efficient way. In addition to that, a design example is discussed to illustrate the proposed method, wherein the presented toolbox is used for simulations, and the simulation results are shown.

Efficiency Improvement of Delta Sigma Modulator-Based Transmitter Using Complex Delta Sigma Modulator and Noise Reduction Loop

This paper proposes an architecture to enhance coding efficiency (CE) of the Delta Sigma Modulator (DSM) transmitters. In this architecture, a complex–low pass delta sigma modulator (LPDSM) is used instead of existing Cartesian–LPDSM and polar–low pass envelope delta sigma modulator (LPEDSM). Simulation results show that for Uplink long-term evolution (LTE) signal with 1.92[Formula: see text]MHz bandwidth and 7.8-dB peak to average power ratio (PAPR), the CE for the complex–LPDSM-based transmitter is equal to 41.7% in compare to 9.7% CE for Cartesian–LPDSM transmitter. Also, due to the resolving of noise convolution problem, the complex–LPDSM-based transmitter baseband part needs lower oversampling ratio (OSR) and clock speed than polar–LPEDSM transmitter baseband part to achieve the same signal-to-noise and distortion ratio (SNDR). In the next step, a quantization noise reduction loop is implemented in this architecture. By using this technique for an Uplink LTE signal with 1.92[Formula: see text]MHz bandwidth, with the same PAPR and OSR of 16, the CE is improved from 41.7% to 56.1% with 40[Formula: see text]dB SNDR.

A 21-GS/s Single-Bit Second-Order Delta–Sigma Modulator for FPGAs

A new high-speed delta–sigma modulator (DSM) topology is proposed by cascading a bit reduction process with a multi-stage noise shaping MASH-1-1 DSM. This process converts the two-bit output sequence of the MASH-1-1 DSM to a single-bit sequence, merely compromising the DSM noise-shaping performance. Furthermore, the high clock frequency requirements are significantly relaxed by using parallel processing. This DSM topology facilitates the designs of wideband software defined radio transmitters and delta–sigma radio-over-fiber transmitters. Experimental results of the FPGA implementation show that the proposed low-pass DSM can operate at 21 GS/s, providing 520-MHz baseband bandwidth with 42.76-dB signal-to-noise-and-distortion ratio (SNDR) or 1.1-GHz bandwidth with 32.04-dB SNDR (based on continuous wave measurements). An all-digital transmitter based on this topology can generate 218.75MBd 256 QAM over 200-m OM4 multimode fiber in real time, with 7-GS/s sampling rate and an error vector magnitude below 1.89%.

Coding Efficiency and Bandwidth Enhancement in Polar Delta-Sigma Modulator Transmitter Using Quantization Noise Reduction and Parallel Processing Techniques

This paper introduces an architecture to enhance coding efficiency (CE) and bandwidth of the delta-sigma modulator (DSM) transmitters. In this architecture a low-pass envelope DSM (LPEDSM) is used instead of the traditional Cartesian low-pass DSM (LPDSM) to reduce the quantization noise and to improve the coding efficiency. The simulation results show that for an uplink long-term evolution (LTE) signal with 1.92[Formula: see text]MHz bandwidth, 7.8[Formula: see text]dB peak-to-average power ratio (PAPR), and an oversampling ratio (OSR) of 32, the CE for the polar LPEDSM transmitter is equal to 41.72% in comparison to 9.7% CE for the Cartesian LPDSM transmitter. In the next step, the CE and bandwidth of the transmitter are improved at the same time by using the quantization noise reduction technique in the polar LPEDSM transmitter with parallel baseband. By using this combined technique in the four-branch transmitter baseband part for an uplink LTE signal with 7.68[Formula: see text]MHz bandwidth, 7.8[Formula: see text]dB PAPR, and an OSR of 32, the CE is improved from 42.59% to 55.86% with 40[Formula: see text]dB signal-to-noise-and-distortion ratio (SNDR) while the clock speed is only 61.44[Formula: see text]MHz which is four times lower than the clock speed requirement of the conventional transmitter baseband part to achieve the same SNDR.

A 10 MHz Bandwidth, 70 dB SNDR Continuous Time Delta-Sigma Modulator With Digitally Improved Reconfigurable Blocker Rejection

This paper presents a continuous-time third-order low-pass delta-sigma modulator (DSM) with digitally enhanced out-of-band (OOB) signal filtering for enhanced blocker rejection in receiver analog-to-digital converters (ADCs). It is well known that strong OOB interferers define the required dynamic range (DR) of a receiver. Usually, a channel-select filter (CSF) is therefore required, together with the succeeding ADC. The feedback-compensated DSM can relax the CSF with its signal transfer characteristic. In this work, this is improved with a reconfigurable digital filter, which modifies the feedback signal of the outer-loop DAC to increase the OOB blocker rejection of the modulator. As a proof of concept, the digitally improved blocker rejection is shown in a prototype design. Additionally, a reconfigurable excess loop delay compensation technique based on an adaptive delay-locked-loop (DLL) has been implemented. The prototype is realized in a 90 nm CMOS technology, works at 480 MHz clock frequency, requires an area of $0.17\;\text{mm}^2$ , and achieves an in-band (IB) SNDR of 70 dB in a bandwidth of 10 MHz with a power consumption less than 14.4 mW. In the prototype, a digitally reconfigurable blocker rejection is realized achieving 6 dB additional suppression from 20 or 40 MHz on, or even 25 dB at the specific frequency of 20 MHz.

Coding efficiency and bandwidth enhancement in polar delta sigma modulator transmitter

This paper introduces an architecture to enhance coding efficiency (CE) and bandwidth of the delta sigma modulator transmitters. In this architecture a low pass envelope delta sigma modulator (LPEDSM) is used instead of traditional cartesian low pass delta sigma modulator (LPDSM) to reduce the quantization noise and to improve the CE. Simulation results show that for an Uplink long term evolution (LTE) signal with 1.4 MHz bandwidth, 7.8-dB peak to average power ratio (PAPR), and an oversampling ratio (OSR) of 32, the CE for the polar LPEDSM transmitter is equal to 42 % in compare to 9.7 % CE for cartesian LPDSM transmitter. In the next step, a quantization noise reduction loop with in-band quantization noise filtering are implemented in this architecture. By using this combined technique for an Uplink LTE signal with 1.4 MHz bandwidth, with the same PAPR and OSR of 32, the CE is improved from 42 to 59.33 % with 40 dB signal to noise and distortion ratio.

Overloading Prediction in Symmetric Cross Coupled Low-Pass Sigma Delta Modulators

This paper evaluates the prediction of stability of various symmetric cross coupled low-pass sigma delta(ΣΔ) modulators, by using the describing function theory. The symmetric cross coupled low pass ΣΔ modulator, enhances performance and stability when compared to conventional noise shaping sigma delta modulators and achieves up to 2Nth order noise shaping from N-path cross coupling with better in-band noise rejection without sacrificing conversion rate and bandwidth. Here, over-loading levels of symmetric cross coupled ΣΔ modulatorsare predicted and compared with time domain simulations for sinusoidal signals. The relationship between stability, NTF and quantizer levels has also been investigated.

A Digitized IF-Over-Fiber Transmission Based on Low-Pass Delta-Sigma Modulation

In this letter, we propose and demonstrate a digitized intermediate frequency (IF)-over-fiber transmission system based on the delta-sigma modulation technique as a means of digitizing an analog IF signal. Using a realized 130-nm CMOS, two-level third-order low-pass delta-sigma modulator (DSM) chip operating at 622.08 MHz, a 64-Quadrature Amplitude Modulation long-term evolution (LTE) 10-MHz signal at a 10-MHz IF frequency was successfully digitized, transported over an emulated digital fiber-optic link, and analyzed in terms of signal spectra, error vector magnitude (EVM), and constellations. The difference between power levels of the received LTE IF signal and quantization noise due to the developed DSM was larger than 45 dB, and an EVM value of 2.48% for the received LTE signal was obtained.

A Reconfigurable <formula formulatype="inline"> <tex Notation="TeX">$\Delta\Sigma$</tex></formula> ADC With Up to 100 MHz Bandwidth Using Flash Reference Shuffling

A reconfigurable 65-nm continuous-time low-pass delta-sigma modulator operates with a sampling frequency from 491 MHz to 1536 MHz, a signal bandwidth from 10 MHz to 100 MHz, and a dynamic range of 75.4 dB to 62.8 dB, respectively. Flash ADC calibration and reference shuffling with zipper rotation are used to improve the linearity of the flash, while also increasing the highest sampling rate and bandwidth of the modulator. Dynamic element matching using a randomized incremented pointer improves the linearity of the DAC.

A High-Resolution Lowpass Sigma-Delta Modulator Applied in Micro-Gyroscope

In this paper, in order to enhance resolution and guarantee the stability of the micro-gyroscope, a high-resolution lowpass sigma-delta modulator is proposed. It employs single-loop fourth-order and full differential structure. The simulated result on the Simulink platform shows that the SNDR is 105.4dB and the effective number of bits (ENOB) is 17.22bits. The entire circuits are implemented with 0.5μm CMOS process. The simulated result on Cadence shows that the SNDR is 99.7dB. The modulator operates at a sampling frequency of 25.6MHz and the signal bandwidth is 100kHz with 128 oversampling ratio (OSR). The dynamic range (DR) is 120 dB approximately and the SNDR changes linearly with the input level.

A reconfigurable low-pass/high-pass $$\varDelta \varSigma$$ Δ Σ ADC suited for a zero-IF/low-IF receiver

This paper presents the design of a reconfigurable delta sigma analog to digital converter. Its main degree of freedom is the choice of the noise shaping between low-pass and high-pass. Thanks to this reconfiguration parameter, the converter takes full advantage of both noise shapings and employs the most suited architecture depending on the received standard. Moreover, the low-pass/high-pass reconfiguration makes the analog-to-digital converter compliant for both the low-IF and the zero-IF receiver architectures. The paper also presents a novel reconfigurable dynamic element matching technique which efficiently addresses the digital to analog converter mismatch for both the high-pass and the low-pass delta sigma modulators. The sampling frequency and the quantizer number of bits are likewise adjustable. A GSM/UMTS compliant delta sigma analog to digital converter including reconfigurable decimator has been designed in a 1.2 V 65 nm CMOS process. The high-pass modulator is employed in a low-IF receiver for the GSM mode to profit from its robustness against offset and 1/f noise. For the UMTS mode, the low-pass modulator is employed in a zero-IF receiver because of its lower sensitivity to clock jitter.

A Novel Dual-Mode Low Pass Sigma-Delta Modulator Chip Design for WCDMA and Bluetooth Applications

A dual-mode low pass sigma-delta (ΣΔ) modulator at clock rates of 160 and 100 MHz respectively with cascaded integrators is presented for WCDMA and Bluetooth applications. One of main features is that cascaded integrators with feedback as well as distributed input coupling (CIFB) topology erase a summation amplifier and save power consumption. Another feature is that only one set loop filter is designed by switching capacitors to achieve a dual-mode function and greatly saves chip area. A prototype is fabricated in TSMC 0.18-m CMOS process. At the supply voltage of 1.8 V, measured results have achieved the SNDR of 42/33 dB over 1/2 MHz, respectively for Bluetooth/WCDMA. The chip dissipates a low power of 10.5 mW. Including pads the chip area is only 0.61 (0.71× 0.86) mm².

A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback

This paper introduces a continuous-time low-pass sigma-delta modulator operating with a seven-phase 400 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,$</tex> </formula> MHz clocking scheme to control time-based processing in the 3-bit two-step quantizer and main digital-to-analog converter (DAC). An on-chip voltage-controlled oscillator and a complementary injection-locked frequency divider are utilized for low-jitter clock signal generation with multiple phases, allowing 3-bit pulse-width modulated feedback with a single-element DAC to avoid performance degradation from unit element mismatch problems associated with conventional multi-bit DACs.

Dynamic Quadrant Swapping Scheme Implemented in a Post Conversion Block for I, Q Mismatch Reduction in a DQPSK Receiver

This paper presents a new dynamic quadrant swapping scheme that reduces crosstalk due to I/Q path mismatch for DQPSK receiver. The scheme reduces crosstalk by selectively transforming/swapping the I, Q components of the received symbols. The scheme's effectiveness is demonstrated by applying it to the IF digitizer part of the receiver. In the IF digitizer the incoming IF (first IF) signal is mixed and then converted to two digital signals, the I and Q signals, both at a second IF. These digital signals are then fed into a post conversion block. In this block dynamic quadrant swapping is applied, which reduces the crosstalk. Using an IF digitizer that includes two separate mixers with two separate low pass sigma-delta modulators for I and Q paths, the scheme's effectiveness is tested. Both simulation results and measured results show a significant improvement in image rejection ratio and BER, when the scheme is applied. With a SNR of 10.8 dB, at a 160.16 MHz incoming IF, and with a data rate of 36 kbps, the scheme improves the measured BER from 4.2 × 10 to 1.4 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">- 3</sup> . At a 10 MHz incoming IF, and with a data rate of 2 kbps, the scheme improves the measured image rejection ratio from 41 dB to 65 dB and the measured BER from 1.3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> to 0.7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> . The post conversion block is layout in 0.09 ¿m CMOS technology. It occupies an area of 0.00092 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and is simpler than previous reported schemes. The IF digitizer is fabricated in 0.35 ¿m CMOS technology.

An Adaptive ELD Compensation Technique Using a Predictive Comparator

This brief presents an adaptive excess loop delay (ELD) compensation technique for continuous-time delta-sigma modulators. This technique utilizes a predictive comparator with adaptive control using the sign least-mean-square algorithm to estimate the compensation coefficients. Contrary to other state-of-the-art compensation methods, the proposed technique is immune to manipulation of the loop filter transfer function and loop circuitry. Consequently, it will not deteriorate the performance of the modulators. Simulations performed on two different delta-sigma modulators show the effectiveness of the proposed technique to compensate the ELD in low-pass and bandpass delta-sigma modulators.

DT Modeling of Clock Phase-Noise Effects in LP CT $ \Delta\Sigma$ ADCs With RZ Feedback

The performance of continuous-time (CT) DeltaSigma modulators is limited by their sensitivity to clock phase noise (PN). The clock PN-induced in-band noise (IBN) is dependent on the magnitude and frequency of both the desired in-band signals and the out-of-band signals, as well as the shape of the clock PN spectrum. This brief presents a discrete-time (DT) model of the dominant clock PN-induced errors. It enables fast and accurate simulations of the clock PN effects with arbitrary input signals, PN spectra, and noise-transfer functions. The model has been verified by CT simulations and measurements on a second-order low-pass CT DeltaSigma modulator with return-to-zero feedback. The flexibility and usefulness of the DT model are demonstrated, and the two dominant clock PN effects are compared by means of simulations with orthogonal frequency-division multiplexing input signals and various PN specifications.

Multibit Delta-Sigma Modulator With Noise-Shaping Dynamic Element Matching

This paper describes a fifth-order multibit low-pass delta-sigma modulator employing a proposed noise-shaping dynamic element matching (NS-DEM) technique to remove DAC nonlinearity error. Unlike most existing DEMs that trade SNR for SFDR, the proposed technique improves both SFDR and SNR. The noise shaping is incorporated in the first integrator of the loop filter without any additional analog circuitry. The fabricated modulator chip achieves 94-dB SFDR and 78-dB DR in 2.2-MHz BW and meets the ADSL2+ specifications.

A LOW POWER CASCADED FEED-FORWARD DELTA-SIGMA MODULATOR FOR RF WIRELESS APPLICATIONS

This paper presents a design of a novel cascaded third-order feed-forward delta-sigma analog-to-digital converter (ADC). This ADC is realized using fully differential switched capacitor architecture and produces a 12-bit resolution at a data output rate (DOR) of 2.5 MS/s for RF wireless applications. The delta-sigma modulator consists of a second-order single-bit feed-forward modulator cascaded with a multi-bit first-order modulator. The cascaded feed-forward third-order (2-1) ADC is simulated using Matlab and Simulink. The delta-sigma modulator was designed using Cadence Virtuoso in TSMC 0.18 μm CMOS technology. The power consumption of the designed modulator is 12.74 mW, and the resolution is 11.85 bits for an over-sampling ratio (M = 32). The figure of merit is 1.38 pJ at a sample rate of 80 MS/s. The proposed delta-sigma modulator is compared with other state-of-the-art low-pass delta-sigma modulators in terms of their speed, power, DOR, and the proposed modulator has one of the lowest power consumption.

Microgyroscope control system using a high-order band-pass continuous-time sigma-delta modulator

The paper presents a novel 6th order continuous-time, force-feedback band-pass sigma-delta modulator control system for the detection mode of micromachined vibratory gyroscopes. Compared with the architecture using a low-pass sigma-delta modulator, this band-pass solution uses a much lower sampling frequency for the sigma-delta modulator and thus reduces the requirement for frequency response of the detection interface and control electronics. In this work, the sigma-delta modulator operates at only four times of mechanical resonant frequency, which allowed its implementation in a continuous-time circuit using discrete electronic components on a PCB; this has the advantage of simple prototyping and can improve the signal anti-aliasing characteristics.

A Subsampling Quadrature &lt;formula formulatype="inline"&gt;&lt;tex&gt;$\Sigma \Delta$&lt;/tex&gt;&lt;/formula&gt; Modulator Based on Distributed Resonators for Use in Radio Receiver

The receiver architecture proposed in this brief seizes the subsampling properties of continuous-time sigma-delta (SigmaDelta) modulators based on distributed resonators to construct a quadrature receiver. The proposed architecture is based on a low-pass SigmaDelta modulator that subsamples an intermediate frequency signal around the sampling frequency and does not require quadrature mixers. Instead, the quadrature mixing is replaced by suitably choosing the sampling instants inside the loop. Two practical circuit implementations are proposed. The first one uses separate circuitry for the I and Q paths. The second architecture introduces an innovative way to produce the I and Q outputs that is immune to path mismatch due to the sharing of all the analog circuitry for both paths. The proposed modulator may be feasible for the typical IF frequencies used in cellular base stations.