A 10 MHz Bandwidth, 70 dB SNDR Continuous Time Delta-Sigma Modulator With Digitally Improved Reconfigurable Blocker Rejection

Abstract

This paper presents a continuous-time third-order low-pass delta-sigma modulator (DSM) with digitally enhanced out-of-band (OOB) signal filtering for enhanced blocker rejection in receiver analog-to-digital converters (ADCs). It is well known that strong OOB interferers define the required dynamic range (DR) of a receiver. Usually, a channel-select filter (CSF) is therefore required, together with the succeeding ADC. The feedback-compensated DSM can relax the CSF with its signal transfer characteristic. In this work, this is improved with a reconfigurable digital filter, which modifies the feedback signal of the outer-loop DAC to increase the OOB blocker rejection of the modulator. As a proof of concept, the digitally improved blocker rejection is shown in a prototype design. Additionally, a reconfigurable excess loop delay compensation technique based on an adaptive delay-locked-loop (DLL) has been implemented. The prototype is realized in a 90 nm CMOS technology, works at 480 MHz clock frequency, requires an area of $0.17\;\text{mm}^2$ , and achieves an in-band (IB) SNDR of 70 dB in a bandwidth of 10 MHz with a power consumption less than 14.4 mW. In the prototype, a digitally reconfigurable blocker rejection is realized achieving 6 dB additional suppression from 20 or 40 MHz on, or even 25 dB at the specific frequency of 20 MHz.