Low Output Conductance Research Articles

Pseudo-source gated beta-gallium oxide MOSFET

This study demonstrates pseudo-source-gated beta-gallium oxide (β-Ga2O3) metal oxide semiconductor field effect transistors (MOSFETs). The proposed pseudo-source gated transistor (pseudo-SGT) architecture has a thin (∼11 nm) recessed channel design, effectively emulating conventional SGT characteristics without significantly compromising on-current. The fabricated devices exhibit remarkable intrinsic gain of 104, low output conductance of 10−8 S/mm, transconductance of 10−3 S/mm, and drain saturation voltage of ∼1.5 V, while maintaining a drain current of 1.3 mA/mm. These enhanced performance metrics significantly expand the potential of β-Ga2O3 MOSFETs for the development of Ga2O3 monolithic power integrated circuits.

On the improved RF performance of step field plate LDMOS transistor

This paper presents an analysis of the Step Field Plate Laterally Diffused Metal Oxide Semiconductor (SFP LDMOS) structure for improved high power and RF performance. The proposed structure is cost-effective, CMOS integrable, and has a high power figure of merit (FoM) due to its high off-state breakdown voltage (BVDS,off) and low specific on-resistance (Rsp). Significant improvement in frequency behavior is observed, as demonstrated by the flatter trans-conductance (gm), 12.5x lower gate-to-drain capacitance (Cgd), 2.5x lower gate-to-source capacitance (Cgs), and lower output conductance (gds). Single tone and double tone analyses are performed on an RF PA circuit implemented in TCAD. Results show ∼5 dBm higher output power (Pout), ∼6 dB higher power gain, and 46% higher drain efficiency (η), which are attributed to ∼1.9x lower drain-to-source capacitance (Cds) and ∼15 dBm lower magnitude of third-order intermodulation distortion due to lower third order derivative of drain current (ID). The paper also explains the device physics behind these observations.

Effect of Step Gate Work Function on InGaAs p-TFET for Low Power Switching Applications.

In this study, we theoretically investigated the effect of step gate work function on the InGaAs p-TFET device, which is formed by dual material gate (DMG). We analyzed the performance parameters of the device for low power digital and analog applications based on the gate work function difference (∆ϕS-D) of the source (ϕS) and drain (ϕD) side gate electrodes. In particular, the work function of the drain (ϕD) side gate electrodes was varied with respect to the high work function of the source side gate electrode (Pt, ϕS = 5.65 eV) to produce the step gate work function. It was found that the device performance varies with the variation of gate work function difference (∆ϕS-D) due to a change in the electric field distribution, which also changes the carrier (hole) distribution of the device. We achieved low subthreshold slope (SS) and off-state current (Ioff) of 30.89 mV/dec and 0.39 pA/µm, respectively, as well as low power dissipation, when the gate work function difference (∆ϕS-D = 1.02 eV) was high. Therefore, the device can be a potential candidate for the future low power digital applications. On the other hand, high transconductance (gm), high cut-off frequency (fT), and low output conductance (gd) of the device at low gate work function difference (∆ϕS-D = 0.61 eV) make it a viable candidate for the future low power analog applications.

(Invited) Multi-Gate Contact-Controlled Transistors

Contact effects are a central focus in the development of high performance thin-film transistors (TFTs) and circuits, motivated by the increased speed and current density achievable by reducing contact energy barriers. Conversely, the rectifying properties of contacts have been utilised to create devices in which the current is, for the most part, controlled by the contact properties and bias conditions rather than the semiconductor channel [1]. These transistors operate at lower speeds but bring operational advantages such as geometrical and bias stress tolerance and have been extensively studied in their operation [2] and potential applications [3, 4] in varied material systems [5-7].We have recently introduced the Multimodal Transistor (MMT), in which channel conductance and charge injection at the source are controlled independently by individual gates [8], offering important benefits to the functionality of analog and mixed signal circuits. These devices build on earlier innovations which modulate contact barriers [1, 5, 6, 7, 9-11] and take advantage of the recent acceptance into the mainstream of multi-gate TFTs [12, 13] to enable constant transconductance, high-speed switching, low output conductance, low-voltage saturation, and robustness against geometrical variability.Here, the structure and operation of MMTs (Figure 1) is briefly reviewed and challenges and opportunities for this device are discussed, focusing on the specifics of solution-processed and organic implementations.[1] J. M. Shannon et al., IEEE Trans. Electron Devices, 60, 2444–2449 (2013).[2] A. Valletta et al., J. Appl. Phys. 114 064501 (2013).[3] R. A. Sporea et al., Scientific Reports 4 4295 (2014).[4] Bestelink, E. et al., IEEE Sens. J., 20 (24), 14903 (2020).[5] Zhang, J., et al, PNAS 116, 4843 (2019).[6] Lee, S. and A. Nathan, Science 354, 302 (2016).[7] Jiang, C. et al, Science 363, 719 (2019).[8] E. Bestelink et al., Advanced Intelligent Systems, 2000199 (2020).[9] Torricelli, F. et al, Nat. Commun. 7, 1 (2016).[10] Yoo H. et al., Sci. Rep. 7, 1 (2017).[11] Uemura T. et al., Adv. Mater. 26, 2983 (2014).[12] Myny, K. et al., IEEE JSSC 46 (5), 1223, (2011).[13] Lee S. et al., JSID 27, 507, (2019).Figure 1. A) Schematic cross-sections of the multimodal transistor (MMT) showing its principle of operation: conduction state is set by the channel gate CG2, while current magnitude is controlled by source gate CG1. B) output characteristics of a nanocrystalline silicon MMT indicating the early saturation and constant transconductance, gm . C and D) are transfer characteristics obtained by varying CG1 and CG2 voltages, respectively. Figure 1

Fin Cross-Section Shape Influence on Short Channel Effects of MuGFETs

Multiple-gate FETs is normally constructed on pre-etched silicon fins. These devices often present casual width variations along the silicon height; mostly caused by technological limitations of the fin definition process, due to non-ideal anisotropic etch. The resulting devices have, consequently, non-rectangular cross-sections, which can affect their electrical behavior. This work addresses the dependence of fin width non-uniformity on the occurrence of short-channel effects through comparative analysis, based on threedimensional numeric simulation of non-rectangular cross-section devices. The influence of the fin crosssection shape on electrical parameters showed to be dependent on channel length, becoming more sensible to the fin shape as the channel length is reduced, with better DC performance present on devices with bottom fin width smaller than top fin width due to the higher transconductance and lower output conductance, resulting on higher intrinsic voltage gain. For opposite fin shapes the total gate capacitance present higher values, beneficiating AC analog parameters, such as unit gain frequency.

Double gate symmetric tunnel FET: investigation and analysis

In this work, using calibrated 2D simulations, the authors first demonstrate that the OFF-state current and subthreshold swing (SS) are significantly high for the double gate Ge source/drain symmetric p-n-p tunnel field effect transistor (TFET) with a silicon channel without n + pockets at the source- and drain-channel interfaces. They further establish that using $n^{+}$n+ pockets at the source- and drain-channel interface, the Ge source/drain symmetric p-n-p TFET exhibits a 130 times improvement in I ON / I OFF ratio and a 26% reduction in SS due to the two orders of magnitude reduction in its OFF-state current when compared with the one without the n + pockets. The results also indicate that the Ge source/drain symmetric p-n-p TFET suffers from a low output conductance at low drain voltages. Since the proposed device exhibits bidirectional current flow, it can be easily integrated with the conventional complementary metal-oxide semiconductor technology.

Influence of Channel Length and High-K Oxide Thickness on Subthreshold DC Performance of Graded Channel and Gate Stack DG-MOSFETs

Comparative assessment of graded channel gate stack (GCGS) DG MOSFET structure is done by using two-dimensional (2D) Sentrausu TCAD simulator for different high K oxide thickness. This novel device includes gate stack (GS) engineering (high K) and nonuniformly channel engineering (GC) to suppress the short channel effects and improve the device performance. This novel device can be a better alternative for the future high speed switching and low power circuit applications. It has the advantage of improved breakdown voltage, reduced leakage current, low output conductance and reduced bipolar parasitic effects. The given device must be properly investigated with respect to the variation of different high K oxide thickness on different parameters such as drain induced barrier lowering (DIBL), subthreshold slope (SS), [Formula: see text]/[Formula: see text], [Formula: see text] roll off before fabrication to have better reliability. The 2D Sentrausu TCAD simulator using drift-diffusion model was used to simulate the developed structure and good agreement is obtained with respect to already published result in the sub-threshold regime. The result indicates that there is a need to be optimize the DC parameters for specific circuit applications.

An investigation of highly scaled III-nitride Gallium-face and Nitrogen-face HEMTs

Electrical performance of highly scaled III-nitride Ga-face and N-face HEMTs have been investigated using a two-dimensional numerical simulator. Four HEMT structures were studied, in three of which GaN substrate were grown in Ga-polar direction and in the last structure GaN substrate was grown in N-polar direction. Simulation results indicate that N-face structure has superior performance as compared with Ga-face structures. The undesirable effects originated from a potential distribution in the channel and current injection through the buffer effectively decrease and therefore their resultant effects such as low output conductance, threshold voltage shift and soft pinch-off become much less noticeable in N-face HEMT structure as compared with Ga-face HEMTs with similar geometry. Furthermore, superior small signal, high frequency characteristics as compared to Ga-face HEMTs structures can be achieved.

The performance measure of GS-DG MOSFET: an impact of metal gate work function

The quantitative assessment of the nanoscale gate stack double gate (GS-DG) MOSFET performance values are numerically calculated with different gate metal work functions (Φm = 4.52 eV, 4.6 eV, 4.7 eV). The effect of electrostatic control on dc, analog and RF figures of merit (FOMs) which includes subthreshold slope (SS), drain induced barrier lowering (DIBL), transconductance generation factor (TGF), early voltage (VEA), intrinsic gain (AV), cut off frequency (fT) and transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) have been investigated for the model GS-DG MOSFET. Higher TGF and AV was achieved with Φm = 4.6 eV for the device. For a better comparison among the analog/RF FOMs, the threshold voltage (Vth) is maintained at a constant value for different work function cases. To achieve a constant Vth, the channel doping (NA) and source/drain doping (ND) is tuned accordingly for all device cases. Superior fT which is due to higher transconductance (gm) and lower output conductance (gd), was observed for the device. In addition, better gain performances i.e. GFP and GTFP were achieved resulting from improved gm. Thus, the device structure modelled with Φm of 4.6 eV can be considered as a better candidate for analog and RF circuit applications.

Schottky barrier source-gated ZnO thin film transistors by low temperature atomic layer deposition

We have fabricated ZnO source-gated thin film transistors (SGTFTs) with a buried TiW source Schottky barrier and a top gate contact. The ZnO active channel and thin high-κ HfO2 dielectric utilized are both grown by atomic layer deposition at temperatures less than 130 °C, and their material and electronic properties are characterized. These SGTFTs demonstrate enhancement-mode operation with a threshold voltage of 0.91 V, electron mobility of 3.9 cm2 V−1 s−1, and low subthreshold swing of 192 mV/decade. The devices also exhibit a unique combination of high breakdown voltages (>20 V) with low output conductances.

Junctionless MOSFETs with laterally graded-doping channel for analog/RF applications

In this paper, we propose a laterally graded-channel pseudo-junctionless (GPJL) MOSFET for analog/RF applications. We examine the dynamical performance of GPJL MOSFET and compare it with the common junctionless (JL) MOSFET architecture using a 2-D full-band electron Monte Carlo simulator (MC) with quantum correction. Our results indicate that the GPJL MOSFET outperforms the conventional JL MOSFET, yielding higher values of drain current (I ds), transconductance (g m), and cutoff frequency (f t). Further, the emerging electric field and velocity distributions, as a consequence of the channel engineering introduced by the GPJL MOSFET, result in lower output conductance (g ds) and higher early voltage (V ea). The preeminence of the GPJL transistor over the JL transistor is further illustrated by showing improvements on the intrinsic voltage gain (A vo) in the subthreshold regime, to as high as 61 %. These results indicate that our proposed GPJL MOSFET yields improvement in the analog/RF performance metrics as compared to JL MOSFETs.

Role of Joule Heating on Current Saturation and Transient Behavior of Graphene Transistors

We use simulations to examine current saturation in sub-micron graphene transistors on SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si. We find that self-heating is partly responsible for current saturation (lower output conductance) but degrades current densities above 1 bmA/μm by up to 15%. Heating effects are reduced if the supporting insulator is thinned or, in shorter channel devices, by partial heat sinking at the contacts. The transient behavior of such devices has thermal time constants of ~ 30-300 ns, which is dominated by the thickness of the supporting insulator and that of the device capping layers (a behavior also expected in ultrathin-body SOI transistors). The results shed important physical insight into the high-field and transient behavior of graphene transistors.

Fabrication and characterisation of high-performance and high-current back-gate thin-film field-effect transistors using sorted single-walled carbon nanotubes

The authors present the wafer scale fabrication and characteristics of back-gate semiconducting carbon nanotube thin-film field-effect transistors (SN-TFTs) suitable for high-current applications. Good on-off current ratio TFTs using affordable 95- purity semiconducting tubes by appropriately choosing the length of the nanotubes and improving the nanotube density have been demonstrated. Moreover, the nanotube thin-film deposition is carried out using a simple solution-based assembly method and good TFT performance and high currents are achieved with random-oriented network of nanotubes. Hafnium oxide (HfO x ) is used as the gate dielectric material to improve the device performance. The global gate devices have shown an excellent p -type behaviour with a low output conductance value of 0.3 S. The SN-TFTs have exhibited a maximum on off ratio of 4 10 4 at lower operating gate voltages, a maximum on-current of 3.1 mA at a current density of 6.2 A/ m, a steep sub-threshold slope of 600 mV/decade, threshold voltage of 1.5 V, a maximum normalised transconductance of 0.7 S/ m and a maximum carrier mobility of 44.2 cm 2 /V s.

Source-Gated Transistors for Versatile Large Area Electronic Circuit Design and Fabrication

Source-gated transistors (SGTs) comprise a blocking contact or potential barrier at the source, which control the current. The paper describes how SGTs can be optimized for particular applications and for specific semiconductor material systems. It is shown how the saturation voltage can be designed to be an order of magnitude smaller than in equivalent FETs to give power savings of over 50% for the same current output. The SGT also achieves a better saturation regime, with lower output conductance over a larger range of drain voltages. Flat-panel lighting, remote sensing and signal processing and large-area circuits made using inexpensive but imprecise patterning techniques are some of the applications which could benefit from incorporating these devices.

New Bidirectional T-Shaped Triple-Gate n-Type Polycrystalline Silicon Thin-Film Transistors Formed by Low-Temperature Sequential Lateral Solidification Process to Reduce of Kink Effects

A new bidirectional T-shaped triple-gate device structure, which suppresses the kink effect of sequential lateral solidification (SLS)-processed polycrystalline silicon thin film transistors (poly-Si TFTs), is proposed and fabricated without any additional process. The proposed poly-Si TFTs have a lateral grain growth in channels, similar to TFTs fabricated by SLS or continuous wave (CW) laser crystallization. The whole current flow of the proposed device is mainly affected by the grain boundaries of lateral grain growth. The bidirectional T-shaped triple-gate structure has incorporated a channel located parallel to the lateral grain growth direction, and the another channel located vertically to the lateral grain growth direction. It is verified from experimental and simulation results that the proposed bidirectional T-shaped triple-gate TFT effectively suppresses the kink current of poly-Si TFT with anisotropic mobility in the triple-gate structure. Our experimental results show that the proposed bidirectional T-shaped triple-gate TFT can suppress the kink effect more effectively than the conventional dual-gate TFT, and L-shaped dual-gate TFT and can improve reliability under the high drain bias condition. The proposed device demonstrates that bidirectional operation is possible for integrated circuits compared with the L-shaped dual-gate structure that shows only fixed one-directional behavior. The proposed device exhibits a very low output conductance in the saturation regime, and this result indicates that higher output resistance is obtained in the proposed bidirectional T-shaped triple-gate TFT.

Channel Length Scaling in Graphene Field-Effect Transistors Studied with Pulsed Current−Voltage Measurements

We investigate current saturation at short channel lengths in graphene field-effect transistors (GFETs). Saturation is necessary to achieve low-output conductance required for device power gain. Dual-channel pulsed current-voltage measurements are performed to eliminate the significant effects of trapped charge in the gate dielectric, a problem common to all oxide-based dielectric films on graphene. With pulsed measurements, graphene transistors with channel lengths as small as 130 nm achieve output conductance as low as 0.3 mS/μm in saturation. The transconductance of the devices is independent of channel length, consistent with a velocity saturation model of high-field transport. Saturation velocities have a density dependence consistent with diffusive transport limited by optical phonon emission.

Analog/RF Performance of Multichannel SOI MOSFET

In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned silicon bodies (UTBs). In other words, the operation of the MCFET is theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET with a gate length of 50 nm are extracted and discussed. Thanks to the enormous transconductance (gm) and very low output conductance, the RF/analog performances of MCFET-voltage gain (A VI) and early voltage (V EA) are superior compared with that of the single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency (fT), due to the large total input gate capacitances (C GG). This inspires the introduction of spacer engineering in MCFET, aiming at improving both C GG and fT. The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications.

Temperature-Dependent Characteristics of a Pseudomorphic High Electron Mobility Transistor with Graded Triple Delta-Doped Sheets

The temperature-dependent characteristics of an interesting double-channel pseudomorphic high electron mobility transistor with graded triple δ-doped sheets are systematically studied and demonstrated. By using the graded triple δ-doped sheets and InGaAs double-channel structure, the studied device exhibits temperature-dependent dc and microwave characteristics well. Experimentally, for a gate device, the high turn-on voltage of 1.06 , low gate leakage current of 76 at , high maximum transconductance of 175 with 1.6 broad operating regime , low output conductance of 0.56 , and high voltage gain of 306 (259) are obtained at 300 , respectively. Furthermore, good device performance with low-temperature variation coefficients under the operating range from is obtained. Moreover, good agreements between the simulated analysis and experimental results are found.

Temperature-dependent characteristics of an InP/InGaAs double heterojunction bipolar transistor with a step-graded InAlGaAs collector

The dc and electron impaction ionization characteristics of an InP/InGaAs double heterojunction bipolar transistor with a step-graded InAlGaAs collector structure are studied and reported. From the experiments, the studied device shows a better common-emitter breakdown voltage and lower output conductance at higher temperature operations. Due to the insertion of a step-graded InAlGaAs collector structure at the base-collector heterojunction, the usually observed switching and hysteresis phenomena in InP/InGaAs-based HBTs are not seen in the studied device. The temperature-dependent electron impact ionization characteristics are also investigated. Above all, the studied DHBT device provides the promise for millimeter-wave and power circuit applications.

Comparative study on temperature-dependent characteristics of InP∕InGaAs single- and double-heterojunction bipolar transistors

Interesting temperature-dependent characteristics of InP∕InGaAs-based single-heterojunction bipolar transistor (SHBT) and double-heterojunction bipolar transistor (DHBT) devices are compared and studied. Experimentally, both studied devices show wider collector current (IC) operation regions, with over 11 decades in magnitude of collector current (IC=10−12to10−1A). However, the studied DHBT exhibits improved breakdown characteristics [common-emitter breakdown voltage (BVCEO)=8.05V and common-base breakdown voltage (BVCBO)=11.3V] and low output conductance at high temperature. Moreover, the undesired current-blocking effect, switching, hysteresis phenomenon usually found in an InP∕InGaAs conventional DHBT are not observed in the DHBT device. As compared with the studied SHBT, the studied DHBT shows a lower multiplication factor and weaker temperature dependence. Therefore, it is known that, based on experimental results, the studied DHBT device provides the promise for low-voltage and low-power circuit app...