Low Resistance Ohmic Contacts Research Articles

Al-rich AlGaN based transistors

Research results for AlGaN-channel transistors are reviewed as they have progressed from low Al-content and long-channel devices to Al-rich and short-channel RF devices. Figure of merit (FOM) analysis shows encouraging comparisons relative to today’s state-of-the-art GaN devices for high Al-content and elevated temperatures. Critical electric field (EC), which fuels the AlGaN transistor FOM for high Al-composition, is not measured directly, but average gate-drain electric field at breakdown is substantially better in multiple reported AlGaN-channel devices compared to GaN. Challenges for AlGaN include the constraints arising from relatively low room temperature mobility dominated by ternary alloy scattering and the difficulty of making low-resistivity Ohmic contacts to high Al-content materials. Nevertheless, considerable progress has been made recently in the formation of low-resistivity Ohmic contacts to Al-rich AlGaN by using reverse compositional grading in the semiconductor, whereby a contact to a lower-Al alloy (or even to GaN) is made. Specific contact resistivity (ρc) approaching ρc ∼ 2 × 10−6 Ω cm2 to AlGaN devices with 70% Al-content in the channel has been reported. Along with scaling of the channel length and tailoring of the threshold voltage, this has enabled a dramatic increase in the current density, which has now reached 0.6 A/mm. Excellent ION/IOFF current ratios have been reported for Schottky-gated structures, in some cases exceeding 109. Encouraging RF performance in Al-rich transistors has been reported as well, with fT and fmax demonstrated in the tens of gigahertz range for devices with less than 150 nm gates. Al-rich transistors have also shown lesser current degradation over temperature than GaN in extreme high-temperature environments up to 500 °C, while maintaining ION/IOFF ratios of ∼106 at 500 °C. Finally, enhancement-mode devices along with initial reliability and radiation results have been reported for Al-rich AlGaN transistors. The Al-rich transistors promise to be a very broad and exciting field with much more progress expected in the coming years as this technology matures.

High Resolution Investigation on the NiAu Ohmic Contact to p-AlGaN|GaN Heterostructure

The low-resistance ohmic contact NiAu|p-type AlGaN|GaN was carefully investigated by high resolution electron microscope (HRTEM) and X-ray photoelectron spectroscopy (XPS) after two-step annealing at 550 and 750°C. It is shown that complicate double-direction diffusion and reaction occur in the metal layer and underlying GaN layer. The stacks of Ni|Au|Ni|Au turn into one alloyed layer and an intimate relationship establishes at the NiAu|GaN boundary which should play a primary role in ohmic contact to lower the contact barrier. A great part of Ni is oxidized as dispersive NiO nanoclusters in the metal layer, which might have an effect to hinder Ga atoms migrating upward. So at the intimate interface, the metal layer close to the contact enriched with Ga and Au, and the GaN upper layer metallized by Au and Ni should reduce the lattice mismatch and the contact barrier. Dense vacancies in the upper GaN layer and dislocations connected with the contact boundary also have the effects to improve the current carrier transportation. So the low ohmic contact to p-GaN should be obtained by the combination of these microstructural characteristics.

Influence of the Metallization Composition and Annealing Process Parameters on the Resistance of Ohmic Contacts to n-type 6H-SiC

For silicon carbide, the problem of obtaining low-resistance ohmic contacts with improved service characteristics remains topical despite a significant body of experimental data. The influence exerted by the composition of Ni and TiAl metallization, alloying parameters, additional doping of the contact layer of silicon carbide (SiC) with N+ nitrogen ions, and the crystallographic Si- or C-face on the resistance of ohmic contacts to n-6H-SiC is examined. It is found that the greatest influence on how ohmic contacts to n-6H-SiC are formed is exerted by the alloying process resulting in a decrease in the contact resistance by approximately six times. The process of additional doping with N+ also reduces the contact resistance by nearly a factor of four. It is found that low-resistance contacts can be obtained on both faces with approximately the same low resistance. TiAl metallization is optimal for the C-face, and Ni metallization, for the Si-face. This choice of metallization makes it possible to obtain ohmic contacts on both polar faces with approximately the same resistances on the order of 2.5 × 10–4 Ω cm2.

Interface dynamics in ohmic contact optimization on AlGaN/GaN heterostructure by the formation of TiN

We illustrate a systematic approach to reduce the ohmic contact resistance on AlGaN/GaN heterostructure. We have optimized the ohmic contact resistance by varying the thickness of AlGaN barrier layer, Ti layer, Al/Ti ratio, and temperature. We have observed nonlinear dependency on various process conditions. Careful observations on performed experiments bring out the interface dynamics of the metal and semiconductor layers. We have demonstrated a very low typical contact resistance of 0.06 Ω.mm for AlGaN barrier thickness of 13 nm, Ti/Al/Ni/Au of 12/150/40/50 nm, and annealed at 775 °C. The minimum contact resistance is found to be 0.05 Ω mm when measured across devices. This RC value is appropriate for high power RF applications of AlGaN/GaN based high electron mobility transistors. This value of the contact resistance is the lowest among the values reported on AlGaN/GaN heterostructure using alloyed contacts. A lower thickness AlGaN barrier can help to reduce the thermal budget for achieving low ohmic contact resistance. This is achieved at lower critical thickness for Ti which is dependent on the AlGaN barrier thickness. It is also observed that Ti:Al ratio should be increasingly larger for decreasing thickness of Ti. This trend is observed till 7 nm of Ti.

Formation of Ohmic Contacts to n-GaAs at Temperatures Compatible with Indium Flip-Chip Bonding

Heterogenous integration of III-V photodetectors with Si readout circuitry is an enabling technology for applications including focal plane arrays [1] and concentrating solar cells [2, 3]. Typical integration schemes include low temperature flip-chip bonding using indium (In) bump bonds, followed by epoxy underfill, and mechanical and/or chemical removal of the III-V substrate to expose the epitaxially grown detector layers [1]. For maximum flexibility in device design and processing, it is desirable to be able to form low resistance illumination-side contacts to either p-type or n-type layers after flip-chip bonding. Formation of non-alloyed contacts to p-GaAs is relatively straightforward and can be readily implemented after flip-chip bonding [4]. Conventional contacts to n-GaAs are formed by evaporation of Ge/Au/Ni followed by a rapid thermal annealing step at 400 °C [4], considerably above the 156 °C melting point of In and above the degradation temperature of many standard underfill epoxies. Several groups have studied the formation of ohmic contacts to n-GaAs through low temperature annealing of Pd/Ge/Au metal stacks [3, 5, 6], however all reports to date have used annealing temperatures near or above the melting point of In. In this work, we report the formation of ohmic contacts with a specific contact resistivity as low as 5.6×10-6 Ω-cm2 after annealing at a temperature of 140 °C, significantly below the In melting point. Figures 1 and 2 show experimental results of transfer line method (TLM) test structures measured on an epitaxially grown 800 nm thick, 1x1018 cm-3 n-GaAs layer with 7 nm Pd/ 50 nm Ge/ 200 nm Au contacts patterned with photolithography and evaporation. The samples were annealed in an oven with a N2 ambient and measured repeatedly throughout the annealing process. We observe a transition from Schottky to ohmic behavior after 10 hours of annealing followed by a steady decrease in resistance for annealing times out to 48 hours. A companion sample that had been flip-chip bonded with In bumps and underfilled with Epotek 301 epoxy showed no degradation after annealing. The black line in Fig. 1 is provided as a reference of the measured specific contact resistivity of a standard Ge/Au/Ni/Au metal stack deposited on the same n-GaAs layer after a 30 second, 400 °C anneal. The creation of low-resistance ohmic contacts to n-GaAs at this low temperature is an enabling technology for III-V heterogeneous integration efforts with a wide array of temperature-sensitive materials such as In, epoxies, photoresists, and plastics. Acknowledgment Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.

Intimate Ohmic contact to two-dimensional WSe2 via thermal alloying

The most important interface in semiconductor devices is the interface between the semiconductor and the first layer of the metal contact. However, the van der Waals (vdWs) gap in two-dimensional (2D) materials hindered the formation of an intimate contact between the 2D material and the metal electrode, limiting the device performances. We demonstrated a gapless Ohmic contact to 2D WSe2 by forming a Pt−W−Se alloy, which significantly improved the device performances (contact resistance, current on/off ratio, output current density, field-effect mobility, and hysteresis) of the 2D WSe2 field-effect transistor. The contact resistance to 2D WSe2 was reduced by more than seven orders of magnitude after thermal alloying. The disappearance of the vdW gap confirmed by scanning transmission electron microscopy enhanced the hole conduction and quenched the electron conduction. Our strategy of metallurgical alloying is effective to form a low-resistance stable Ohmic contact to WSe2, which paves the way for utilization of the full potential of 2D materials.

Metal‐Contact‐Induced Transition of Electrical Transport in Monolayer MoS2: From Thermally Activated to Variable‐Range Hopping

AbstractAn understanding of the charge transport of atomically thin molybdenum sulfide (MoS2) beneath the metal electrode is important to the fabrication of high performance MoS2 devices and circuits with low ohmic contact resistance. However, the carrier‐transport mechanism in monolayer MoS2 under the metal contact has remained elusive due to the difficulty of measuring the electrical properties of MoS2 in contact regions. A method to distinguish the electrical properties of monolayer MoS2 in the contact and channel regions is presented. Temperature‐dependent measurement reveals that the carriers are thermally activated in the channel region. In contrast, they are variable‐range hopping in the contact region. This difference can be attributed to the localization of the MoS2 electronic states caused by metal‐induced gap states. The variable‐range hopping transport in MoS2 under contact causes a reduction of the carrier mobility and an increase in the contact resistance. This work is not only important for fundamental understanding of metal–MoS2 contact but also helpful for further improving the performance of MoS2 devices.

Impact of Silver Surface Morphology on the Wall Plug Efficiency of Blue Vertical Light-Emitting Diodes

Due to merits of good thermal conductivity and vertical current distribution, vertical light-emitting diodes (VLEDs) have been widely studied for many years. However, the wall plug efficiency (WPE) remains limited by the light trapping effect in GaN cavity and difficulties to achieve low-resistance ohmic contacts to p-GaN. As one of the solutions, Ni-/Ag-based mirror layers as ohmic contacts have attracted much attention due to the high work function of Ni and high reflectivity of Ag for blue light. In this paper, a Ni/Ag/Ni/Ag/Ti metal stack was deposited separately on the surface of p-GaN. A high WPE of 45.7% for GaN-based blue VLEDs on Si substrates has been achieved at the mean diameter (69 nm) of Ag grains and root-mean-square (rms) surface roughness (2.06 nm) of Ag mirror layers. There are three impacts on VF: formation of NiO, growth of Ag grain, and increases of Ag oxide. The impacts of surface topography on optical properties are investigated by the Mie scattering theory for Ag grains and surface scattering theory for roughness surface of Ag mirror layer. The conclusion shows that: 1) with growth of Ag grain, the absorption of Ag grains is heightened obviously and the intensity distribution of scattering light with scattering angle is changed from uniformity to irregularity and 2) since the magnitudes of specular reflectance are dramatically larger than the scattering about 1011 times, the specular reflectance of Ag roughness surface totally covers the attribution of scattering and is only decided by rms values and wavelength of incident light.

Annealing temperature dependence of alloy contact for N-polar GaN HEMT structure

The N-polar face of the GaN high electron mobility transistor (HEMT) is capable of forming a low-resistivity ohmic contact. However, few reports to date describe the process of fabricating N-polar GaN HEMTs. In the present study, we investigated the dependence of the contact electrode metal resistance on the annealing temperature. A circular transmission line model was used to measure the contact resistance. Low resistances of 10−5–10−6 Ω cm2 in the as-deposited state were observed. Contact characteristics following the annealing treatment deteriorated at low temperatures and improved again at high temperatures. This tendency is possibly related to the thin oxide layer at the interface between Ti and GaN. Using Ti/Al/Ti/Au electrodes of 20/100/10/50 nm, we observed a contact resistivity of 2.9 × 10−6 Ω cm2 after annealing at 775 °C.

(Keynote) Exploration of Process Techniques for Ga2O3 Based Diodes

Monoclinic β-phase Ga2O3 has outstanding potential for power electronics, and high quality, large diameter bulk crystals and epitaxial layers of Ga2O3 are already available with a wide range of controllable n-type doping levels by edge-defined film-fed (EFG) growth using iridium crucibles, by Czochralski or by float zone. The direct energy bandgap of Ga2O3, ∼4.9 eV, yields a very high theoretical breakdown electric field (∼8 MV/cm). For power electronics, the Baliga figure-of-merit, proportional to carrier mobility, critical electric field and breakdown voltage, is almost four times higher for Ga2O3 than for GaN. Currently, the major limitation for Ga2O3 based device fabrication is the lack of low resistance Ohmic contacts, low damage dry etching process, and thermally stable Schottky contacts. In this work, we review the processing techniques of Ohmic and Shcottky metallizations, plasma etching, surface treatments, and dielectrics for gate oxides as well as diode edge terminations.

Structural and electrical studies on Ti/Al-based Au-free ohmic contact metallization for AlGaN/GaN HEMTs

In order to fabricate the AlGaN/GaN-on-Si HEMTs on existing Si-CMOS production lines, manufacturing processes must meet the rigors of Si-CMOS technology eliminating Au. One of the requirements is formation of Au-free, low resistivity ohmic contacts to AlGaN/GaN heterostructures. In this work we report structural and electrical studies of Ti/Al-based ohmic contacts to AlGaN/GaN HEMTs with TiN/Cu cover layers. Ohmic contacts have been observed after annealing of Ti/Al/TiN/Cu or Ti/Al/Ti/TiN/Cu/TiN multilayers on recessed AlGaN/GaN structure at temperature of 550 °C, specific contact resistance is about 2.3 × 10−4 Ω cm2, however, lower value was obtained after annealing at 750 °C. The XRD and TEM studies reveal formation of additional phases during annealing, namely Al3Ti and Ti2AlN inside the volume of the metallization stack and AlN at metal/GaN interface. Measured dependence of contact resistance on temperature suggests a “metal-like” carrier transport mechanism in partially recessed Ti/Al/Ti/TiN/Cu ohmic contact to 2D electron gas.

Device processing and junction formation needs for ultra-high power Ga2O3 electronics

Abstract

Comparison of defect structure in Si and Ge ion implanted GaN epilayers by RBS/channeling

In this work, we compared ion implantation n-type doping processes in GaN using Si+ or Ge+ ions, by conducting structural and electrical characterization. In the case of Ge+ implantation processes, we compared both the standard single implantation and the sequential doping technique. Analysis of RBS/c spectra and AFM images did not show surface degradation after each technological step (RMS < 1 nm). RBS/c studies showed that the sequential Ge+ implantation/annealing process leads to lowering of the defect concentration as compared to the single implantation process. All those doping processes resulted in low specific ohmic contact resistance RC < 1 Ω·mm. The obtained sheet resistivity of Si-implanted GaN region was RSH = 120 Ω/□, as compared to RSH of 500–530 Ω/□ for Ge-implanted GaN regions.

Van der Waals Stacking Induced Transition from Schottky to Ohmic Contacts: 2D Metals on Multilayer InSe.

Incorporation of two-dimensional (2D) materials in electronic devices inevitably involves contact with metals, and the nature of this contact (Ohmic and/or Schottky) can dramatically affect the electronic properties of the assembly. Controlling these properties to reliably form low-resistance Ohmic contact remains a great challenge due to the strong Fermi level pinning (FLP) effect at the interface. Herein, we employ density functional theory calculations to show that van der Waals stacking can significantly modulate Schottky barrier heights in the contact formed between multilayer InSe and 2D metals by suppressing the FLP effect. Importantly, the increase of InSe layer number induces a transition from Schottky to Ohmic contact, which is attributed to the decrease of the conduction band minimum and rise of the valence band maximum of InSe. Based on the computed tunneling and Schottky barriers, Cd3C2 is the most compatible electrode for 2D InSe among the materials studied. This work illustrates a straightforward method for developing more effective InSe-based 2D electronic nanodevices.

Low resistivity ohmic contacts on lightly doped n-type β-Ga2O3 using Mg/Au

Mg/Au stacks were introduced to prepare ohmic contact at different annealing temperatures on Sn lightly doped β-Ga2O3. Linear current–voltage characteristics were realized when the annealing temperatures were 300, 400 and 500 °C. The transmission line measurements were used to extract the specific contact resistance (ρc) of the annealed samples. The ρc decreased as annealing temperature increased and a minimum ρc of 2.1 × 10−5 Ω cm2 was obtained for the sample annealed at 500 °C. However, the contact electrodes with the ρc of 1.3 × 10−4 Ω cm2 after annealing at 400 °C had better surface profile and stability. The ohmic contact mechanism and stability of electrodes were discussed in details.

Formation of non-alloyed Ti/Al/Ni/Au low-resistance ohmic contacts on reactively ion-etched n-type GaN by surface treatment for GaN light-emitting diodes applications

Ti/Al/Ni/Au (30/120/20/100 nm) non-alloyed ohmic contacts on reactively ion-etched n-GaN have been obtained by thermal annealing in N2 + O2 ambient prior to metal contacts deposition. After surface treatment, contacts show the linear current–voltage (I–V) characteristics with specific contact resistance (SCR) of 2.91 × 10−5 Ω-cm2 without any post-deposition annealing, whereas, SCR of untreated sample has been found 1.02 × 10−4 Ω-cm2. The improvement in SCR of Ti/Al/Ni/Au contacts with this process may be attributed to formation of n+-highly doped layer due to presence of oxygen during thermal annealing. A further increase in SCR of non-treated sample from 1.02 × 10−4 Ω-cm2 to 3.54 × 10−4 Ω-cm2, has been observed on further annealing of contacts at 550 °C in N2 + O2 ambient for 5 min, which is generally an essential condition for formation of low-resistance highly transparent p-contact on p-GaN during fabrication of conventional GaN light-emitting diodes (LEDs). Based on X-ray photoelectron spectroscopy results, we found that there is increase in Ga 3d photoelectron binding energy with this surface treatment, which indicates a shift of Fermi level closure to conduction band, resulting in decrease of Schottky barrier height (SBH). The reduction in SBH is responsible for formation of low-resistance Ohmic contacts on n-GaN. Such non-alloyed n-contacts formed on thermally annealed reactively etched n-GaN surface may open for fabrication of more efficient conventional GaN LEDs. In addition, the forward voltage of GaN LED fabricated by present suggested process lowered by an amount of 0.37 V at 100 mA compared to standard process.

Investigating the RTA Treatment of Ohmic Contacts to n-Layers of Heterobipolar Nanoheterostructures

The preparation of ohmic contacts to heterobipolar nanostructures has a number of characteristic features. In addition to the basic requirement of minimizing contact resistance, contacts to this type of structures have a transition layer whose depth of penetration must not exceed the emitter layer’s thickness, due to the possibility of short-circuiting the emitter base p–n junction. In this work, the effect the main technological parameters of rapid thermal annealing have on a contact’s characteristics are examined, and the process of obtaining a low-resistance ohmic contact to heterobipolar transistor layers is optimized. Ohmic contacts to the n-layers of heterobipolar nanoheterostructures based on gallium arsenide and produced via layer-by-layer electron-beam deposition of Ge/Au/Ni/Au are considered. The diffusion distribution profiles of doping with Ge impurities are calculated as a function of the time and temperature of rapid thermal annealing, and are examined via scanning electron microscopy. It is found that rapid thermal annealing for 60 s at a temperature of 398°C yields ohmic contacts with low resistance, smooth surface morphology, and the minimum size of the transition layer.

High thermal stability ohmic contacts to nitride semiconductors with refractory metal sidewall diffusion barrier deposited by magnetron sputtering

GaN HEMTs are generally promising candidates for RF and switching power transistors due to their high breakdown strength and the high current density giving a low on-resistance. Low-resistance ohmic contacts are needed to reduce losses and self-heating. Conventional ohmic contacts use Ti and Al with a cap to avoid oxidation of the Al layer. Alternative ohmic metals for use with nitride semiconductors are being sought using Hf or Ta, which can be annealed at lower temperatures. That have been shown, the Au-free low temperature Ta/Al ohmic contacts fabricated with the refractory sidewall diffusion barrier have the lower contact resistance and the better surface morphology after the high temperature annealing. Normally-off p-gate high voltage GaN transistor based on Ta/Al ohmic contacts with the sidewall diffusion barrier have the higher drain-source current, lower gate-source current and higher source-drain breakdown voltage.

AlGaN/GaN High Electron Mobility Transistors on Semi-Insulating Ammono-GaN Substrates with Regrown Ohmic Contacts.

AlGaN/GaN high electron mobility transistors on semi-insulating bulk ammonothermal GaN have been investigated. By application of regrown ohmic contacts, the problem with obtaining low resistance ohmic contacts to low-dislocation high electron mobility transistor (HEMT) structures was solved. The maximum output current was about 1 A/mm and contact resistances was in the range of 0.3–0.6 ·mm. Good microwave performance was obtained due to the absence of parasitic elements such as high access resistance.

Practical Optimization of Highly Sensitive AZO Photoconductor With Circular Electrode Scheme

Highly responsive ZnO-based photoconductors with a circular electrode scheme are introduced in this paper. Some cost-effective samples were fabricated through simple chemical routes and conventional photolithography methods. Al:ZnO thin films with a high density of hole trap states were prepared after several optimizations during the synthesis process. Circular electrodes with low ohmic contact resistances were formed by optimizing the metallization process. Then, the prepared prototypes were analyzed and their specifications were measured. Performance of the devices was also investigated by using a device simulator. The experimental data showed good agreement with the simulation results. Such that the high responsivity of about 1.9 × 104 AW–1 and signal-to-noise ratio of 9.14 × 103 were recorded after optimization of annealing temperature (at 350 °C), under a weak ultraviolet illumination of 268.27 μW⋅cm–2 at 253 nm wavelength.