Low Off-state Current Research Articles

High quality a-InGaZnO and a-ZrAlO deposited at 375 °C by spray pyrolysis for low voltage operation TFTs

We report the high-performance, bottom-gate a-InGaZnO (IGZO) TFT with high-k ZrAlO (ZAO) gate insulator by spray pyrolysis (SP). The a-IGZO/ZAO TFT exhibits the average saturation mobility of 23.12 cm2 V−1 s−1, subthreshold swing of 121 mV dec-1, ION/OFFratio of ∼108 with no hysteresis and low off-state current of ∼10-19A µm−1. In addition, the TFT exhibits good interface quality with less trap density (∼9x1010 cm−2) and conduction band tail state (∼4.3x1018 cm−3) extracted from TCAD fitting. The high-performance is attributed to the formation of uniform and dense a-IGZO and ZAO thin films with low defect density. Therefore, the SP a-IGZO/ZAO TFTs have great potential to be employed in low-cost, low driving voltage TFTs for display application.

Integrated 2D multi-fin field-effect transistors

Vertical semiconducting fins integrated with high-κ oxide dielectrics have been at the centre of the key device architecture that has promoted advanced transistor scaling during the last decades. Single-fin channels based on two-dimensional (2D) semiconductors are expected to offer unique advantages in achieving sub-1 nm fin-width and atomically flat interfaces, resulting in superior performance and potentially high-density integration. However, multi-fin structures integrated with high-κ dielectrics are commonly required to achieve higher electrical performance and integration density. Here we report a ledge-guided epitaxy strategy for growing high-density, mono-oriented 2D Bi2O2Se fin arrays that can be used to fabricate integrated 2D multi-fin field-effect transistors. Aligned substrate steps enabled precise control of both nucleation sites and orientation of 2D fin arrays. Multi-channel 2D fin field-effect transistors based on epitaxially integrated 2D Bi2O2Se/Bi2SeO5 fin-oxide heterostructures were fabricated, exhibiting an on/off current ratio greater than 106, high on-state current, low off-state current, and high durability. 2D multi-fin channel arrays integrated with high-κ oxide dielectrics offer a strategy to improve the device performance and integration density in ultrascaled 2D electronics.

Transistors with ferroelectric ZrXAl1−XOY crystallized by ZnO growth for multi-level memory and neuromorphic computing

Ferroelectric (FE) field-effect transistors are interesting for their non-destructive readout characteristic and energy efficiency but are difficult to integrate on silicon platforms. Here, FE ZrXAl1−XOY (ZAO) is demonstrated by compressive strain in contact with ZnO. The metal-ferroelectric-semiconductor-metal capacitor exhibits a substantial remnant polarization of 15.2 µC cm−2, along with a bowknot-like anti-clockwise hysteresis in the capacitance curves. The FE-ZAO gated ZnO thin-film transistor presents a large memory window (3.84 V), low subthreshold swing (55 mV dec−1), high ION/IOFF ratio (≈108), and low off-state current (≈1 pA). The grazing incidence X-ray diffraction and scanning transmission electron microscopy analyses reveal the ferroelectric rhombohedral phase (space group R3m) in the nanocrystal ZAO, containing an angle of ≈71.7° between the [111] and [11-1] directions with d111-spacing of 3.037 Å and d11-1-spacing of 2.927 Å. Finally, the memory and neuromorphic applications are analyzed by demonstrating multi-level memory and synaptic weight performance with a high learning accuracy of 91.82%.

Highly uniform resistive switching characteristics of KGM resistive memory through air plasma technology

In this study, a highly stable resistive switching behavior was obtained by utilizing konjac glucomannan, a biomaterial, as a dielectric layer through a solution-based process, and the ITO bottom electrode was modified by using an air plasma technique. Electrical results showed that the pretreatment device did not observe significant switching characteristics (∼101). The device, which underwent additional plasma treatment, was recognized for its significant improvements in this area, demonstrating a reduced set voltage (Vset = 0.37 V) with a 6% coefficient of variation, more than 200 consecutive cycles, and up to 90% electrical yield. Moreover, the treated device exhibited a dramatically higher memory window (>104) due to the relatively low off-state current. According to the XPS and UPS analysis, the work function increased from an untreated 4.3 to 5.79 eV as the treatment time increased to 180 s. The conductive filaments, which stemmed from oxygen vacancies, were introduced through plasma treatment to enhance the proportion of oxygen vacancies in the ITO films, thereby creating a stable and consistent filament path. Consequently, the systematic and reproducible resistive switching phenomenon was intensified. The reported results confirmed that the reliability and uniformity in bioelectronic devices can be accomplished through a simple and effective plasma technique. This approach paved the way for alternative applications of these devices.

Floating gate photo-memory devices based on van der Waals heterostructures for neuromorphic image recognition

Two-dimensional (2D) materials with reconfigurable properties show potential in neuromorphic hardware applications. However, most 2D materials-based neuromorphic hardware is volatile, which needs large energy to accomplish perception functions. Here, we report on nonvolatile floating gate photo-memory devices based on ReS2/h-BN/SnS2 van der Waals heterostructures. The devices exhibit a large memory window of ∼60 V, a high program/erase current ratio of ∼107 with excellent retention characteristics, a low off-state current of 7.4 × 10−13 A, and a high detectivity of 1.98 × 1013 cm Hz1/2 W−1, allowing for multi-bit information storage. For the multi-level storage capacity, 27 photo-memory states are obtained by pulsed laser illumination. Moreover, a neuromorphic computing network is also constructed based on the photo-memory devices with a maximum recognition accuracy of up to 90%. This work paves the way for miniaturization and high-density integration of future optoelectronics for neuromorphic hardware applications.

Cascaded Logic Gates Based on High-Performance Ambipolar Dual-Gate WSe2 Thin Film Transistors.

Ambipolar dual-gate transistors based on low-dimensional materials, such as graphene, carbon nanotubes, black phosphorus, and certain transition metal dichalcogenides (TMDs), enable reconfigurable logic circuits with a suppressed off-state current. These circuits achieve the same logical output as complementary metal-oxide semiconductor (CMOS) with fewer transistors and offer greater flexibility in design. The primary challenge lies in the cascadability and power consumption of these logic gates with static CMOS-like connections. In this article, high-performance ambipolar dual-gate transistors based on tungsten diselenide (WSe2) are fabricated. A high on-off ratio of 108 and 106, a low off-state current of 100 to 300 fA, a negligible hysteresis, and an ideal subthreshold swing of 62 and 63 mV/dec are measured in the p- and n-type transport, respectively. We demonstrate cascadable and cascaded logic gates using ambipolar TMD transistors with minimal static power consumption, including inverters, XOR, NAND, NOR, and buffers made by cascaded inverters. A thorough study of both the control gate and the polarity gate behavior is conducted. The noise margin of the logic gates is measured and analyzed. The large noise margin enables the implementation of VT-drop circuits, a type of logic with reduced transistor number and simplified circuit design. Finally, the speed performance of the VT-drop and other circuits built by dual-gate devices is qualitatively analyzed. This work makes advancements in the field of ambipolar dual-gate TMD transistors, showing their potential for low-power, high-speed, and more flexible logic circuits.

High Ion/Ioff ratio 4H-SiC MISFETs with stable operation at 500 °C using SiO2/SiNx/Al2O3 gate stacks

In this work, 4H-SiC lateral metal-insulator-semiconductor field-effect transistors (MISFETs) were demonstrated to operate up to 500 °C with a high on/off current ratio (over 109). A low off-state current of 3.6 × 10−9 mA/mm at 500 °C was obtained in SiC MISFET with a ring structure. The MISFETs with SiO2/SiNx/Al2O3 gate dielectric stack showed minimum subthreshold swings of 155 and 240 mV/dec at room temperature and 500 °C, respectively, indicating good thermal stability of this gate dielectric stack on SiC. An interface trap density of 1.3 × 1011 cm−2 eV−1 at E − EV = 0.2 eV was extracted from the Capacitance–Voltage (CV) measurements at room temperature, which confirms excellent dielectric interface. The electron mobility increases with increasing temperature and reaches 39.4 cm2/V s at 500 °C. These results indicate that SiC MISFETs with triple layer dielectrics and ring structure have a high potential in extreme-temperature electronics.

Multimodal Encapsulation to Selectively Permeate Hydrogen and Engineer Channel Conduction for p-Type SnOx Thin-Film Transistor Applications.

It has been challenging to synthesize p-type SnOx (1 < x < 2) and engineer the electrical properties such as carrier density and mobility due to the narrow processing window and the localized oxygen 2p orbitals near the valence band. Herein, we report on the multifunctional encapsulation of p-SnOx to limit the surface adsorption of oxygen and selectively permeate hydrogen into the p-SnOx channel for thin-film transistor (TFT) applications. Time-of-flight secondary ion mass spectrometry (ToF-SIMS) measurements identified that ultrathin SiO2 as a multifunctional encapsulation layer effectively suppressed the oxygen adsorption on the back channel surface of p-SnOx and selectively diffused hydrogen across the entire thickness of the channel. Encapsulated p-SnOx-based TFTs demonstrated much enhanced channel conductance modulation in response to the gate bias applied, featuring higher on-state current and lower off-state current (on/off ratio > 103), field effect mobility of 3.41 cm2/(V s), and threshold voltages of ∼5-10 V. The fabricated devices show minimal deviations as small as ±6% in the TFT performance parameters, which demonstrates good reproducibility of the fabrication process. The relevance between the TFT performance and the effects of hydrogen permeation is discussed in regard to the intrinsic and extrinsic doping mechanisms. Density functional theory calculations reveal that hydrogen-related impurity complexes are in charge of the enhanced channel conductance with gate biases, which further supports the selective permeation of hydrogen through a thin SiO2 encapsulation.

An Ultra-steep Slope Two-dimensional Strain Effect Transistor.

We introduce a high-performance and ultra-steep slope switch, referred to as strain effect transistor (SET), with a subthreshold swing < 0.68 mV/decade at room temperature for 7 orders of magnitude change in the source-to-drain current based on atomically thin 1T'-MoTe2 as the channel material, piezoelectric lead zirconate titanate (PZT) as the gate dielectric, and nickel (Ni) as the source/drain contact metal. We exploit gate-voltage induced strain transduction in PZT leading to abrupt and reversible cracking of the metal contacts to achieve the abrupt switching. The SET also exhibits a low OFF-state current < 1 pA/μm, a high ON-state current > 1.8 mA/μm at a supply voltage of 1 V, a large current ON/OFF ratio > 1 × 109, and a high transconductance of > 100 μS/μm. The switching delay for the SET was found to be < 5 μs, and no device failure was observed even after 1 million (1 × 106) switching cycles.

Stable reconfiguring, high-density memory and synaptic characteristics in Sn alloyed CsPbI3 perovskite based resistive switching device

In search of efficient data storage devices, the need of the hour demands novel materials that can offer superior speed, low power consumption and reproducibility. Here, we have chosen a halide perovskite material for the development of reconfigurable memory properties. A metal-insulator-metal structure comprising of Au/α-CsPbI3/ITO has been fabricated to realize non-volatile memory characteristics. However, the active cubic phase of CsPbI3 is not stable at room temperature if not shielded properly as found in literature. To minimize the effect of passivation and interface reaction, the CsPbI3 was alloyed with Sn at the Pb-site. The substitution resulted in stable phase of α-CsPbI3 at room temperature due to increase in tolerance factor. Thus, the device with 10 % Sn alloyed perovskite shows reliable and uniform resistive switching behavior with high ON/OFF ratio (>104), low operating voltage (<0.5 V) along with multi-bit operation capability. On the hand, the device with orthorhombic structure, i.e. δ-CsPbI3 failed to demonstrate any significant switching behavior with the similar operating voltages. Such discrepancy in device mechanism could be attributed to the structural dissimilarity between the two phases, where migration of ions/vacancies holds prime role. Finally, the change in device resistance was postulated by valance change mechanism (VCM), which was validated by conducting atomic force microscopy (c-AFM). This switching mechanism and low OFF state current of the device were utilized to emulate synaptic characteristics in the device consuming very low energy and pave the way for the development of next-generation multi-functional electronic devices.

(Digital Presentation) Multimodal Encapsulation of p-SnOx to Engineer the Carrier Density for Thin Film Transistor Applications

It has been challenging to synthesize p-type SnOx (1≤x<2) and engineer the electrical properties such as carrier density and mobility due to the narrow processing window and the localized oxygen 2p orbitals near the valence band.We recently reported on the processing of p-type SnOx and an oxide-based p-n heterostructures, demonstrating high on/off rectification ratio (>103), small turn-on voltage (<0.5 V), and low saturation current (~1×10-10 A)1. In order to further understand the p-type oxide and engineer the properties for various electronic device applications, it is important to identify (or establish) the dominating doping and transport mechanisms. The low dopability in p-type SnOx, of which the causation is also closely related to the narrow processing window, needs to be mitigated so that the electrical properties of the material are to be adequately engineered 2, 3.Herein, we report on the multifunctional encapsulation of p-SnOx to limit the surface adsorption of oxygen and selectively permeate hydrogen into the p-SnOx channel for thin film transistor (TFT) applications. Time-of-flight secondary ion mass spectrometry measurements identified that ultra-thin SiO2 as a multifunctional encapsulation layer effectively suppressed the oxygen adsorption on the back channel surface of p-SnOx and augmented hydrogen density across the entire thickness of the channel. Encapsulated p-SnOx-based TFTs demonstrated much-enhanced channel conductance modulation in response to the gate bias applied, featuring higher on-state current and lower off-state current. The relevance between the TFT performance and the effects of oxygen suppression and hydrogen permeation is discussed in regard to the intrinsic and extrinsic doping mechanisms. These results are supported by density-functional-theory calculations. Acknowledgement This work was supported by the U.S. National Science Foundation (NSF) Award No. ECCS-1931088. S.L. and H.W.S. acknowledge the support from the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 20011028) by KRISS. K.N. was supported by Basic Science Research Program (NRF-2021R11A1A01051246) through the NRF Korea funded by the Ministry of Education. References Lee, D. H.; Park, H.; Clevenger, M.; Kim, H.; Kim, C. S.; Liu, M.; Kim, G.; Song, H. W.; No, K.; Kim, S. Y.; Ko, D.-K.; Lucietto, A.; Park, H.; Lee, S., High-Performance Oxide-Based p–n Heterojunctions Integrating p-SnOx and n-InGaZnO. ACS Applied Materials & Interfaces 2021, 13 (46), 55676-55686.Hautier, G.; Miglio, A.; Ceder, G.; Rignanese, G.-M.; Gonze, X., Identification and design principles of low hole effective mass p-type transparent conducting oxides. Nat Commun 2013, 4.Yim, K.; Youn, Y.; Lee, M.; Yoo, D.; Lee, J.; Cho, S. H.; Han, S., Computational discovery of p-type transparent oxide semiconductors using hydrogen descriptor. npj Computational Materials 2018, 4 (1), 17. Figure 1

Improved DC Performance of Nanotube Junctionless Field-Effect Transistors with Dielectric Pocket Integration

In this paper, a nanotube architecture of Junctionless FET (JLFET) is investigated wherein it is observed that the performance characteristics of JLFET are improved by introducing Dielectric Pockets into the device near the source-channel and channel-drain interfaces by coming up with a novel structure of nanotube junctionless FET (NTJLFET) called as Dielectric Pocket-NTJLFET (DP-NTJLFET). Using TCAD tool, the proposed DP-NTJLFET has been simulated for a channel length of 20 nm in order to consider and show the improvement in various short-channel effects. The inclusion of Dielectric Pockets into the device significantly reduced the OFF-state current, which eventually improved the current switching ratio (∼2600%) for a pocket length and thickness of 4 and 7 nm, respectively. Further, the proposed device exhibits an improved subthreshold swing characteristics and a better measure of DIBL (improved by ∼12%) for DP-NTJLFET as compared to the conventional NTJLFET. As a result of achieving low OFF-state current, the proposed DP-NTJLFET may be found suitable for the future low-power applications.

Anatomy of high-uniform unidirectional volatile switching behavior in SiO2/TiO2-based selection device

Unidirectional volatile switching behavior is a typical resistive switching phenomenon in oxides, which has been proposed as attractive candidates for selection devices for high density memory and neuromorphic systems applications with cross-point arrays. However, the microscopic origin of the underlying mechanism is still unclear due to the lack of direct experimental evidence. Here, a high performance selection device with a low forming voltage, low OFF-state current, high nonlinearity, and excellent uniformity is proposed in SiO2/TiO2 stacked structure. The underlying nature of the unidirectional volatile switching behavior in the Pt/Ag/SiO2/TiO2/Ti selection device is revealed by using scanning electron microscope and energy-dispersive X-ray spectroscopy analysis in planar structure devices, which can be attributed to the unstable conductive filament (CF) consisting of Ag nanoparticles formed in the SiO2 layer, and the Schottky contact formed between the Ag CF and TiO2 interface. This work provides clearly experimental evidence to deepen understanding of themechanism for unidirectional volatile switching behavior, which can provide a guide to further improve the device performances for high density memory and neuromorphic systems applications.

CNTFET Circuit-Based Wide Fan-In Domino Logic for Low Power Applications

Carbon nanotube field effect transistors (CNTFETs) are the best alternative option for the metal oxide semiconductor field effect transistor (MOSFET) in the ultra-deep submicron (ultra-DSM) regime. CNTFET has numerous benefits such as lower off-state current, high current density, low bias potential and better transport property as compared to MOSFET. A rolled graphene sheet-based cylindrical tube is constructed in the channel region of the CNTFET structure. In this paper, an improved domino logic (IDL) configuration is proposed for domino logic circuits to improve the different performance metrics. An extensive comparative simulation analysis is provided for the different performance metrics for different circuits to verify the novelty of the proposed IDL approach. The IDL approach saves the leakage power dissipation by 95.61% and enhances the speed by 87.10% for the 4-bit full adder circuit as compared to the best reported available domino method. The effects of the number of carbon nanotubes (CNTs), temperature, and power supply voltage variations are estimated for leakage power dissipation for the 16-input OR (OR16) gate. The reliability of different performance metrics for different circuit is calculated in terms of uncertainty by running the Monte Carlo simulations for 500 samples. Stanford University’s 32[Formula: see text]nm CNTFET model is applied for circuit simulations.

Enhanced Phase Stability and Carrier Suppression of Ternary Cation-Based Amorphous Oxide Semiconductor Thin Film Transistors

Transparent optoelectronic materials have gained significant attention for application in high performance devices such as next generation displays1-2, photovoltaics3, electrochromic devices4, and sensors5-6. Metal oxide-based semiconductors, specifically, are a promising group of transparent optoelectronic materials, now considered to be the vital building blocks for future device applications due to the unique combined properties of excellent optical transparency (from the visible to near-infrared regime), and high electrical conductivities7-8. Metal oxides have already seen wide implementation in various optoelectronic devices, depending on their electrical conductivity, as transparent electrodes by degenerately-doped oxides such as indium tin oxides (ITO) and doped zinc oxides (ZnO), as semiconducting active layers based on In2O3, ZnO or SnO2, and as insulators (e.g., SiO2, Al2O3, HfO2) for dielectrics or encapsulations.The key pixel driving switches in display technologies, thin film transistors (TFTs), require a vast array of demanding material properties such as high carrier mobilities (usually defined as the “TFT field effect mobility”), low thermal budgets during processing, resilient phase stability, and reliable device performance under high thermal and bias stress conditions. Amorphous oxide semiconductors (AOSs), specifically those based on indium oxides, are receiving unique attention for TFT implementation due to their promisingly high carrier mobilities (> 5-20 cm2/Vs) compared to conventional amorphous Si (<~1 cm2/Vs), low processing temperature requirements (ambient to 200 °C), superior mechanical flexibility to their crystalline counterparts, and large area process-ability. Indium oxide-based binary and ternary cation material systems show tremendous promise for use in next generation displays as these materials exceed the aforementioned material property and fabrication requirements. Unfortunately, undoped In2O3 experiences a rapid onset of microstructural crystallization at very low homologous temperatures (T/Tm<0.19) at 150 °C and struggles to maintain its amorphous phase structure. The inclusion of Zn in In2O3 has revealed a viable and promising binary cation material which specifically addresses the structural instability of undoped In2O3, Indium Zinc Oxide (IZO), as the addition of Zn into In2O3 proves to stabilize the temperature-sensitive amorphous phase of indium oxide. Furthermore, the reported carrier mobility of IZO has shown to be as high as 20-40 cm2/Vs for both Hall and 15-30 cm2/Vs for TFT field effect mobilities. Studies have dug deeper to further unveil the effects of doping of In2O3-basd materials, and the ternary cation system of indium gallium zinc oxides (IGZO) has proven to be even more popular than binary systems as the addition of Ga in IGZO allows for the controllable suppression of channel carrier density during TFT applications (preferred for TFT devices where a low device off-state current is desired). In addition to Ga, more third cation species have been investigated as suitable material candidates such as Hf, Si, and Zr, but the carrier mobilities (~3-10 cm2/Vs) are around 3-10 times lower than that of In2O3 or IZO.Therefore, securing strategies to develop a material system which maintains both high carrier mobility (e.g., >~20 cm2/Vs) and suppresses carrier generation for TFT channel application is of significant importance, and is necessary to expedite the realization of next-generation transparent displays which possess reliable performance, fast switching speed, and, consequently, ultra-high definition resolution. In this study, the ternary cation oxide system of indium aluminum zinc oxide (IAZO) is investigated with varying Al concentration in IAZO thin films. The IAZO thin films were deposited using magnetron co-sputtering at room temperature. The structural, optical, and electrical properties were systematically characterized as a function of Al concentration and compared to baseline IZO samples. The carrier transport characteristics, as well as the dominant mechanisms for carrier density and resistivity and their relation to Al concentration, are discussed. Furthermore, amorphous IAZO-based TFTs were developed to objectively compare and validate device performance and parameters against IZO-based TFTs.The authors gratefully acknowledge the financial supports of the U.S. NSF Award No. ECCS-1931088; the Purdue Research Foundation (Grant No. 60000029); and the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 20011028) by KRISS.References Nomura et al. Nature 2004, 432 (7016), 488-492.Lee et al. Applied Physics Letters 2014, 104 (25), 252103.Fortunato et al. MRS Bull. 2007, 32 (3), 242-247.Maho et al. Journal of The Electrochemical Society 2017, 164, H25-H31.Venkatanarayanan et al. Elsevier: Oxford, 2014; pp 47-101.Zhao et al. The Journal of Physical Chemistry C 2015, 119 (26), 14483-14489.Lewis et al. MRS Bull. 2000, 25 (8), 22-27.Coutts et al. MRS Bull. 2000, 25 (8), 58-65. Figure 1

(Invited) Crystalline Oxide Semiconductor Applicable to Low-Power Consumption Edge AI

An oxide semiconductor field-effect transistor (OSFET) using c-axis-aligned crystalline indium–gallium–zinc oxide (CAAC-IGZO) exhibits extremely low off-state current (Ioff) and can be fabricated at a low process temperature that is 400°C or lower. The features indicate that the CAAC-IGZO FET is suitable for a monolithic stacking process and application to artificial intelligence (AI). This paper shows electric characteristics of the CAAC-IGZO FET and their factors.

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) using plasma deposited BN as gate dielectric

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) were fabricated on Si substrates with a 10 nm boron nitride (BN) layer as a gate dielectric deposited by electron cyclotron resonance microwave plasma chemical vapor deposition. The material characterization of the BN/GaN interface was investigated by X-ray photoelectric spectroscopy (XPS) and UV photoelectron spectroscopy. The BN bandgap from the B1s XPS energy loss is ∼5 eV consistent with sp2 bonding. The MISHEMTs exhibit a low off-state current of 1 × 10−8 mA/mm, a high on/off current ratio of 109, a threshold voltage of −2.76 V, a maximum transconductance of 32 mS/mm at a gate voltage of −2.1 V and a drain voltage of 1 V, a subthreshold swing of 69.1 mV/dec, and an on-resistance of 12.75 Ω·mm. The interface state density (Dit) is estimated to be less than 8.49 × 1011 cm−2 eV−1. Gate leakage current mechanisms were investigated by temperature-dependent current–voltage measurements from 300 K to 500 K. The maximum breakdown electric field is no less than 8.4 MV/cm. Poole–Frenkel emission and Fowler–Nordheim tunneling are indicated as the dominant mechanisms of the gate leakage through the BN gate dielectric at low and high electric fields, respectively.

Study of ZnO/BST interface for thin-film transistor (TFT) applications

This work presents an investigation of ZnO/BST interface for the potential use of (Ba,Sr)TiO3 as a gate–dielectric in ZnO based thin-film transistors (TFTs) for low-voltage operation. A metal-insulator-semiconductor capacitor (MIS-C) structure, which consists of a Pt/BST/ZnO stack, was fabricated on a corning glass substrate. The capacitance-voltage (C-V) characteristic of MIS-C gives the capacitance peak in both forward and backward sweep. This peak behavior of BST is due to its paraelectric nature attributed by changing the direction of a polar molecule over the applied electric field. C-V curve of ZnO/BST MIS-C structure exhibits a counter-clockwise hysteresis of -1.33 V due to the existence of donor-like oxygen vacancies present in BST and ZnO interface. The subthreshold slope of the device was found to be 203 mV/ decade and calculated using the measurement of interface state density (Dit). ZnO/BST interface also exhibits a very low value of leakage current density (3.148 × 10−7 Acm−2). Thus, the use of BST as a gate-dielectric in ZnO TFT has excellent potential, owing to its steep subthreshold slope, which implies fast switching and low off-state current.

Role of ALD Al2O3 Surface Passivation on the Performance of p-Type Cu2O Thin Film Transistors.

High-performance p-type oxide thin film transistors (TFTs) have great potential for many semiconductor applications. However, these devices typically suffer from low hole mobility and high off-state currents. We fabricated p-type TFTs with a phase-pure polycrystalline Cu2O semiconductor channel grown by atomic layer deposition (ALD). The TFT switching characteristics were improved by applying a thin ALD Al2O3 passivation layer on the Cu2O channel, followed by vacuum annealing at 300 °C. Detailed characterization by transmission electron microscopy-energy dispersive X-ray analysis and X-ray photoelectron spectroscopy shows that the surface of Cu2O is reduced following Al2O3 deposition and indicates the formation of a 1-2 nm thick CuAlO2 interfacial layer. This, together with field-effect passivation caused by the high negative fixed charge of the ALD Al2O3, leads to an improvement in the TFT performance by reducing the density of deep trap states as well as by reducing the accumulation of electrons in the semiconducting layer in the device off-state.

Drain Induced Barrier Widening and Reverse Short Channel Effects in Tunneling FETs: Investigation and Analysis

In this paper, using calibrated TCAD simulations, we demonstrate how the performance of a Tunneling FET (TFET) can be improved by using a new phenomenon called drain induced barrier widening (DIBW) at the source-channel junction. Our results indicate that TFETs in which DIBW dominates exhibit a steep subthreshold swing (≈35 mV/dec) and a low OFF-state current ( $\approx 10^{-16}\text{A}/\mu \text{m}$ ) without affecting the ON-state current. We also show that TFETs exhibit a reverse short channel effect due to an increase in the tunneling width at the source-channel junction.