Low Off-state Current Research Articles

A non-Ohmic normally-off GaN monolithic bidirectional switch with MIS field effect schottky tunnel junction

A non-Ohmic normally-off GaN Monolithic bidirectional switch (MBS) with two metal-insulator-semiconductor field-effect schottky tunnel junctions is proposed and investigated by TCAD sentaurus. The MBS exhibits normally-off operation on account of the thick tunnel barrier at schottky-source and schottky-drain electrodes, whose effective thickness is controlled by two insulated gates next to source and drain. A positive gate bias can pull down the conduction band and result in a thin tunnel barrier with high tunneling current, while a zero gate bias brings about a thick barrier effectively suppressing the tunneling current. The simulated results show that the proposed MBS can deliver a low off-state current of 10 μA and a small on-state voltage of 3.55 V at the same time. And compared with the conventional Ohmic-contact MBS, the proposed MBS does not show any degeneration in on-state loss. Moreover, the absence of Au-based Ohmic process and high temperature annealing process enables the proposed MBS with CMOS compatibility and low thermal budget.

Low-Power Display System Enabled by Combining Oxide-Semiconductor and Neural-Network Technologies

Oxide semiconductor field-effect transistors (OSFETs) are characterized by their extremely low off-state current. By fabricating both a display and peripheral large-scale integrated circuits with OSFETs, the components can be driven in a normally off manner, thus enabling a display system with low power consumption. We explore herein the feasibility of a more energy-efficient display system, which is achieved by predicting changes in image data and thus more efficiently controlling the power-gate timing. This is done by using an artificial neural network.

Monolayer optical memory cells based on artificial trap-mediated charge storage and release

Monolayer transition metal dichalcogenides are considered to be promising candidates for flexible and transparent optoelectronics applications due to their direct bandgap and strong light-matter interactions. Although several monolayer-based photodetectors have been demonstrated, single-layered optical memory devices suitable for high-quality image sensing have received little attention. Here we report a concept for monolayer MoS2 optoelectronic memory devices using artificially-structured charge trap layers through the functionalization of the monolayer/dielectric interfaces, leading to localized electronic states that serve as a basis for electrically-induced charge trapping and optically-mediated charge release. Our devices exhibit excellent photo-responsive memory characteristics with a large linear dynamic range of ∼4,700 (73.4 dB) coupled with a low OFF-state current (<4 pA), and a long storage lifetime of over 104 s. In addition, the multi-level detection of up to 8 optical states is successfully demonstrated. These results represent a significant step toward the development of future monolayer optoelectronic memory devices.

Resist-free fabricated carbon nanotube field-effect transistors with high-quality atomic-layer-deposited platinum contacts

Carbon nanotubes are considered as alternative channel material for future transistors, but several challenges exist for reliable fabrication of these devices. In this work, carbon nanotube field-effect transistors (CNTFETs) were fabricated by patterning of Pt contacts using a combination of electron beam induced deposition and area-selective atomic layer deposition (ALD). This bottom-up technique eliminates compatibility issues caused by the use of resist films and lift-off steps. Electrical characterization of a set of 33 CNTFETs reveals that using this direct-write ALD process for Pt patterning yields improved contacts as compared to evaporated Pt, most likely due to improved wettability of the contacts on the carbon nanotube. Moreover, these CNTFETs can be characterized as unipolar p-type transistors with a very low off-state current.

Fully transparent flexible tin-doped zinc oxide thin film transistors fabricated on plastic substrate.

In this work, we have successfully fabricated bottom gate fully transparent tin-doped zinc oxide thin film transistors (TZO TFTs) fabricated on flexible plastic substrate at low temperature by RF magnetron sputtering. The effect of O2/Ar gas flow ratio during channel deposition on the electrical properties of TZO TFTs was investigated, and we found that the O2/Ar gas flow ratio have a great influence on the electrical properties. TZO TFTs on flexible substrate has very nice electrical characteristics with a low off-state current (Ioff) of 3 pA, a high on/off current ratio of 2 × 107, a high saturation mobility (μsat) of 66.7 cm2/V•s, a steep subthreshold slope (SS) of 333 mV/decade and a threshold voltage (Vth) of 1.2 V. Root-Mean-Square (RMS) roughness of TZO thin film is about 0.52 nm. The transmittance of TZO thin film is about 98%. These results highlight that the excellent device performance can be realized in TZO film and TZO TFT can be a promising candidate for flexible displays.

Influence of plasma fluorination on p -type channel tin-oxide thin film transistors

Abstract This paper describes a high-performance p -type tin-oxide (SnO) thin film transistor (TFT) using fluorine plasma treatment on the SnO active channel layer. The influence of fluorine plasma treatment for this p -type SnO TFT device was also investigated. Through tuning the fluorine plasma power treated on the SnO active channel layer at low temperature, the optimal p -type SnO TFT device exhibits a very high on/off current ratio of 9.6 × 10 6 , a field-effect mobility of 2.13 cm 2 V −1 s −1 , a very low subthreshold swing of 106 mV/dec and an extremely low off-state current of 1 pA at a low driven voltage of p -type SnO channel that reduced crystallized channel roughness and passivated oxygen vacancies and interface traps. This high-performance p -type SnO TFT device using fluorine plasma treatment on the active channel shows great promise for future high-resolution and high-speed display applications.

Physical insight of junctionless transistor with simulation study of Strained channel

The article inquest towards junctionless transistor exploiting channel engineering technique with (Si1-xGex). An accurate and deep understanding of the gated resister with demonstration of lower off-state current, improve on-state drain current and transconductance with its conventional counterpart using numerical simulation. The strain is to improve the electron mobility with high electric field and to reduce the scattering rate across the channel. SGOI-JLCT have a great potential for low power switching applications.

Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio.

Concepts of non-volatile memory to replace conventional flash memory have suffered from low material reliability and high off-state current, and the use of a thick, rigid blocking oxide layer in flash memory further restricts vertical scale-up. Here, we report a two-terminal floating gate memory, tunnelling random access memory fabricated by a monolayer MoS2/h-BN/monolayer graphene vertical stack. Our device uses a two-terminal electrode for current flow in the MoS2 channel and simultaneously for charging and discharging the graphene floating gate through the h-BN tunnelling barrier. By effective charge tunnelling through crystalline h-BN layer and storing charges in graphene layer, our memory device demonstrates an ultimately low off-state current of 10−14 A, leading to ultrahigh on/off ratio over 109, about ∼103 times higher than other two-terminal memories. Furthermore, the absence of thick, rigid blocking oxides enables high stretchability (>19%) which is useful for soft electronics.

Reduction of Kink Effect of Poly-Si TFT With Bottom Field Plate by Dispersing Current Density Technique

A new multiple-gate poly-Si thin-film transistor (TFT) with a bottom field plate (FP) is proposed. The FP disperses the high current density away from the top corner of the spacer channel with the highest electric field, leading to an improved kink effect. Moreover, owing to an inversion layer induced by the FP at the bottom region of spacer poly-Si channel, a higher on-state current is achieved. In addition, the electric field near drain area is reduced, leading to a lower off-state current. Overall, the new multiple-gate poly-Si TFT shows improved characteristics as compared with the counterpart without a bottom FP.

Uncoupled mode space approach for analysis of nanoscale strained junctionless double-gate MOSFET

In this paper, we have analyzed the electrical characteristics of Strained Junctionless Double-Gate MOSFET (Strained JL DG MOSFET). A quantum mechanical transport approach based on non-equilibrium Green's function (NEGF) method with the use of uncoupled mode space approach has been employed for this analysis. We have investigated the effects of high-$$\kappa $$ź materials as gate and spacer dielectrics on the device performance. Low OFF-state current, low DIBL, and low subthreshold slope have been obtained with increase in the gate and spacer dielectric constants. The electrical characteristics of strained JL DG MOSFET have also been compared with conventional JL DG MOSFET and Inversion Mode (IM) DG MOSFET. The results indicated that the Strained JL DG MOSFET outperforms the conventional JL and IM DG MOSFETs, yielding higher values of drain current.

64-4:Invited Paper: Printed Metal Oxide Transistors

Compared to conventional amorphous silicon (a-Si) TFTs, amorphous metal oxide TFTs have superior device performance such as higher mobility, better sub-threshold swing, and lower off-state current. Amorphous metal oxide TFTs have an additional advantage on the device uniformity due to the lacks of grain boundary issues in the poly-Si TFTs. Compared with sputtered oxide TFTs, metal oxide TFTs with solution processes have better flexibility and controllability to adjust the composition of chemical solution. Among various solution-based approaches, direct printing is a promising low-cost technique in fabricating TFTs. The printing technique offers several advantages in manufacturing electronics such as a direct writing of materials, reduction of chemical waste, and reproducibility with high-resolution scale, which are not affordable from other solution-based approaches. While many printed OTFTs have been reported, relatively fewer studies, associated with printed metal oxide TFTs, have been pursued. Interests to printed metal oxide TFTs have grown continuously since the first report of a general route towards printed oxide TFTs. A variety of metal oxide materials have been reported as the channel layer of printed metal oxide TFTs. In this report, the development of printed metal oxide TFTs will be discussed including the precursor inks, the precursor conversion process, the types of the applied printers, and fabricated thin film transistor characteristics. Lastly the report will be concluded with a concise summary and future outlook.

Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement

This script features a study of bandgap, gate material work function and gate dielectric engineering for enhancement of DC and Analog/RF performance, reduction in the hot carriers effect (HCEs) and drain induced barrier lowering (DIBL) for better device reliability. In this concern, the use of band gap and gate material work function engineering improves the device performance in terms of the ON-state current and suppressed ambipolar behaviour with maintaining the low OFF-state current. With these advantages, the use of gate material work function engineering imposes restriction on the high frequency performance due to increment in the parasitic capacitances and also introduces the hot carrier effects. Hence, the gate dielectric engineering with bandgap and gate material work function engineering are used in this paper to overcome the cons of the gate material work function engineering by obtaining a superior performance in terms of the current driving capability, ambipolar conduction, HCEs, DIBL and high frequency parameters of the device for ultra-low power applications. Finally, the optimization of length for different work function is performed to get the best out of this.

High-Performance Al–Sn–Zn–O Thin-Film Transistor With a Quasi-Double-Channel Structure

We successfully fabricated high-performance Al–Sn–Zn–O thin-film transistors (ATZO TFTs) with a quasi-double-channel (QDC) structure on glass by radio-frequency magnetron sputtering. The bilayer ATZO films are fabricated with different oxygen partial pressures during the sputtering process. The structure of the top ATZO layer is optimized to improve OFF-state performances. With this QDC structure, the ATZO TFT demonstrates excellent electrical performances, including a low OFF-state current of 840 fA, an ON/OFF current ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.08 \times 10^{9}$ </tex-math></inline-formula> , a steep threshold swing of 0.16 V/decade, a superior saturation mobility of 108.28 cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}\text{V}^{-1}\text{s}^{-1}$ </tex-math></inline-formula> , and a threshold voltage of 2.09 V.

Performance Evaluation of Novel Strain-Engineered Ge-InGaAs Heterojunction Tunnel Field-Effect Transistors

Novel strain-engineered staggered gap Ge/In x Ga1– x As heterojunction tunnel FETs (H-TFETs) are proposed and theoretically evaluated. Modulation of the indium alloy composition at the source–channel heterointerface resulted in $18.6\times $ and $16.9\times $ enhancement in $I_{\mathrm{\scriptscriptstyle ON}}$ for n- and p-channel Ge/In x Ga1– x As H-TFETs, respectively, as compared with strained Ge homojunction TFETs (p+-Ge/i-Ge/n+-Ge). The n-type H-TFETs (p+-Ge/i-In x Ga1– x As/n+-In x Ga1– x As) exhibited superior leakage suppression due to a larger tunneling barrier at the channel–drain interface. Moreover, the p-type H-TFETs (n+-In x Ga1– x As/i-Ge/p+-Ge) demonstrated a significant enhancement in $I_{\mathrm{\scriptscriptstyle ON}}$ due to an unequal shift in the conduction band edge as a result of doping-induced bandgap narrowing. The simulated tensile-strained Ge/In x Ga1– x As H-TFETs show a great promise for ultralow-power switches with high ON-state and low OFF-state current, providing a new path for low-power complimentary TFET logic.

Fabrication of high performance field-effect transistors and practical Schottky contacts using hydrothermal ZnO nanowires

The production of large quantities of single crystalline semiconducting ZnO nanowires (NWs) at low cost can offer practical solutions to realizing several novel electronic/optoelectronic and sensor applications on an industrial scale. The present work demonstrates high-density single crystalline NWs synthesized by a multiple cycle hydrothermal process at ∼100 °C. The high carrier concentration in such ZnO NWs is greatly suppressed by a simple low cost thermal annealing step in ambient air at ∼450 °C. Single ZnO NW FETs incorporating these modified NWs are characterized, revealing strong metal work function-dependent charge transport, unobtainable with as-grown hydrothermal ZnO NWs. Single ZnO NW FETs with Al as source and drain (s/d) contacts show excellent performance metrics, including low off-state currents (fA range), high on/off ratio (105–107), steep subthreshold slope (<600 mV/dec) and excellent field-effect carrier mobility (5–11 cm2/V-s). Modified ZnO NWs with platinum s/d contacts demonstrate excellent Schottky transport characteristics, markedly different from a reference ZnO NW device with Al contacts. This included abrupt reverse bias current–voltage saturation characteristics and positive temperature coefficient (∼0.18 eV to 0.13 eV). This work is envisaged to benefit many areas of hydrothermal ZnO NW research, such as NW FETs, piezoelectric energy recovery, piezotronics and Schottky diodes.

Analysis for Extremely Low Off-State Current in CAAC-IGZO FETs

A field effect transistor (FET) using c-axis aligned crystalline In–Ga–Zn–O (CAAC-IGZO) for an active layer has an extremely low off-state current, which is much lower than an off-state current of a silicon FET. As we measured and analyzed the off-state current, the voltage drop caused by the off-state current in a memory device was found to approach to a stretched exponential function. This is because in the off-state CAAC-IGZO FET, a small number of carriers move discretely and current does not flow uniformly. The low off-state current was also maintained even when its channel length was scaled down to approximately 50 nm.

Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View

This work presents an analysis about the influence of the gate and source/drain underlap length (LUL) on UTBB FDSOI (UltraThin-Body-and-Buried-oxide Fully-Depleted-Silicon-On-Insulator) devices operating in conventional (VB = 0 V), dynamic threshold (DT, VB = VG), and the enhanced DT (eDT, VB = kVG) configurations, focusing on low power applications. It is shown that the underlap devices present a lower off-state current (IOFF at VG = 0 V), lower subthreshold swing (S), lower gate-induced drain leakage (GIDL), higher transconductance over drain current (gm/ID) ratio and higher intrinsic voltage gain (|AV|) due to their longer effective channel length in weak inversion and lower lateral electric field, while the eDT mode presents higher on-state current (ION) with the same IOFF, lower S, higher maximum transconductance (gmmax), lower threshold voltage (VT), higher gm/ID ratio and higher |AV| due to the dynamically reduced threshold voltage and stronger transversal electric field.

Fabrication of dynamic oxide semiconductor random access memory with 3.9 fF storage capacitance and greater than 1 h retention by using c-axis aligned crystalline oxide semiconductor transistor with L of 60 nm

A dynamic oxide semiconductor random access memory (DOSRAM) array that achieves reduction in storage capacitance (Cs) and decrease in refresh rate has been fabricated by using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) transistor (L = 60 nm) with an extremely low off-state current. We have confirmed that this array, composed of cells that include a CAAC-OS transistor with W/L = 40 nm/60 nm using InGaZnO and a 3.9 fF storage capacitor, operates with write and read times of 5 ns. Therefore, DOSRAM can ensure sufficient Cs while maintaining operation speed comparable to that of dynamic random access memory (DRAM). We have found that the read signal voltage of DOSRAM is changed by approximately 30 mV after 1 h at 85 °C. Thus, DOSRAM is a promising replacement for DRAM.

Structural and electrical characteristics of thin film transistor employing an oriented crystalline InGaZnO channel

In this study, we investigate the impact of orientated crystalline InGaZnO (IGZO) thin film transistor. To evaluate interface thermodynamic stability of temperature-sensitive IGZO film, the film-structural stabilities of high- and low-indium-content InGaZnO were studied. With increasing annealing temperature up to 700 °C, the crystallinity becomes more pronounced while device electrical characteristics are further improved. We find that the apparently reduced off-state current can be attributed to the formation of c-axis-orientated crystalline located at the X-ray diffraction peak of . The performance improvements include a very low turn-on voltage close to zero voltage, a small subthreshold swing of 130 mV/dec, and a low off-state current of 2.4 × 10−14 A/µm at a low operating voltage of 4 V.

Correlation of thermal annealing effect, crystallinity and electrical characteristics in c-axis crystallized InGaZnO thin-film transistors

A low off-state current of 1.6×10−14A/μm and a small subthreshold gate swing of 152mV/decade were achieved in a novel thin film transistor using a c-axis crystallized InGaZnO semiconductor that could be obtained at a low substrate temperature range of 150°C. From experimental results, we found that the lowered off-state current is mainly attributed to the formation of rich Ga–O bonds to reduce oxygen vacancies, and the c-axis crystallized structure of IGZO to increase the potential barrier on the source side due to the increase of local trap states at the grain boundary.