Low-noise Transimpedance Amplifier Research Articles

A High Sensitivity CMUT-Based Passive Cavitation Detector for Monitoring Microbubble Dynamics During Focused Ultrasound Interventions.

Tracking and controlling microbubble (MB) dynamics in the human brain through acoustic emission (AE) monitoring during transcranial focused ultrasound (tFUS) therapy are critical for attaining safe and effective treatments. The low-amplitude MB emissions have harmonic and ultra-harmonic components, necessitating a broad bandwidth and low-noise system for monitoring transcranial MB activity. Capacitive micromachined ultrasonic transducers (CMUTs) offer high sensitivity and low noise over a broad bandwidth, especially when they are tightly integrated with electronics, making them a good candidate technology for monitoring the MB activity through human skull. In this study, we designed a 16-channel analog front-end (AFE) electronics with a low-noise transimpedance amplifier (TIA), a band-gap reference circuit, and an output buffer stage. To assess AFE performance and ability to detect MB AE, we combined it with a commercial CMUT array. The integrated system has 12.3 - [Formula: see text] receive sensitivity with 0.085 - [Formula: see text] minimum detectable pressure (MDP) up to 3 MHz for a single element CMUT with 3.78 [Formula: see text] area. Experiments with free MBs in a microfluidic channel demonstrate that our system is able to capture key spectral components of MBs' harmonics when sonicated at clinically relevant frequencies (0.5 MHz) and pressures (250 kPa). Together our results demonstrate that the proposed CMUT system can support the development of novel passive cavitation detectors (PCD) to track MB activity for attaining safe and effective focused ultrasound (FUS) treatments.

500-kHz Bandwidth Feedback for Scanning Ion Conductance Microscopy With Nanoresolution

Scanning ion conductance microscopy (SICM) has been developing rapidly and has been a versatile tool for nanoscale imaging. However, the imaging quality and scanning speed of SICM have been significant restriction factors for its various applications. One of the main reasons is the mutual restriction of bandwidth and noise of the ion current feedback. In this paper, a low-noise two-stage transimpedance amplifier (TIA) with 500 kHz bandwidth was proposed and a low-capacitance pipette was combined to depress the high-frequency ion current noise of SICM's feedback circuit. The effect of pipette capacitance, which is a major cuase of high-frequency noise, was significantly reduced by covering a thin polydimethylsiloxane (PDMS) film on the outer wall of the pipette. Finite element method (FEM) was employed for the first time to simulate the pipette capacitance model. Impedance spectroscopy experiments verified that this method can greatly reduce the pipette capacitance (about 0.7 times). Through the comparative analysis of ion current noise, as well as the scanning experiments of standard silicon material sample and PMDS sample, it was demonstrated that the proposed method has a significant effect in reducing the high frequency noise of ion current measurement. Therefore, our method can provide an avenue to realize high-speed imaging with high positioning accuracy.

Design and fabrication of an amperometric CO gas sensor and a readout circuit using a low-noise transimpedance amplifier to achieve standard analog outputs

This article presents a sensor design method that utilizes two electrodes made of gold and tin oxide, along with a gas concentration detection circuit. The use of an n-type semiconductor with a rutile structure contributes to improved sensitivity, and a sol-gel coating with SnO2 is applied. The sensor includes 20 finger electrodes printed on a ceramic substrate, along with a heater placed on the bottom layer to enable interaction with the external environment. The gas concentration is detected through the use of an amperometric method and an ultra-low noise amplifier. The proposed system incorporates a microcontroller and a low-noise analog interface, delivering standard analog outputs ranging from 0 ∼ 10 V and 4 ∼ 20 mA, proportional to the gas concentration. The experimental results demonstrate a sensitivity of 6nA/ppm within the range of 0 ∼ 470 ppm, with a detection limit of 1 ppm. Key advantages of the proposed circuit include linear response within the specified range, resistance to thermal changes, and cost-effectiveness. Moreover, the sensor exhibits reliable repeatability, with a response time of 27.5 s and a recovery time of 39 s. The front-end circuit's adjustable bandwidth and gain enable precise fine-tuning of the measured CO concentration range.

Low-noise and high-speed trans-impedance amplifier for nanopore sensor.

The small current detection circuit is the core component of the accurate detection of the nanopore sensor. In this paper, a compact, low-noise, and high-speed trans-impedance amplifier is built for the nanopore detection system. The amplifier consists of two amplification stages. The first stage performs low-noise trans-impedance amplification by using ADA4530-1, which is a high-performance FET operational amplifier, and a high-ohm feedback resistor of 1 GΩ. The high pass shelf filter in the second stage recovers the higher frequency above the 3 dB cutoff in the first stage to extend the maximum bandwidth up to 50 kHz. The amplifier shows a low noise below sub-2 pA rms when tuned to have a bandwidth of around 5 kHz. It also guarantees a stable frequency response in the nanopore sensor.

A Fast, Low-Jitter, and Low-Time-Walk Multi-Channel Front-End IC for Diamond and Silicon Radiation Detectors

This paper presents the design and implementation of a radiation-hardened analog front-end (AFE) integrated circuit (IC) developed for interfacing with solid state ionizing radiation detectors, providing accurate amplitude and time-of-arrival measurements. The AFE is designed for use in the Beam Conditions Monitor Prime (BCM’) of the ATLAS experiment at the Large Hadron Collider (LHC). The proposed AFE is comprised of four channels, allowing for re-configuration to operate as either a low-noise high-gain amplifier for beam luminosity measurements, or a high-linearity low-gain amplifier for beam abort functionality. Each of the AFE channels consists of a low noise trans-impedance amplifier (TIA) optimized for minimal jitter and amplitude noise, a second stage differential amplifier, followed by a fully differential Constant Fraction Discriminator (CFD) to provide an amplitude independent time pick-off with a wide dynamic range. The CFD utilizes a new all-pass filter delay topology and high-performance zero-crossing detector to minimize time-walk. The core of each AFE channel occupies an area of 0.06 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 65 nm CMOS technology and consumes 57 mW, including the drivers. The measured AFE chips achieve 1 ns pulse rise time, 130 electron baseline equivalent noise charge (ENC), and <25 ps RMS jitter at 1 fC input charge. To the authors’ best knowledge, this work demonstrates the lowest published time-walk of ±6 ps across 30 dB signal dynamic range. Furthermore, irradiated AFEs are shown to tolerate up to 225 Mrad total ionizing dose with no significant degradation in measured performance characteristics.

Dual-Photodiode Differential Receivers Achieving Double Photodetection Area for Gigabit-Per-Second Optical Wireless Communication

This article presents two dual-photodiode (PD) differential optical receivers that achieve double photodetection area to support gigabit-per-second optical wireless communication (OWC), while maintaining the receiver bandwidth. To enable differential light detection with a single incident light beam, a dual-PD OWC receiver architecture is proposed. In this architecture, two PDs are connected to the receiver complementarily without sacrificing the receiver bandwidth, and meanwhile, remain properly reversely biased. In addition, an adaptive dc photocurrent cancellation (ADPC) circuit is employed to prevent the saturation of the receivers under strong and imbalanced incident light. Based on the proposed architecture, two OWC receivers are implemented, including a proposed receiver and a reference one. In the proposed receiver, a low-noise shunt-feedback transimpedance amplifier (SF-TIA) with differential-pair-based current reuse and cross-coupled resistive feedback is proposed to enhance the sensitivity. In contrast, the reference receiver employs positive capacitive feedback to improve the transimpedance amplifier (TIA) performance. Both receivers have been fabricated with a standard 180 nm CMOS process and have been wire-bonded to two PDs. Experimental results indicate that both receivers can detect optical signals with data rates up to 2 Gb/s, and the proposed receiver architecture has significantly improved the bit error rate (BER) at 1.5 Gb/s from worse than 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-6}$</tex-math> </inline-formula> –10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-9}$</tex-math> </inline-formula> (error-free) with constrained optical power density. Moreover, the proposed receiver achieves an input sensitivity of 3.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{pp}}$</tex-math> </inline-formula> due to the superior performance of the proposed TIA, which outperforms the sensitivity of 10.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{pp}}$</tex-math> </inline-formula> from the reference receiver. Both sensitivities are measured at 1.5 Gb/s for a BER of 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-9}$</tex-math> </inline-formula> (error-free). The power consumption of the proposed and the reference receiver are 24.3 and 19.1 mW, respectively, excluding the output driver.

A low power 0.5–3.0 GHz passive mixer based wideband receiver front-end

A 0.5–3.0 GHz passive mixer based receiver front-end (RFE) is presented. This RFE consists of low noise amplifier, passive mixer, transimpedance amplifier (TIA) and local oscillator signal generator. In order to reduce the power consumption and noise figure, an optimized LNA is proposed in this paper. To further reduce the power consumption, topology of TIA is simplified. The chip is fabricated with SMIC 65 nm technology. At the frequency band of 0.5–3.0 GHz, it achieves a gain of 34 dB and NF of 3.2 dB. The power consumption is 3.8–5.0 mW with core area of 0.06 mm2.

Chip-Level GHz Capable Balanced Quantum Homodyne Receivers

We present a design of balanced homodyne receivers suitable for ultra-low noise quantum applications such as continuous-variable quantum key distribution and quantum random number generation. For best noise and bandwidth performance a die-level low-parasitic photodiode together with a low-noise high-speed transimpedance amplifier are explored together with a planar lightwave circuit splitter chip serving as a photomixer. Bandwidths of 750 MHz and 2.6 GHz were accomplished while maintaining optimum noise performance, as evidenced by very high quantum-to-classical noise ratios of 26.8 and 18.6 dB, respectively. A common-mode rejection ratio of at least 40 dB was achieved for a frequency range of up to 1 GHz. Its application for continuous-variable quantum key distribution was evaluated by means of estimations under a strict untrusted receiver assumption, showing its potential for generating up to 43 Mbit/s secure-key rate over a reach of 10 km, whereas up to 100 Mbit/s could be supported at shorter reaches. Moreover, the high quantum-to-classical clearance values can enable high quality quantum random number generation at Gb/s rates. The multi-purpose operation of the designed balanced receivers for classical communications was examined showing reception sensitivities of −55.8 and −52.6 dBm at 500 Mbit/s and 1 Gbit/s quadrature phase shift keying transmission, respectively, using the 750 MHz receiver. The faster 2.6 GHz receiver enabled 10 Gbit/s duobinary transmission at −14.8 dBm sensitivity.

Two-Channel Detecting Sensor with Signal Cross-Correlation for FTIR Instruments.

Compared to the standard FTIR detection setup, our sensor ensures a higher signal-to-noise ratio (SNR) and lower signal standard deviation by reducing the uncorrelated noise components (e.g., thermal and 1/f noises of the detection module). Its construction is based on two-channel detection modules and a processing unit with implemented cross-correlation signal analyses. Each module was built of LWIR HgCdTe photodiodes and low-noise transimpedance amplifiers. the experiments demonstrated a decrease in a signal standard deviation of about 1.7 times with a 10 dB-improvement in the SNR. this result indicates our sensor's main benefit, especially in registered "weak" and noisy interferograms.

On Noise Modeling of Capacitive Feedback Transimpedance Amplifiers in CMOS

The work reports on the development of a detailed noise current model for a low-noise capacitive feedback transimpedance amplifier (TIA) in CMOS. The proposed TIA circuit implements the programmable-gain using an array of discretely controlled feedback capacitors and resistances in the biasing circuit and is originally designed bearing in mind low-noise requirements for optical time-domain reflectometer (OTDR) applications with the base gain of 10 kΩ at 1 GHz bandwidth and noise levels below 5.0 pA/Hz. The newly developed model for input-referred noise current spectral density complements the previously suggested transimpedance gain model and takes into account both the primary and secondary noise sources so far ignored in the models known in the literature. The proposed noise model consists of five terms and includes the effects caused by biasing components of the input stage and the noise shaping from the source follower. The performance of the developed noise model is evaluated using the post-layout simulation in 0.18 μm CMOS and 0.25 μm BiCMOS technologies, and a close match of the proposed model is demonstrated in the results of the post-layout simulation with the noise level below 1.8 pA/Hz for the base gain configuration in CMOS. A comparison to available noise models from the literature confirms that previously known noise models for this promising TIA architecture omitted important noise components present in practical and physically realizable circuits and, therefore, resulted in underestimating the base noise level by a factor of two to three, while completely ignoring the flicker noise mapping in the low-frequency range.

High Gain, Low Noise and Power Transimpedance Amplifier Based on Second Generation Voltage Conveyor in 65 nm CMOS Technology.

A transimpedance amplifier (TIA) based on a voltage conveyor structure designed for high gain, low noise, low distortion, and low power consumption is presented in this work. Following a second-generation voltage conveyor topology, the current and voltage blocks are a regulated cascode amplifier and a down converter buffer, respectively. The proposed voltage buffer is designed for low distortion and low power consumption, whereas the regulated cascode is designed for low noise and high gain. The resulting TIA was fabricated in 65 nm CMOS technology for logic and mixed-mode designs, using low-threshold voltage transistors and a supply voltage of ±1.2 V. It exhibited a 52 dBΩ transimpedance gain and a 1.1 GHz bandwidth, consuming 55.3 mW using a ±1.2 V supply. Our preamplifier stage, based on a regulated cascode, was designed considering detector capacitance, bonding wire, and packaging capacitance. The voltage buffer was designed for low-power consumption and low distortion. The measured input-referred noise of the TIA was 22 pA/√Hz. The obtained total harmonic distortion of the TIA was close to 5%. In addition, the group delay is constant for the considered bandwidth. Comparisons against published results in terms of area (A), power consumption (P), bandwidth (BW), transimpedance gain (G), and noise (N) are were performed. Both figures of merit FoMs—the ratio √ (G × BW) and P × A—and FoM/N values demostrated the advantages of the proposed approach.

Low-Area Four-Channel Controlled Dielectric Breakdown System Design for Point-of-Care Applications.

In this study, we propose a low-area multi-channel controlled dielectric breakdown (CDB) system that simultaneously produces several nanopore sensors. Conventionally, solid-state nanopores are prepared by etching or drilling openings in a silicon nitride (SiNx) substrate, which is expensive and requires a long processing time. To address these challenges, a CDB technique was introduced and used to fabricate nanopore channels in SiNx membranes. However, the nanopore sensors produced by the CDB result in a severe pore-to-pore diameter variation as a result of different fabrication conditions and processing times. Accordingly, it is indispensable to simultaneously fabricate nanopore sensors in the same environment to reduce the deleterious effects of pore-to-pore variation. In this study, we propose a four-channel CDB system that comprises an amplifier that boosts the command voltage, a 1-to-4 multiplexer, a level shifter, a low-noise transimpedance amplifier and a data acquisition device. To prove our design concept, we used the CDB system to fabricate four nanopore sensors with diameters of <10 nm, and its in vitro performance was verified using λ-DNA samples.

Low-noise large-bandwidth transimpedance amplifier for measuring scanning tunneling shot noise spectra in cryogenic STM and its applications

Shot noise is a powerful tool to study quantum systems. In this work, a design of transimpedance amplifier (TIA) for a cryogenic scanning tunneling microscope (CryoSTM) is proposed to meet the requirements of the shot noise measurements for quantum systems. In the TIA, the preamplifier is made of the low-noise low-power cryogenic high electron mobility transistors. With the high transimpedance gain of 1 GΩ, the bandwidth of the proposed TIA is larger than 300 kHz. In the CryoSTM, the TIA with the tip-sample component is called as CryoSTM-TIA. The bandwidth of the proposed CryoSTM-TIA is still larger than 300 kHz. Its equivalent input noise current power spectral density is less than 30(fA)2/Hz at 100 kHz. It is detailed, for quantum systems, by using the CryoSTM-TIA, how to measure scanning tunneling current spectra, scanning tunneling differential conductance spectra, and scanning tunneling noise current power spectra, in atomic scale, and then extract their scanning tunneling shot noise spectra. Thus, it is possible to study novel quantum phenomena in various quantum systems by measuring shot noise with the CryoSTM-TIA, such as the Andreev reflection in atomic scale, the Kondo effect in a single molecular magnet, and the existence of Majorana bound states, etc.

A Low-Noise and High-Accuracy Transimpedance Amplifier Exploiting Power-on-Calibration Technique for LiDAR

A low-noise and high-accuracy transimpedance amplifier (TIA) for light detection and ranging (LiDAR) system is proposed in this article. A power-on-calibration (POC) technique is proposed to improve the transimpedance gain accuracy of single-channel TIA and eliminate the transimpedance mismatch of multichannel TIAs. The noise canceling technique is adopted to improve the circuit sensitivity. Implemented and fabricated in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> standard CMOS technology, the whole circuit consumes 39.6 mW with a 3.3-V supply, where the TIA core circuit and output buffer consume 29.7 and 9.9 mW, respectively. The measured transimpedance gain and bandwidth of the TIA are 86 dB<inline-formula> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> and 240 MHz, respectively. The achieved input-referred noise current is 3.1 pA/<inline-formula> <tex-math notation="LaTeX">$\sqrt {\mathrm {Hz}} $ </tex-math></inline-formula>. A linear dynamic range of 66 dB has been obtained with a minimum detectable signal (MDS) of 500 nA [signal-to-noise ratio (SNR) &#x003D; 10] and an output-amplitude error less than 20&#x0025;. In addition, the measured small-signal gain error is reduced from &#x00B1;40&#x0025; to less than &#x00B1;5&#x0025; due to the proposed POC technique.

A Low-Noise High-Gain Broadband Transformer-Based Inverter-Based Transimpedance Amplifier

In this paper, a transformer-based bandwidth (BW) extension technique is employed to improve the BW, noise, and silicon area of inverter-based transimpedance amplifiers (TIAs) even when they use inductive peaking. A TIA based on the proposed technique, designed and laid out in a 16-nm FinFET process, demonstrates a 36% increased in BW, a 19% reduction in input-referred noise, and a 57% reduction in silicon area compared to the conventional TIA with inductive peaking. In the proposed TIA architecture, inclusion of a transformer in the forward path compensates partially for the parasitic capacitances of the inverter and relaxes the transimpedance limit of the conventional TIA. The proposed technique also lowers the input-referred current noise spectrum of the TIA. Post-layout in companion with electromagnetic (EM) simulations and statistical analysis are employed to verify the effectiveness of the proposed architecture. Simulation results show that the TIA achieves a transimpedance gain of 58 dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> , a BW of 17.4 GHz, an input-referred noise of 17.4 pA/sqrt (Hz), and an eye-opening of 20 mV at a data-rate of 64 Gbps PAM4 and at a bit-error-rate (BER) of 1E-6. The whole TIA chain is expected to consume 19 mW and occupies an active area of 0.023 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Open-source lab hardware: Low noise adjustable two-stage gain transimpedance amplifier with DC offset for low-light detection

An open-source, low noise, low cost, and tunable transimpedance amplifier is presented. The compact circuit board requires few parts and costs less than $65 USD. The transimpedance amplifier is intended for low-light detection and operation with commercial photomultiplier tubes (PMTs). It provides a much more cost-effective acquisition tool compared to competitive products on the market. The system can easily be assembled and modified to suit specific current sensing applications. The amplifier features two variable gains and an adjustable DC offset to optimize dynamic range and suppress potential bias in the signal. With a target bandwidth of DC to 2 Hz and fourth-order Sallen-Key cutoff, the design is ideally suited for various applications in the field of analytical chemistry and biology, such as laser-induced fluorescence detection or chemiluminescence measurements.

A design methodology for programmable-gain low-noise TIA in CMOS

Abstract The work reports on the design of an area-efficient inductor-less low-noise CMOS transimpedance amplifier suitable for entry-level optical time-domain reflectometers. The work suggests a novel approach for implementing a programmable-gain in capacitive feedback TIA with an independent adjustment of the low- and high-frequency behavior using the input stage biasing impedance and one of the feedback capacitors. The approach addresses a typical noise problem of fast feed-forward or resistive feedback topologies while alleviating the trade-off of the key TIA performance indicators. A more accurate amplifier model is proposed which takes into account the effects due to capacitive isolation and both biasing circuits. Further modifications to the reference design are suggested including the PMOS-based implementation of the biasing circuit to address the voltage headroom issue. The circuit was implemented using a standard 180 nm CMOS process and operates from 1.8 V supply with the drawn current of 11.7 mA.

A low noise transimpedance amplifier for optical receiver.

In this paper, a regulated cascode (RGC) structure and a shunt-feedback transimpedance amplifier are cascaded. By analyzing the average input-referred noise current, this paper used the method of adjusting the metal-oxide-semiconductor size and increasing the transimpedance gain to optimize the circuit noise characteristics without introducing redundant structures and noise sources. The measured results demonstrated that when the photodetector capacitance is 300 pF and the supply voltage is 1.8V, the fabricated transimpedance amplifier has a transimpedance gain of 59.5 dBΩ and a -3 dB bandwidth of 4GHz. Simultaneously, the average input-referred noise current spectral density is less than 7 pA/√Hz, and the data rate is as high as 5 Gb/s. The circuit takes advantage of the traditional shunt-feedback transimpedance amplifier and introduces a RGC structure between it and the input terminal as a current buffer structure. A π-type matching network was formed by adding an inductor between the shunt-feedback amplifier and the introduced RGC. All these structures can effectively improve the gain-bandwidth product of the designed amplifier.

Analysis and Design of a Low Noise Shunt-Shunt CMOS Transimpedance Amplifier for 10 Gbps Optoelectronic Receivers

This article presents a complete design flow of a low noise transimpedance amplifier for 10 Gbps optoelectronic receivers. The proposed topology is based on the shunt-shunt structure with negative feedback. A set of equations was deduced from the frequency analysis and noise analysis. An optimization algorithm is proposed in order to maximize the bandwidth and improve the noise performance simultaneously. Experimental results shown a 51 dBΩ transimpedance gain, a 10.54 Ghz bandwidth and an input referred current noise equal to 6.8, the lowest one between other state-of-art designs. The circuit was manufactured in 130 nm RF CMOS technology.

A 32GHz 68dBΩ Low-Noise and Balance Operation Transimpedance Amplifier in 130nm SiGe BiCMOS for Optical Receivers

A 32GHz 68dBΩ Low-Noise and Balance Operation Transimpedance Amplifier in 130nm SiGe BiCMOS for Optical Receivers