Low-noise Transconductance Amplifier Research Articles

IIP2-Calibration-Free Receiver Front End With Notch-Filtered Low-Noise Transconductance Amplifier for 5G New Radio Cellular Applications

IIP2-Calibration-Free Receiver Front End With Notch-Filtered Low-Noise Transconductance Amplifier for 5G New Radio Cellular Applications

An Ultra-Low-Voltage 2.4-GHz Flicker-Noise-Free RF Receiver Front End Based on Switched-Capacitor Hybrid TIA With 4.5-dB NF and 11.5-dBm OIP3

In this article, an ultra-low-voltage 2.4-GHz radio frequency (RF) receiver front-end architecture targeting the removal of output flicker noise is presented, making it possible to use zero-IF topology for narrow-band communication standards. The trans-impedance amplifier (TIA) is built on the proposed hybrid operational trans-conductance amplifier (OTA) with a switched-capacitor (SC) amplifier as the first gain stage and an active primary–secondary amplifier as the second gain stage, achieving an imperceptible flicker-noise corner frequency. With the SC gain stage, the interstage common-mode voltage can be set to 0 V, which reduces the minimum supply voltage to 0.5 V. As another benefit, dc offset compensation (DCOC) is performed inherently in the interstage sampling and coupling process. Fabricated in 28-nm RF CMOS process, the front-end prototype, including an on-chip matching inductor, occupies a die area of 0.8 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . Operating in the Industrial Scientific Medical (ISM) frequency band of 2.4 GHz with 1-MHz IF bandwidth, the front end provides a 36–40-dB conversion gain, an 11.5-dBm OIP3, and a flicker-noise corner frequency less than 10 kHz with the supply voltage ranging from 0.5 to 0.6 V. The RF impedance matching network provides passive voltage gain before the low-noise trans-conductance amplifier (LNTA), achieving a 4.5-dB noise figure (NF) with 0.8-mA biasing current in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_m$</tex-math> </inline-formula> stage. With the ultra-low supply voltage and the passive IF gain stage, the power consumption of the proposed front end is only 610 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> W under a 0.53-V supply voltage.

Quad-channel broadband compact multi-antenna GNSS down-converter for high-reliability navigation

Abstract A high-reliability broadband high-linearity down-converter for multi-antenna global navigation satellite system (GNSS) receiver is presented in this paper. Based on direction-of-arrival estimation, the multi-antenna GNSS receiver can separate the GNSS signals from the interfering signals and suppress harmful broadband radio frequency interferences. To drive the off-chip 50 Ω resistive load and meet the stringent requirements of linearity, a quad-channel down-converter with a broadband common-gate low-noise transconductance amplifier, current-driven passive mixer and novel bridge mode transimpedance driving amplifier have been proposed to contruct the multi-antenna receiver. The operating frequency of this down-converter is from 1.15 to 1.65 GHz, covering all bands for global positioning system (GPS), Beidou navigation satellite system (BDS), global navigation satellite system (GLONASS) and Galileo. The measured results show that the proposed quad-channel down-converter achieves +38 dBm output 3rd order intercept point (OIP3) and +17 dBm OP1dB (output-referred 1 dB compression point), 9.5 dB to 12.9 dB noise figure (NF) across the variable gain of 10 dB to 27 dB and approximately 47 dB channel isolation.

Wideband Cascaded and Stacked Receiver Front-Ends Employing an Improved Clock-Strategy Technique

A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The cascaded receiver includes an inverter-based low-noise transconductance amplifier (LNTA) using a feed-forward technique to enhance the noise performance; a passive mixer; and an inverter-based transimpedance amplifier (TIA). The stacked receiver architecture is used to reduce the power consumption by sharing the current between the LNTA and the TIA from a single supply. It utilizes a wideband LNTA with a capacitor cross-coupled (CCC) common-gate (CG) topology, a passive mixer to convert the RF current to an IF current, an active inductor (AI) and a 1/f noise-cancellation (NC) technique to improve the noise performance, and a TIA to convert the IF current to an IF voltage at the output. Both cascaded and stacked receivers are simulated in 22 nm CMOS technology. The cascaded receiver achieves a conversion-gain from 26 dB to 36 dB, a double-sideband noise-figure (NFDSB) from 1.4 dB to 3.9 dB, S11&lt;−10 dB and an IIP3 from −7.5 dBm to −10.5 dBm, over the RF operating band from 0.4 GHz to 12 GHz. The stacked receiver achieves a conversion-gain from 34.5 dB to 36 dB, a NFDSB from 4.6 dB to 6.2 dB, S11&lt;−10 dB, and an IIP3 from −21 dBm to −17.5 dBm, over the RF operating band from 2.2 GHz to 3.2 GHz. The cascaded receiver consumes 11 m from a 1 V supply voltage, while the stacked receiver consumes 2.4 m from a 1.2 V supply voltage.

A Reconfigurable RF Filter With 1%–40% Fractional Bandwidth for 5G FR1 Receivers

This paper presents a radio frequency front-end (RFFE) for 5G New Radio (NR) receivers operating in Frequency Range 1 (FR1). The core of this RFFE is a synthetic fourth-order Q-enhanced RF filter employing gm-boosting, noise-cancelling, capacitive cross-coupling, and forward body-biasing techniques to achieve 1.7 GHz to 6.4 GHz operating range and 1 adjustable fractional bandwidth (FBW). The function of the filter is based on subtracting out-of-phase signals in the passband and in-phase signals in the stopband. Two Q-enhanced LC resonators are utilized for outphasing. The filter is preceded by a low-noise transconductance amplifier, and it is followed by a programmable gain amplifier and a differential buffer stage for the measurement purposes and gain equalization. The experimental results demonstrate that the voltage gain is tunable between 18 and 47 dB with 0.2 dB steps, which leads to an equalized output power in all the filter configurations. Fabricated in 22 nm Fully Depleted Silicon on Insulator (FD-SOI) technology, the RFFE achieves 4.6 dB NF, -14 dBm IB-IIP3, and 26 dBm IB-IIP2 at 4 GHz. Notably, the fourth-order steep roll-off provides 22 dBm OOB-IIP3 at 2WBW frequency offset. The entire RFFE draws 22-45 mA from a 1 V supply and the filter core occupies 0.11 mm2 chip area.

A linearity enhancement technique for low-noise transconductance amplifiers in SAW-less receivers

A new linearization technique for the transconductance of MOS transistors has been proposed. In the presented method a new composite transistor has been proposed. Moreover, composite transistors with different operating points are connected in parallel to boost the transconductance and cancel the distortion of the overall structure. The superiority of the proposed technique over the previously reported methods is that it also improves the linearity for high-power input signals. A detailed analysis has been given to prove the effectiveness of the newly proposed technique. In order to verify the analysis, a Low-Noise Transconductance Amplifier has been designed exploiting the presented approach and the extensive post-layout simulation results demonstrate at least 26 dB and 7 dB improvements in IIP3 and 1-dB compression point, respectively.

A Comparison of Off-Chip Differential and LC Input Matching Baluns in a Wideband and Low-Power RF-to-BB Current-Reuse Receiver Front-End

A wideband and low-power RF-to-baseband (BB) current-reuse receiver (CRR) front-end is proposed, and its performance is verified using two matching networks, one with an LC balun and on-chip biasing inductor, CRR1, and another with a differential balun and without on-chip biasing inductor, CRR2, requiring less area. The transimpedance amplifier (TIA) and low-noise transconductance amplifier (LNTA) share the bias current from a single supply to reduce power consumption. It employs both an active-inductor (AI) and a 1/f noise-cancellation technique to improve the NF and RF bandwidth performance. A passive mixer is utilized for RF to BB conversion, which does not require any DC power and voltage headroom. Both CRR1 and CRR2 are fabricated in TSMC 130 nm CMOS technology on a single die and packaged using a QFN48. CRR1 occupies an active area of 0.54 mm2. From 1 to 1.7 GHz, it achieves a conversion gain of 41.5 dB, a double-sideband (DSB) NF of 6.5 dB, S11&lt;−10 dB, and an IIP3 of −28.2 dBm, while the local-oscillator (LO) frequency is at 1.3 GHz. CRR2 occupies an active area of 0.025 mm2. From 0.2 to 1 GHz, it achieves an average conversion gain of 37 dB, an average DSB NF of 8 dB, and an IIP3 of −21.5 dBm while the LO frequency is at 0.7 GHz. Both CRR1 and CRR2 consume 1.66 mA from a 1.2 V supply voltage.

A Design Methodology for Wideband Current-Reuse Receiver Front-Ends Aimed at Low-Power Applications

This work gives a design perspective on low-power and wideband RF-to-Baseband current-reuse receivers (CRR). The proposed CRR architecture design shares a single supply and biasing current among both LNTA and baseband circuits to reduce power consumption. The work discusses topology selection and a suitable design procedure of the low noise transconductance amplifier (LNTA), down-conversion passive-mixer, active-inductor (AI) and TIA circuits. Layout considerations are also discussed. The receiver was simulated in 130 nm CMOS technology and occupies an active area of 0.025 mm2. It achieves a wideband input matching of less than −10 dB from 0.8 GHz to 3.4 GHz. A conversion-gain of 39.5 dB, IIP3 of −28 dBm and a double-sideband (DSB) NF of 5.6 dB is simulated at a local-oscillator (LO) frequency of 2.4 GHz and an intermediate frequency (IF) of 10 MHz, while consuming 1.92 mA from a 1.2 V supply.

A Wideband Low-Power RF-to-BB Current-Reuse Receiver Using an Active Inductor and 1 /f Noise-Cancellation for L-Band Applications

A low-power and wideband RF-to-baseband (BB) current-reuse receiver (CRR) front-end utilizing both a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1/f$ </tex-math></inline-formula> noise cancellation (NC) technique and an active inductor (AI) is proposed tuned to operate from 1 GHz to 1.7 GHz for L-Band applications, including those that require high modulation bandwidths. The CRR front-end employs a single supply and shares the bias current of the low noise transconductance amplifier (LNTA) with the BB circuits to reduce the power consumption. To minimize the losses of the radio frequency (RF) signal right before down-conversion, a high impedance AI circuit isolates the mixer input from the CRR output node. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1/f$ </tex-math></inline-formula> NC circuit suppresses the low frequency noise of the LNTA that leaks to the output. A common-gate LNTA with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {g_{m}}$ </tex-math></inline-formula> -boosting, along with a single-to-differential LC-balun are used to enhance the input matching, conversion gain and noise figure (NF). The proposed receiver is fabricated in a TSMC 130 nm CMOS process and occupies an active area of 0.54mm2. The input matching (S11) is below −10 dB from 1 GHz to 1.7 GHz. At a local-oscilator (LO) frequency of 1.3 GHz, intermediate-frequency (IF) of 10 MHz and default current settings, the CRR achieves a conversion gain of 41.5 dB, a double-sideband (DSB) NF of 6.5 dB, and an IIP3 of −28.2 dBm while consuming 1.66 mA from a 1.2 V supply.

A 2.4 GHz 87 μW low-noise amplifier in 65 nm CMOS for IoT applications

As the Bluetooth devices for the internet of things require extremely low-power dissipation to maintain longer battery life, a low-noise amplifier (LNA) as the main power-consuming part in the circuit needs more current-efficient topologies on power saving. This paper proposes a low-noise transconductance amplifier that combines the techniques of passive impendence transformation, [Formula: see text]-boosting technique, and current reuse, leading to a low power under the 1.2 V power supply. The transformer-based [Formula: see text]-boosted structure is applied in the four-transistor-stacked current-reuse topology leading to a [Formula: see text] power saving. The proposed LNA simulated in 65 nm CMOS shows the NF of 3.3 dB and the IIP3 of −8 dBm, respectively, while dissipating 87 [Formula: see text]W dc power. Compared to the previous low-power LNA, this design has fairly low-power consumption and low NF while other performance metrics remain competitive.

A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs Architecture

A modified noise/nonlinearity cancellation low-noise transconductance amplifier (LNTA) based on an inductively degenerated common-source stage is proposed to improve linearity. The linearity of the proposed LNTA is analyzed using the Volterra series yielding closed-form equations for the third-order input intercept point (IIP3) that shows excellent matching with the simulation results. The derived equations for noise figure (NF) and IIP3 are simple enough to be used for design optimization. Calculations and simulation results show that the proposed LNTA is more linear than a conventional one, while NF approximately remains unchanged. Another feature of the proposed noise-canceling LNTA is that no additional baseband recombination stage is needed, leading to reduced complexity in the receiver baseband stage. The NF and out-of-band (OOB) IIP3 of the receiver is about 3.3 dB and more than 20 dBm, respectively. The receiver consumes 10.5 mA from 1.8-V supply voltage. The current consumption of the LO divider is 6.5 mA from a dedicated 1-V supply voltage.

A 0.7-V Sub-mW Type-II Phase-Tracking Bluetooth Low Energy Receiver in 28-nm CMOS

We present an architecture of a Bluetooth low energy (BLE)-compliant receiver which, for the first time ever, breaks the 1mW barrier of power consumption. It is based on a type-II phase-tracking loop and addresses the mutual magnetic coupling between on-chip inductors of a digitally controller oscillator (DCO) and low-noise transconductance amplifier (LNTA), which causes RX performance degradation in the prior-art implementations. An inverter-based inductor-free LNTA is employed instead. The resulting adjacent channel rejection (ACR) improves by 1.5/2.5dB at 2/3MHz offset. By further leveraging current-reuse and switched-capacitor circuitry, this RX achieves the best-in-class FoM of 183.2dB with sensitivity of -93.2dBm. Thanks to the single-channel topology, the proposed RX occupies tiny area of 0.48mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 28-nm CMOS.

A 4.8-dB NF, 440-μW Bluetooth Receiver Front-End With a Cascode Noise Canceling LNTA

An ultralow power (ULP) low-noise receiver front-end for the BLE application is presented in this letter. The tradeoff between noise and power consumption is mitigated by employing a transformer-based passive $g_{m}$ -boosting common-gate low noise transconductance amplifier (LNTA). Local-positive feedback (LPF) and feedforward (FF) noise cancellation techniques are combined in the LNTA to further lower noise. After the passive mixer, a TIA implements complex filtering with a moderate conversion gain. The receiver front-end, fabricated in TSMC 28-nm process, consumes only $440~\mu \text{W}$ under 0.9-V supply with a minimum noise figure of 4.8 dB.

A wideband receiver front-end with low noise and high linearity by exploiting reconfigurable dual paths in 180 nm CMOS

In this paper, a wideband receiver front-end including the flexible reconfigurable main and auxiliary paths is proposed. Therein, the main path has the low-noise advantage thanks to the low-noise transconductance amplifier (LNTA) preceding the mixer and baseband. Meanwhile, by utilizing a mixer-first structure, the auxiliary path renders a high in-band and out-of-band linearity. Furthermore, an inductor resonance structure is also designed to mitigate the baseband noise crosstalk issue which is disclosed by a charging/discharging mechanism via the tail capacitance of passive mixers. Both of the receiving paths have shared a common baseband circuit while loading a commonly-shared 25% duty-cycle LO source generator. Simulation results by a 180 nm CMOS have demonstrated that the main path provides a low noise figure (NF) of 2.7 dB, while the auxiliary path obtains the in-band and out-of-band IIP3 of 9.2 and 21 dBm under typical LO excitation frequency of [Formula: see text] GHz. The power consumption of the main path of the dual-path front-end is 57 mW and that of the auxiliary path is 26 mW under a supply voltage of 1.8 V.

A Baseband-Matching-Resistor Noise-Canceling Receiver With a Three-Stage Inverter-Only OpAmp for High In-Band IIP3 and Wide IF Applications

In this article, we propose a baseband noise-canceling receiver architecture to increase in-band linearity. A key feature of the architecture is that all active circuits are in baseband, including the low-noise transconductance amplifier (LNTA). The LNTA operating at baseband frequencies allows the use of feedback to increase the linearity. This article analyzes a tradeoff that exists between in-band linearity and noise in mixer-first receivers and shows how the proposed architecture breaks such tradeoff. The receiver targets high IF bandwidths, enabled by a transimpedance amplifier (TIA) composed of an OpAmp using only inverters. This article describes the stabilization mechanism of this OpAmp with a unity-gain bandwidth (UGB) of 7.6 GHz. The receiver is fabricated in 22-nm FDSOI CMOS. The measured results show an in-band IIP3 of > 9 dBm for an IF bandwidth of 175 MHz with sub-5-dB noise figure (NF) across 1-6-GHz local oscillator (LO) frequencies.

2.4 GHz BLE Receiver With Power-Efficient Quadrature RF-to-Baseband-Current-Reuse Architecture for Low-Power IoT Applications

In this paper, a 2.4 GHz Bluetooth low energy receiver employing a power-efficient quadrature RF-to-baseband-current-reuse architecture is presented for low-power low-voltage internet of things applications. The proposed quadrature RF-to-baseband-current-reuse RF front-end consists of a low-noise transconductance amplifier, an active-type polyphase filter-based quadrature generator, transimpedance amplifiers, and double-balanced current-mode passive mixers on a single dc current path. An input matching network is used to perform power-constrained simultaneous noise and input power matching and 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f$ </tex-math></inline-formula> noise reduction in the RF and baseband domains, respectively. The quadrature RF signals are provided to the single-quadrature mixers through an embedded active-type polyphase filter-based quadrature generator. The implemented Bluetooth low energy receiver is composed of the RF-to-baseband-current-reuse RF front-end, IF amplifiers, two-stage passive- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> polyphase filter, and fifth-order Chebyshev-II <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-C</i> filters. The proposed design was fabricated using a 65-nm CMOS process and characterized primarily in the Bluetooth low energy operating frequency bands. The active die area of the implemented receiver was 0.85 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the receiver drew a bias current of 1.41 mA from a nominal supply voltage of 0.8 V. The Bluetooth low energy receiver achieved a noise figure of 13.2 dB, conversion gain of 42 dB, image rejection ratio of more than 30 dB, and input-referred third-order intercept point of −25 dBm.

Energy Efficiency Analysis of MIMO Wideband RF Front-End Receivers.

Energy-efficiency is crucial for modern radio-frequency (RF) receivers dedicated to Internet of Things applications. Energy-efficiency enhancements could be achieved by lowering the power consumption of integrated circuits, using antenna diversity or even with an association of both strategies. This paper compares two wideband RF front-end architectures, based on conventional low-noise amplifiers (LNA) and low-noise transconductance amplifiers (LNTA) with N-path filters, operating with three transmission schemes: single antenna, antenna selection and singular value decomposition beamforming. Our results show that the energy-efficiency behavior varies depending on the required communication link conditions, distance between nodes and metrics from the front-end receivers. For short-range scenarios, LNA presents the best performance in terms of energy-efficiency mainly due to its very low power consumption. With the increasing of the communication distance, the very low noise figure provided by N-path LNTA-based architectures outperforms the power consumption issue, yielding higher energy-efficiency for all transmission schemes. In addition, the selected front-end architecture depends on the number of active antennas at the receiver. Hence, we can observe that low noise figure is more important with a few active antennas at the receiver, while low power consumption becomes more important when the number of active RF chains at the receiver increases.

2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter

High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2 × compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal-oxide-semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It consumes 370 μW from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has -7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a -22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.

A Wideband Differential Linear Low-Noise Transconductance Amplifier With Active-Combiner Feedback in Complementary MGTR Configurations

A wideband differential linear low-noise transconductance amplifier (LNTA) is proposed for SAW-less applications. An active combiner provides a dual-loop feedback for wideband matching with power efficiency. Operating as an auxiliary common source (CS) stage, complementary multi-gated transistor (MGTR) configurations are employed to compensate for the second- and third-order nonlinearity of the main CS stage, improving small-signal linearity. Large-signal linearity is also enhanced due to Class AB configurations. Additionally, the push-pull operation of the main CS stage and the auxiliary CS stage preserves good large-signal input matching performance. Implemented in a 0.18-μm CMOS process, the measured LNTA chip provides a minimum noise figure (NF) of 2.5 dB, and a maximum transconductance value of 76.7 mS from 0.1 to 3.1 GHz. On average, an input 1-dB compression point (IP1 dB) of 2.3 dBm and an input third-order intercept point (IIP3) of 17.8 dBm are obtained, respectively. The blocker NF is 4.0 dB under a 0 dBm blocker injection while the S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> <; -10 dB is maintained even with the blocker input of -3.1 dBm. The LNTA core only draws 13.3 mA from a 1.8 V supply.

A 0.5-V BLE Transceiver With a 1.9-mW RX Achieving −96.4-dBm Sensitivity and −27-dBm Tolerance for Intermodulation From Interferers at 6- and 12-MHz Offsets

This article presents a 0.5-V RF transceiver fully compliant with Bluetooth low energy (BLE) standards. The receiver (RX) fabricated in a 22-nm fully depleted silicon on insulator (FD-SOI) process achieves a sensitivity of -96.4 dBm, an intermodulation tolerance of -27 dBm for interferers at 6- and 12-MHz offsets, while consuming 1.9 mW. An RX-chain with a gain-programmable low-noise transconductance amplifier (LNTA) provides good linearity over a wide input power range. The LNTA changes amplifier topology according to the gain setting. It achieves a gain range of 41 dB and the IIP3 of -13 dBm at maximum gain. The proposed asynchronous SAR-ADC-based time-to-digital converter (TDC) for the all-digital phase-locked loop (ADPLL) is suitable for low-voltage operation and low-power consumption. It achieves a differential nonlinearity (DNL) of ±0.62 LSB and an integral nonlinearity (INL) of ±0.63 LSB.