Low Noise Enhancement Research Articles

Compact thermal noise model for enhancement mode N‐polar GaN MOS‐HEMT including 2DEG density solution with two sub‐bands

A 135 nm gate length-based low noise enhancement mode N-polar double deck T-shaped gate Gallium Nitride (GaN) Metal Oxide Semiconductor (MOS)-high electron mobility transistor with double insulating layer of high- k dielectrics ZrO 2 /HfO 2 is proposed. The device exhibits maximum transconductance of 0.55 S/mm, maximum drain current density of 1.4 A/mm and minimum noise figure (NF min ) of 0.72 dB at 20 GHz. A compact model for Two Dimensional Electron Gas (2DEG) density is developed by explicit solution of surface potential and Fermi level by considering first two sub-bands of triangular quantum well without using any numerical methods. Based on the surface potential drain current, intrinsic charge, gate capacitance, small signal and thermal noise models are developed. To validate the proposed numerical model, the results are calibrated with TCAD device simulation results and available experimental data from literatures.

Design of Low Noise Amplifier for Wimax Application

In this paper, the design of a low noiseamplifier (LNA) for WiMAX application is preasented. This LNA is design to operate at frequency range 3.3 GHz to 3.8GHz and the noise figure targeted are less than 2 dB while gain is more than 10 dB. Transistor ATF-54143 Low Noise Enhancement Mode Pseudomorphic HEMT from Avago Technology will be used to design the LNA because it meet the specifications and recommended by Avago Technology in LNA design for WiMAX application. AWR Microwave Office will be used in simulation for this project and starting from scratch, the LNA will be designed from 2-port network transistor, input and output matching and DC biasing to design a single stage LNA. Two techniques in LNA design which is the Feedback Amplifier (FA) and Balance Amplifier (BA) will be used and simulated to find the best technique which give optimum performance in terms of gain and noise figure. The best technique is the Feedback Amplifier which gives nominal noise figure of 1.02 dB and gain of 12 dB.

A monolithic based NIRS front-end wireless sensor

This paper concerns a novel analog front-end of a wireless brain oxymeter smart sensoring instrument based on near-infrared spectroreflectometry (NIRS). The NIRS sensor makes use of dynamic threshold transistors (DTMOS) for low voltage (1V), low power and low noise enhancement. The design is composed of a transimpedance amplifier (TIA) and an operational transconductance amplifier (OTA). The OTA differential input pairs use DTMOS devices for input common mode range enhancement. The OTA was fabricated in a standard 0.18μm CMOS process technology. Measurements under a 5pF capacitive load for the OTA gave a DC open loop gain of 67dB, unity frequency gain bandwidth of 400kHz, input and output swings of 0.58 and 0.7V, a power consumption of 18μW, and an input referred noise of 134nV/√Hz at 1kHz without any extra noise reduction techniques. The achieved features of the proposed oxymeter front-end will allow ultra low-light level measurements, high resolution and good temperature stability.

A novel fast algorithm of channel estimate

In a digital terrestrial broadcasting environment, since the channel characteristic may be severely distorted due to multipath interference, there is a need for an equalizer to counteract the interference. The equalizer algorithm has to meet two performance requirements: fast convergence capability and low noise enhancement. This paper proposes a simple, fast and efficient channel estimate algorithm used for the equalizer. Simulation results prove that an equalizer with the proposed algorithm can combat multipath of 0 dB magnitude and low noise enhancement. The proposed algorithm has low hardware complexity, and has a prospective application in VSB receivers in digital television terrestrial broadcasting (DTTB).

Enhancement source-coupled logic for mixed-mode VLSI circuits

Low-noise enhancement source-coupled logic (ESCL) is proposed for applications in high-precision mixed-mode integrated circuits (ICs). The differential ESCL topology offers potential low-power supply noise advantages over conventional CMOS logic for mixed-mode ICs by steering a constant current to perform the logic operation and it requires a smaller logic swing ( Delta V/sub L/<0.2 V/sub dd/) compared to static CMOS logic ( Delta V=V/sub dd/). For mixed-mode ICs, ESCL reduces the digital switching noise by approximately two orders of magnitude ('20-30 mu A/gate) compared to conventional static logic spikes (0.5-1 mA/gate) which is essential to the development of sensitive on-chip analog circuitry. Results from several ESCL circuits implemented in a 2- mu m p-well CMOS technology are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>