Enhancement source-coupled logic for mixed-mode VLSI circuits

Abstract

Low-noise enhancement source-coupled logic (ESCL) is proposed for applications in high-precision mixed-mode integrated circuits (ICs). The differential ESCL topology offers potential low-power supply noise advantages over conventional CMOS logic for mixed-mode ICs by steering a constant current to perform the logic operation and it requires a smaller logic swing ( Delta V/sub L/<0.2 V/sub dd/) compared to static CMOS logic ( Delta V=V/sub dd/). For mixed-mode ICs, ESCL reduces the digital switching noise by approximately two orders of magnitude ('20-30 mu A/gate) compared to conventional static logic spikes (0.5-1 mA/gate) which is essential to the development of sensitive on-chip analog circuitry. Results from several ESCL circuits implemented in a 2- mu m p-well CMOS technology are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>