Low Leakage Power Research Articles

AmLuCEP: Amalgamating LUT-based Compression and Adaptive Encoding Assisted Block Placement To Improve Lifetime of PCM-based Main Memories

With the rising demands for high capacity memory and poor scalability of the existing DRAM-based main memories, the emerging Non-volatile memories captures higher attention due to their high density and low leakage power consumption. However, the possible consideration of such memories as alternatives of DRAM is largely hindered by their intrinsic drawbacks like high write latency, high write energy and low write endurance. In this article, we propose an integrated solution by combining the effect of compression and encoding assisted block placement to improve lifetime of NVMs. We have developed a compression technique called LUT_Comp by exploiting the word-level redundancy present in the words of the incoming cache blocks to NVM. LUT_Comp remains effective in reducing bit-flips in NVMs by offering a balance in compression ratio and coverage (Cov). Additionally, we also propose an encoding based block placement policy that places the compressed blocks in the appropriate half within the memory. The integrated approach of compression and block placement termed AmLuCEP offers a uniform bit-flips distribution while further reducing bit-flips in NVM. Experimental results show that AmLuCEP reduces bit-flips by 54%, 42%, 37%, 21%; energy consumption by 41%, 28%, 24%, 13%; and improves lifetime by 57%, 40%, 38%, 21% over baseline and the existing techniques READ [ 38 ], COEF [ 39 ] and SELEC [ 13 ], respectively.

Design of low delay low power hybrid logic based flip-flop using FinFET

The need for a low-power and high-speed technology for computation of digital signals is rising due to the fast growth of technological innovations. Flip-flops serve as fundamental elements in signal processing technologies. Hybrid logic has great potential for constructing flip-flop circuits because of its minimal transistor count as well as low-power properties.The present investigation presents a design for a tiny and low-power hybrid flip-flop that operates fully statically. The design has been developed by utilizing different circuitry-reduction techniques. It incorporates a hybrid logic approach combining pass transistor logic to decrease circuit complexity. The ongoing work utilizes a hybrid logic with low delay and low power to generate flip-flops. The proposed flip-flop design significantly decreases latency compared to the existing master-slave flip-flops. This flip-flop remains immune to clock overloading, resulting in reduced power consumption. Reducing the quantity of PFET (P-channel Field Effect Transistor) transistors enhances the circuit's delay, area, and power consumption. Implementing these circuit optimization techniques yields several benefits, such as reduced CLOCK-to-OUT and DIN-to-OUT node delays, decreased average power consumption, lower leakage power, and a transistor count of only 18. The results were achieved using Cadence Virtuoso at 18 nm finFET technology, with varied process corners, supply voltages ranging from 0.7 V to 1 V, and temperatures ranging from -50 °C to 75 °C. This study also presents a Monte Carlo simulation of power consumption, leakage, and delay for the suggested flip-flop. According to the simulations, the recommended flip-flop exhibits exceptional stability. The recommended flip-flop has lower power usage by at least 17.95 % compared to standard architectures due to the lower number of PFET transistors.

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

Junctionless FinFET devices are a substitute for conventional FinFET devices due to their short channel effects and easy manufacturing at sub 22 nm technology node. The manuscript presents an 8T-SRAM cell based on tri-gate junctionless FinFET technology. The FinFET device is designed with source/drain of Si material and the channel as a stack of Si − Si 0.75 Ge 0.25 − Si. The proposed SRAM cell structure consists of a CMOS inverter with stacked p-FinFETs, improving its performance in terms of noise margin and leakage power consumption. The manuscript investigates the variation of Static Noise Margin (SNM), leakage power dissipation and delay with supply voltage to analyze the sub-threshold operation of SRAM cell. The results reveal that the cascaded p-FinFETs minimize the leakage current owing to the stack effect, resulting in improved noise margin and lower leakage power. The stacked p-FinFET devices based SRAM cell achieves 1.11x read noise margin, 1.11x hold noise margin, −1.08x write noise margin and 57.1% less leakage power compared to conventional SRAM cell at 1.0 V. However, it exhibits more delay due to increased resistance and capacitance of the cascaded transistors. The process variation analysis is also performed to investigate the SNM distribution using monte-carlo simulation by taking 10,000 samples. The results indicate that the SRAM cell structures provide higher than 6σ yield at range of supply voltages.

Analysis of the influence of the traps on the AlGaN/GaN MOSHEMT characteristics for low leakage power devices

Analysis of the influence of the traps on the AlGaN/GaN MOSHEMT characteristics for low leakage power devices

Energy-Efficient High-Speed dynamic logic-based One-Trit multiplier in CNTFET technology

The appeal of portable electronics, embedded systems, and other smart devices has been steadily growing over time. The multi-valued logic (MVL) was primarily introduced to handle the interconnect issues in binary logic. The use of ternary logic reduces the circuit complexity, power consumption in interconnects, and total chip area. The carbon nanotube field-effect transistor (CNTFET) offers some significant features like low leakage power, equal hole and electron mobility, and modulation in threshold voltage by adjusting the diameter of the carbon nanotube (CNT). In this paper, a clocked dynamic and pass transistor logic-based ternary 1-trit multiplier circuit with only 28 transistors has been proposed. The proposed logic avoids the conventional approach of using logic gates, encoder/decoder, and multiplexers, which reduces the total device count to implement the multiplier. The reduced transistor count offers a reduction in power consumption, delay, power-delay-product (PDP), and energy-delay-product (EDP) in comparison to other state-of-the-art designs. Stanford 32-nm CNTFET model file and Synopsis HSPICE simulator have been used to carry out the simulations at a supply of 0.9 V. The proposed circuit shows a 34.16 %, 66.44 %, and 82.80 % reduction in power, PDP, and EDP as compared to the lowest power, delay, and PDP of the designs under consideration. The performance of the multiplier is evaluated under different temperatures, supply voltages, loads, and oxide thickness.

OML-PCM: optical multi-level phase change memory architecture for embedded computing systems

Unlike Dynamic Random Access Memory (DRAM), Phase Change Memory (PCM) offers higher density, longer data retention, and improved scalability because of its non-volatility and low leakage power. However, Electrically-Addressable PCM (EPCM) has a higher dynamic power and long latency than DRAM. To address these issues, scientists have developed Optically-Addressable PCM (OPCM), which uses 5-level cells instead of 2-level cells in EPCM. A silicon photonic link allows optical signals to reach OPCM cells at a high speed. Hence, OPCM can achieve a higher density while maintaining better performance at multi-level cells and consuming less power per access. However, OPCM is not suitable for general use since the photonic links do not provide an electrical interface to the processor. The aim of this paper is to present a hybrid OPCM architecture based on the use of novel multi-bank clusters with distinctive properties. Electrical-Optical-Electrical conversion (EOE) allows OPCM cells to be randomly accessed by using DRAM-like circuitry. The proposed hybrid design with multi-core processing and OPCM achieves a 2.13x speedup over previous approaches while consuming less Central Processing Unit (CPU) power. It is important to note that the proposed design offers 97 units fewer power-consistent bits than EPCM. In addition, the proposed architecture provides comparable performance and power to DDR4, as well as improved bandwidth density, space efficiency, and versatility. The Gem5 simulator was used to evaluate the design. Based on the outcomes of the analysis, the proposed architecture offers 2.08x and 2.14x better evaluations and density performance than EPCM. Furthermore, the execution time has been reduced by 2.13x, the analysis time by 1.23x, and the composition time by 4.60%.

Spin device-based image edge detection architecture for neuromorphic computing

Artificial intelligence and deep learning today are utilized for several applications namely image processing, smart surveillance, edge computing, and so on. The hardware implementation of such applications has been a matter of concern due to huge area and energy requirements. The concept of computing in-memory and the use of non-volatile memory (NVM) devices have paved a path for resource-efficient hardware implementation. We propose a dual-level spin–orbit torque magnetic random-access memory (SOT-DLC MRAM) based crossbar array design for image edge detection. The presented in-memory edge detection algorithm framework provides spin-based crossbar designs that can intrinsically perform image edge detection in an energy-efficient manner. The simulation results are scaled down in energy consumption for data transfer by a factor of 8x for grayscale images with a comparatively smaller crossbar than an equivalent CMOS design. DLC SOT-MRAM outperforms CMOS-based hardware implementation in several key aspects, offering 1.53x greater area efficiency, 14.24x lower leakage power dissipation, and 3.63x improved energy efficiency. Additionally, when compared to conventional spin transfer torque (STT-MRAM and SOT-MRAM, SOT-DLC MRAM achieves higher energy efficiency with a 1.07x and 1.03x advantage, respectively. Further, we extended the image edge extraction framework to spiking domain where ant colony optimization (ACO) algorithm is implemented. The mathematical analysis is presented for mapping of conductance matrix of the crossbar during edge detection with an improved area and energy efficiency at hardware implementation. The pixel accuracy of edge-detected image from ACO is 4.9% and 3.72% higher than conventional Sobel and Canny based edge-detection.

GWalloc: A self-adaptive generational wear-aware allocator for non-volatile main memory

Phase Change Memory (PCM) is considered a promising replacement for DRAM due to its superior performance characteristics such as low leakage power, high integration density, byte addressability and non-volatility. However, PCM’s limited write endurance significantly hinders its wide application. For example, PCM wears out quickly with traditional dynamic memory allocation policy in embedded systems which aggregates lots of writes in few memory blocks. To extend the lifespan of PCM, some wear-aware dynamic memory allocators have been proposed, which generally depend on some fixed parameters to limit the wear of PCM. However, these allocators can be inflexible as it is difficult to specify appropriate values for the required parameters in different scenarios. In this paper, we propose a Self-Adaptive Generational Wear-Aware Allocator (GWalloc). GWalloc divides memory blocks into two generations: the young and the old generation, according to their number of allocation times. GWalloc also dynamically adjusts the system’s wear threshold during allocations so that it can effectively balance the wear degree of PCM and the consumed memory space. The wear threshold restricts the upper wear limit of young memory blocks. Experimental evaluations show that compared with the state-of-the-art wear-aware dynamic memory allocators (NVMalloc, Walloc and UWLalloc), GWalloc improves PCM wear-leveling (evaluated by CV, a wear leveling indicator) by 38.6%, 39.1% and 38.3%, and saves 62.1%, 22.2% and 37.2% memory space overhead.

APPcache+: An STT-MRAM-Based Approximate Cache System With Low Power and Long Lifetime

Due to high static power and low scalability, the traditional SRAM-based cache is not a good solution for image processing applications. Emerging Spin Transfer Torque Magnetic RAM (STT-MRAM) is a promising candidate for cache due to its low leakage power and high density. However, STT-MRAM suffers from high write energy. Therefore, by making use of the ability of tolerating minor errors in image processing applications, this work presents an STT-MRAM based APProximate cache architecture (APPcache+) to write/read approximate data, which can largely reduce the cache energy and improve the STT-MRAM lifetime. APPcache+ includes three main designs. Firstly, we find that there are many similar elements (e.g., pixels in images) in cache lines. Therefore, APPcache+ presents several lightweight similarity-based encoding techniques to remove redundant elements, thus shortening the data size and reducing the energy of STT-MRAM cache. Secondly, we design a partial read scheme to reduce the read energy of the STT-MRAM cache. In the traditional decompression process, the whole line is fetched into the decompressor, leading to unnecessary read energy. The partial read scheme can largely reduce read energy while keeping the overhead low. Thirdly, we observe the encoding schemes may lead to bit write imbalance. Therefore, we propose a lightweight Ping-Pong intra-line wear-leveling scheme to improve the lifetime. Compared with the baseline, extensive evaluation results show that our APPcache+ can largely reduce the overall energy by 32.58%, improve lifetime by 40.7% with only 2.2% performance degradation and 1.86% output quality loss.

Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications

Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications

Self Adaptive Logical Split Cache Techniques for Delayed Aging of NVM LLC

Due to the technological advancements in the last few decades, several applications have emerged that demand more computing power and on-chip and off-chip memories. However, the scaling of memory technologies is not at par with computing throughput of modern day multi-core processors. Conventional memory technologies such as SRAM and DRAM have technological limitations to meet large on-chip memory requirements owing to their low packaging density and high leakage power. In order to meet the ever-increasing demand for memory, researchers came up with alternative solutions, such as emerging non-volatile memory technologies such as STT-RAM, PCM, and ReRAM. However, these memory technologies have limited write endurance and high write energy. This emphasizes the need for a policy that will reduce the writes or distribute the writes uniformly across the memory thereby enhancing its lifetime by delaying the early wear out of memory cells due to frequent writes. We propose two techniques, Enhanced-Virtually Split Cache (E-ViSC) and Protean-Virtually Split Cache (P-ViSC), which dynamically adjust the cache configuration to distribute the writes uniformly across the memory to enhance the lifetime. Experimental studies show that E-ViSC and P-ViSC improve lifetime of NVM L2 caches by upto 2.31× and 1.97× respectively.

High Speed and Low Leakage Power Voltage Level Shifter using Regulated Cross-Coupled Network

This concise presents a power efficient level shifter using regulated cross-coupled network with split inverter. With the use of regulated cross-coupled network, power dissipation of the pull-up region drastically decreases. Level shifters convert the voltage levels which are below the threshold voltage to the acceptable voltage levels by decreasing the transistor size. A Split inverter is used at the output to decrease the short circuit current. Modified Split inverter along with the load capacitor at the output is used to increase the speed and to decrease the power consumption. This LS can save 31% power compared to other techniques. The proposed level shifter works effectively at high speed and consumes less power. For simulation, LT spice tool of 50 nm technology and 90 nm technology is used.

Comparative study of decoupled read buffer SRAM memory cell for improve read noise margin

The demand for portable devices is increasing day by day for which on-chip memory plays an important role to define the performance of the overall system. The various memory cell architectures are proposed by many researchers, but not a single memory cell architecture fulfills all design constraints. The various applications require optimized parameters of memory design such as low-power memory applications requiring low leakage power, high stable memory requiring higher noise margins, and high performance requiring high speed of operation. The conventional 6 T SRAM cell is most suitable for small size memory and high speed circuits. But it fails to achieve higher read stability at lower supply voltage, so various other memory cells are proposed to improve the read stability in memory cells such as 8T, SHO10TP1, WANG9T, KIM10T, and SUL10T. This work presents the comparative analysis of various available SRAM cell architectures under various design constraints. This work also shows the effect of supply voltage scaling over the various memory cells. The presented comparative work is useful for researchers to select the appropriate memory cell according to their requirements. The presented work is simulated using a 90 nm technology file and the simulated results shows that for low power application, 8T memory cell is the most prominent memory cell, for higher stability SHO 10TP1, WANG 9 T, KIM10T is found to be most suitable memory cells, and for high performance & smaller size system requirement, 6T memory cell is found most suitable.

Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell

Supply voltage scaling along with the use of non-volatile memory (NVM) device has proven to be the viable approaches for reducing both static and dynamic power consumption in SRAM's. The non-volatile SRAM has power down mode, however at lower supply voltage, the performance of the cell is affected due to process variations. So, to overcome this issue, this paper presents a 13-transistor process invariant nvSRAM cell. The cell introduces Schmitt Trigger invertor nvSRAM cell structure instead of CMOS inverter in existing cells. This modification provide tolerance to process variations by making the proposed cell operate at the lowest minimum power supply voltage at 6σ failure point in comparison to others, by considering both static and dynamic measure. Also, the proposed cell consumed 33.4X lower leakage power than the existing one at their respective Vmin.

CADEN: Compression-Assisted Adaptive Encoding to Improve Lifetime of Encrypted Nonvolatile Main Memories

Nonvolatile memories are widely considered as a potential replacement of DRAM in main memory due to their high density and low-leakage power consumption. The data in these memories are stored in encrypted form to protect them from data stealing. However, the encryption techniques, on account of their diffusion property impose high randomization in the generated encrypted data. It leads to enormous bit-flips in the memory cells, leading to their early wear out. In this letter, we propose a technique called CADEN that combines our compression technique COMF with an adaptive encoding scheme. The compressed data generated by COMF is encoded in finer granularity using an adaptive encoding approach at low storage overhead. Experimental evaluation shows that CADEN reduces bit-flips and improves lifetime in PCM main memory compared to baseline and existing techniques. In particular, CADEN shows 52% and 57% reduction in bit-flips and energy consumption and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.31\times $ </tex-math></inline-formula> improvement in lifetime over baseline.

A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache System

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising cache memory candidate due to its high density, low leakage power, and nonvolatility. Multilevel cell (MLC) STT-MRAM can further increase density by storing 2 bits in one cell’s hard and soft domain, respectively. However, MLC STT-MRAM suffers two-step write, leading to high write energy, long latency, and severe lifetime degradation. Current encoding techniques propose to encode the new data to reduce the two-step data writes. However, they have two weaknesses: 1) high area overhead, e.g., recent work TSE (Hsieh et al., 2020) needs extra 37.5% MLCs and 2) prolong the write latency due to an extra read. Therefore, we propose enhanced one-step write (EOSwrite) to write data in one step. EOSwrite includes line bypassing and four intraline encoding techniques. Line bypassing schemes can bypass the writes to zero or clean lines, leading to low write/read latency. As for the intraline techniques, we propose four write modes. They utilize the data patterns and the clean data in cache lines to write data in one step, therefore reducing the data write latency. The key idea of one-step write is to write as much data as possible in the soft domain of MLC STT-MRAM. EOSwrite can greatly relieve the weaknesses of the current encoding schemes. Evaluation results show that EOSwrite can improve the lifetime of MLC STT-MRAM by 56.96%, reduce dynamic energy by 33.95%, reduce access latency by 36.95%, and improve system performance of MLC STT-MRAM by 4.30%, respectively. While the area overhead of EOSwrite is only 7.27%.

DESIGN OF A 6T SRAM CELL WITH MINIMAL POWER USING CADENCE VIRTUOSO

It has proven challenging for VLSI designers to lower leakage power at the nanoscale level. This is because high- end gadgets, battery-operated portable pads, and other communication tools are in high demand. Memories are made up of static RAM and dynamic RAM. SRAM has had a significant impact on the worldwide VLSI market sinceit is preferred over DRAM because to its rapid read and write access times. Using a 6T static random access memory cell, this study's novel approach to lowering leakage current at various technologies has been put forth. To reduce the 6T SRAM cell leaking power, three source biasing techniques are used. At 45 nanometer and 90 nm technology nodes, the three techniques are NMOS diode clamping, PMOS diode clamping, and NMOS-PMOS diode clamping. The implementation of a 6T SRAM cell using the Multiple Threshold CMOS (MTCMOS) technique at 45nm technology is also emphasised in this article. Using the cadence virtuoso tool, the simulation is completed and different power dissipations are examined for 45 nm and 90 nm technologies, respectively, at supply voltages of 0.45 V and 0.9 V. Comparing PMOS clamping to the other two suggested techniques, an average power reduction of 82.19% was observed.

A Stable Low Leakage Power SRAM with Built-In Read/Write-Assist Scheme using GNRFETs for IoT Applications

Design of circuits using graphene nanoribbon field-effect transistors (GNRFETs), as promising next-generation devices, can improve total performance of a chip due to offering excellent properties. However, GNRFETs are in the early stage of design, and the studies of process-voltage-temperature (PVT) variations on their performance are very crucial. Therefore, this paper aims to design, simulate, and evaluate a novel stable fully differential 12 T (SFD12T) SRAM using GNRFETs under PVT variations. Simulation results in 16 nm GNRFET technology at 0.5 V show that the proposed design improves read stability/writability by 2.11×/1.09 × compared to fully differential 8 T (FD8T: as a basic cell) due to using built-in read/write-assist scheme, which forces “0” storing node to ground during a read operation and cuts pull-down path off during a write operation, respectively. An improvement of at least 4.79% (18.55% compared to FD8T) in leakage power is achieved due to stacking of transistors. The fourth-best read/write energy among eight studied SRAMs is related to the proposed design. In addition, it can support the bit-interleaving architecture because it eliminates half-select disturbance issues. Generally, the proposed design is the best SRAM from the figure of merit (FOM) point of view, so it can be an optimal choice for Internet-of-Things applications.

Design of a Single-Ended-Write Schmitt-Trigger Based 10T SRAM Cell

Technology scaling is done in order to accommodate more and more transistors in today’s high performance VLSI circuits. These high-performance digital circuits demand large capacity of memory to accomplish faithful operations. However, at scaled technology, SRAM-cell stability is a major issue of concern. Also, increased integration density of these VLSI circuits causes increased power consumption. Leakage power in today’s VLSI circuits has become comparable to dynamic power consumption which also needs to be addressed. In this work, a Schmitt-trigger (ST) based 10T SRAM cell with single-ended-writing and differentially-read feature is proposed. The proposed cell offers enhanced stability and dissipates lower leakage power. Due to separate ports for writing and reading in the proposed cell, the conflict design requirement (which is a condition in conventional 6T cell) is eliminated. Schmitt-trigger based inverters in the proposed cell causes increased threshold voltage of the inverters resulting in enhanced cell stability during read operation. Simulation is carried out on TSPICE using a 65nm Predictive Technology Model (PTM). Results show that the proposed 10T cell provides a 1.7x larger Read static noise margin (RSNM) than the conventional 6T cell. Proposed 10T cell provides Write static noise margin (WSNM) of 155mV during write ‘0’ while 150mV during write ‘1’ operation, respectively, at 0.4V. At a supply voltage of 0.4V, the proposed 10T cell consumes 0.71x lesser static power as compared to that of a conventional 6T cell. However, proposed cell uses more transistors (10 transistors) as compared to that of the conventional 6T cell, therefore, our cell occupies large chip-area as compared to the conventional 6T cell.

MASTER: Reclamation of Hybrid Scratchpad Memory to Maximize Energy Saving in Multi-Core Edge Systems

Most modern multi-core edge devices work in outdoor situations with limited power supplies like energy harvester and batteries. Therefore, energy consumption is a fundamental issue in which the memory subsystem has a significant role. Scratchpad memories (SPM) can provide a broad potential for energy saving. Still, due to the insufficient SPM capacity in such edge devices, a rigorous SPM data allocation scheme is necessary to reduce the energy consumption of the memory subsystem. Emerging non-volatile memories (NVMs) are very useful to reduce the energy consumption of the memory subsystem. Compared with SRAM, NVMs have lower leakage power and higher density, but the read and write latencies of the NVMs are higher than the SRAM. Therefore, embedded and edge devices can take advantage of hybrid SPM composed of both NVM and SRAM to achieve further energy saving. This paper proposes MASTER, a task mapping, task scheduling, and dynamic SPM allocation scheme that efficiently utilizes the hybrid SPM space. To this end, we model the hybrid SPM allocation on a multi-core system with integer linear programming formulation to minimize the energy consumption of the memory subsystem. Experimental results show that MASTER improves the energy saving of the memory subsystem by up to 34 percent compared to EADA, which is a heuristic dynamic data allocation algorithm for multi-core systems with hybrid SPM.