Low-k Damage Research Articles

Low-k integration: Gas screening for cryogenic etching and plasma damage mitigation

The integration of porous organo-silicate low-k materials has met a lot of technical challenges. One of the main issues is plasma-induced damage, occurring for all plasma steps involved during interconnects processing. In the present paper, we focus on porous SiOCH low-k damage mitigation using cryogenic temperature so as to enable micro-capillary condensation. The aim is to protect the porous low-k from plasma-induced damage and keep the k-value of the material unchanged, in order to limit the RC delay of interconnexion levels while shrinking the microchip dimension. The cryogenic temperature is used to condense a gas inside the porous low-k material. Then, the etching process is performed at the temperature of condensation in order to keep the condensate trapped inside the material during the etching. In the first part of this work, the condensation properties of several gases are screened, leading to a down selection of five gases. Then, their stability into the porous structure is evaluated at different temperature. Four of them are used for plasma damage mitigation comparison. Damage mitigation is effective and shows negligible damage for one of the gases at −50°C.

Low-k dielectric etch challenges at the 7 nm logic node and beyond: Continuous-wave versus quasiatomic layer plasma etching performance review

For logic nodes of 7 nm and beyond, back-end-of-line (BEOL) trench patterns have a critical pitch of less than 40 nm, directly affecting the plasma etch process window of the dual damascene etch process. Feature size dependent etch depth (reactive ion etch, RIE lag), hard mask selectivity, and ultra-low-k (ULK) damage have become significant challenges that must be overcome in order to meet target device performance. Recently, atomic layer etching has been used to widen the plasma etch process window in terms of selectivity and process control [S. Sherpa, P. L. F. Ventzek, and A. Ranjan, J. Vac. Sci. Technol. A 35, 05C310 (2017); T. Tsutsumi, H. Kondo, M. Hori, M. Zaitsu, A. Kobayashi, T. Nozawa, and N. Kobayashi, J. Vac. Sci. Technol. A 35, 01A103 (2017)]. In this work, the impact of a quasiatomic layer etch (QALE) process, a conventional continuous wave plasma, and a pulsed plasma process on ULK materials were investigated to determine the benefits of an ALE process approach for BEOL etching. Both blanket ULK film and patterned ULK samples were used for this study. The ULK etch damage from each process was characterized using Fourier transform infrared spectroscopy and x-ray photoelectron spectroscopy on three different ULK films. From patterned samples, it was determined that QALE could be used to successfully suppress RIE lag in low-k materials at advanced pitches, while keeping low-k damage to a minimum. In addition, the QALE technique showed improved hard mask selectivity and resulted in lower line edge pattern roughness. Based on this study, the authors concluded that QALE is a powerful plasma etch method to overcome BEOL etch challenges at advanced pitches.

Low-k protection from F radicals and VUV photons using a multilayer pore grafting approach

Polymer grafting was studied in porous low-k SiCOH films as a protection against plasma damage. Pores of low-k films were covered by a plasma damage management polymer. A multistep deposition approach was applied to increase the polymer layer thickness that helped avoid pore stuffing, nonuniform deposition and polymer overburden. To study polymer protection, low-k films were exposed to F radicals and VUV photons, separately and simultaneously, at temperatures from −45 °C to +10 °C. Effective polymer protection at room temperatures was demonstrated. Lowering the temperature decreases degradation by F radicals while VUV damage, which is temperature independent, became dominant. Low-k damage protection was also significant under simultaneous exposure to F radicals and VUV photons. In the tested temperature range damage under simultaneous exposure to F radicals and VUV photons was higher than the sum of separate F and VUV damage due to a synergistic effect. To decrease the material k-value after etching, the polymer was removed from the pore walls using UV cure. It was shown that almost complete polymer removal was achieved after UV treatment. The described approach was applied to low-k etching in RF CCP CF4, CF4/Ar plasmas and exposure to Ar plasma. Significant improvement of the film k-value after the plasma treatment was confirmed.

Multifold study of volume plasma chemistry in Ar/CF4 and Ar/CHF3 CCP discharges

Low-pressure RF plasma in fluorohydrocarbon gas mixtures is widely used in modern microelectronics, e.g. in the etching of materials with a low dielectric constant (low-k) materials). The multifold experimental and theoretical study of a radio frequency capacitively coupled plasma at 81 MHz in Ar/CF4/CHF3 has been carried out at 50 mTorr and 150 mTorr gas pressures. A wide set of experimental diagnostics together with hybrid PIC MC model calculations were applied to a detailed study of the plasmas. Measurements of the F atoms, HF molecules and CFx radicals, electron density, electronegativity and positive ion composition were performed. Absolutely calibrated VUV spectrometry was carried out to measure the VUV photon fluence towards the electrode. This combined experimental and model approach allowed us to establish the fundamental mechanisms of the charged and neutral species elementary reactions. Dissociative charge transfer reactions and fluoride transfer reactions influence the main ion (CF, CHF) composition in Ar/CF4/CHF3 plasma a lot. The mechanisms of heavy ion formation in Ar/CHF3 are also discussed. The important role of additional attachment mechanisms (besides dissociative attachment to the feedstock gases, CF4, CHF3) was analyzed. The catalytic chain mechanism, including the HF molecules, which defines the CFx kinetics in Ar/CHF3 plasma, was validated. This multifold approach enabled us to determine the complicated plasma chemical composition of the active species as well as the fluxes of VUV photons at the surface of the processed material, and is a result that is important for understanding low-k damage.

Integration of porous low-k dielectrics using post porosity pore protection

Post porosity pore protection is studied as a means for low damage integration of porous low-k dielectrics. Homogeneous low-k densification is achieved using poly(methyl methacrylate) (PMMA) as a sacrificial filler. The improvement in plasma-induced damage is investigated on a plasma-enhanced chemical vapor deposition 2.0 porous organo-silicate glass, including damage from radicals and vacuum ultraviolet photons. Open pores are sealed upon polymer protection; therefore the penetration of metal species during deposition of a metal diffusion barrier is avoided. Various solutions for post metallization polymer removal are investigated, such as hydrogen remote plasma and an ultraviolet cure. The PMMA removal process is studied in order to avoid Cu wire degradation. Finally, low-k damage and barrier continuity are investigated on patterned wafers with functional circuits. By means of transmission electron microscopy inspection and electrical measurement, effective integrated k-values are extracted, giving a value keff ~ 2.5–2.6 for the post metallization polymer removal option.

Characterization of process-induced damage in Cu/low-k interconnect structure by microscopic infrared spectroscopy with polarized infrared light

Microscopic Fourier-transform infrared (FT-IR) spectra are measured for a Cu/low-k interconnect structure using polarized IR light for different widths of low-k spaces and Cu lines, and for different heights of Cu lines, on Si substrates. Although the widths of the Cu line and the low-k space are 70 nm each, considerably smaller than the wavelength of the IR light, the FT-IR spectra of the low-k film were obtained for the Cu/low-k interconnect structure. A suitable method was established for measuring the process-induced damage in a low-k film that was not detected by the TEM-EELS (Transmission Electron Microscope-Electron Energy-Loss Spectroscopy) using microscopic IR polarized light. Based on the IR results, it was presumed that the FT-IR spectra mainly reflect the structural changes in the sidewalls of the low-k films for Cu/low-k interconnect structures, and the mechanism of generating process-induced damage involves the generation of Si-OH groups in the low-k film when the Si-CH3 bonds break during the fabrication processes. The Si-OH groups attract moisture and the OH peak intensity increases. It was concluded that the increase in the OH groups in the low-k film is a sensitive indicator of low-k damage. We achieved the characterization of the process-induced damage that was not detected by the TEM-EELS and speculated that the proposed method is applicable to interconnects with line and space widths of 70 nm/70 nm and on shorter scales of leading edge devices. The location of process-induced damage and its mechanism for the Cu/low-k interconnect structure were revealed via the measurement method.

Impact of Wire Geometry on Interconnect <italic>RC</italic> and Circuit Delay

We investigate the impact of wire geometry on the resistance, capacitance, and RC delay of Cu/low-k damascene interconnects for fixed line-to-line pitch. The resistance is computed by applying a semiempirical resistivity model, calibrated to Cu damascene wires, integrated with a Ru-based liner, currently investigated for the 7 nm logic technology node. The capacitance is simulated by means of a 2D field solver (Raphael) by Synopsys. The impact of line dimensions is analyzed for the case of 32 nm pitch interconnects, which are representative of the 7 nm logic technology node. We show that for aspect ratios greater than 1, the resistance is more sensitive to variations of the line width rather than of the line height, because of the higher surface scattering induced by the sidewall interfaces, which are closer to each other compared with the top and bottom interfaces. For capacitance, low-k sidewall damage exacerbates capacitance sensitivity to line dimensions and, for typical interconnect schemes, the impact of line width variations dominates over variations of the line height. We demonstrate that for a given pitch and dielectric stack height, the RC delay can be significantly reduced by targeting wider and deeper damascene trenches, that is, by trading capacitance for resistance, and that an optimal wire geometry for RC delay minimization exists. In addition, we show that a given RC delay can be achieved with several geometries and, therefore, R and C pairs, which represents a useful degree of freedom for designers to optimize system-level performance. As an application, we analyze a possible 7 nm technology scenario and show that wide and deep damascene trenches can mitigate the impact of the increased wire resistance on circuit delay.

Characterization of CO2 plasma ashing for less low-dielectric-constant film damage

The mechanism of CO2 plasma ashing process was evaluated. CO2 plasma is a good candidate for the ashing process for photoresists because it generates a lot of CO2 ions. These ions can ash equivalent amounts of carbon film with less low-k damage than can oxygen radicals. A high ratio of CO2 ions to oxygen radicals in CO2 plasma can make the ashing process efficient with less low-k damage. The ratio can be controlled by changing the CO2 flow rate, chamber pressure, and radio frequency (RF). When a lower RF frequency of 2 MHz as a plasma generator was used, the authors reduced sidewall low-k damage in patterned structures. CO2 ions can perform anisotropic ashing because the velocity distribution of CO2 ions is directional due to acceleration with a plasma sheath.

Damage free integration of ultralow-k dielectrics by template replacement approach

Cu/low-k integration by conventional damascene approach is becoming increasingly difficult as critical dimensions scale down. An alternative integration scheme is studied based on the replacement of a sacrificial template by ultralow-k dielectric. A metal structure is first formed by patterning a template material. After template removal, a k = 2.31 spin-on type of porous low-k dielectric is deposited onto the patterned metal lines. The chemical and electrical properties of spin-on dielectrics are studied on blanket wafers, indicating that during hard bake, most porogen is removed within few minutes, but 120 min are required to achieve the lowest k-value. The effective dielectric constant of the gap-fill low-k is investigated on a 45 nm ½ pitch Meander-Fork structure, leading to keff below 2.4. The proposed approach solves the two major challenges in conventional Cu/low-k damascene integration approach: low-k plasma damage and metal penetration during barrier deposition on porous materials.

Low-k material damage during photoresist ashing process

The change of –OH and –CH3 component ratios in Fourier transform-infrared analysis of low-k materials during photoresist (PR) ashing processes were compared to assess the differences in the damages to low-k materials in a reactive ion etch (RIE) chamber and a magnetized-inductively coupled plasma (M-ICP) chamber. In M-ICP, the PR ashing rate was 28.1% higher than that of RIE, but the low-k material damage in M-ICP decreased when typical ashing conditions were used in each machine. The dependences of low-k material damage and PR ashing rate on the pressure, source power, and bias power in the M-ICP chamber were studied. We measured the ion energy distributions using an ion energy analyzer from which the flux could be also obtained. We found that the PR ashing rate increased as the ion flux increased, while the low-k material damage also increased as the ion flux and the incident ion energy increased. However, as the pressure decreased, the ion flux increased dramatically and the ion energy decreased. As a result, the PR ashing rate could be high and the low-k material damage low.

Communication—The Impact of TaN Barrier Processes on Different Ultra Low-k Dielectrics

TaN barriers were deposited by physical vapor and atomic layer deposition on different low-k dielectrics with dielectric constant values of 2.4, 2.55 and 2.7. The low-k damage introduced by different TaN processes was studied using metal-insulator-metal capacitors, where the k value was extracted from Capacitance-Voltage measurements. A plasma enhanced atomic layer deposition TaN process caused an increase of k value from 15% to 40% compared to physical vapor deposition TaN and thermal atomic layer deposition. Current-Voltage characteristics showed the presence of moisture impacting the behavior of plasma enhanced atomic layer deposition TaN samples corresponding to a severe plasma damage.

Industrial Challenges of TiN Hard Mask Wet Removal Process for 14nm Technology Node

TiN Hard Mask (TiN-HM) integration scheme has been widely used for BEOL patterning in order to avoid ultra low-k (ULK) damage during plasma-ash process [1]. As the technology node advances, new integration schemes have to be used for the patterning of features below 80 nm pitch with 193 nm immersion lithography. In particular, thicker TiN-HM is necessary in order to ensure Self-Aligned-Via (SAV) integration which resolves via-metal short yield and TDDB issues caused by Litho-Etch-Litho-Etch (LELE) misalignment [2, 3]. The Cu filling process is significantly more difficult if the thick TiN is not removed because of the high aspect ratio of the structures. Moreover, with the use of TiN hard mask, a time-dependent crystal growth (TiCOF) residue may forms between line etch and metal deposition [4, 5], also hindering copper filling. Post-Etch-Treatment after line etching is one solution to the problem but N2plasma is not efficient enough to suppress the residue completely [6], and the CH4treatment proposed in [5] may be difficult to implement for 14 nm node, thus an efficient wet strip and clean provides a better solution.

A Proprietary Chemical Bath Life Study in MHM ULK Scheme Wet Cleaning

As technology evolves to 45nm and beyond, IC companies adopt TiN metal hardmask instead of PR (photo resist) to gain better etching profile, CD uniformity and less low-k material damage. To improve Cu gap fill capability, an in situ TiN pull back is needed in the subsequential wet clean step. This pullback can be done by mixing some additive with clean media, like H2O2. But H2O2 tends to decompose along the time, it also bring the challenges to the wet clean media stability. In this paper, we study a proprietary wet clean chemical behavior with pH, Cu ion concentration, H2O2 additive and bath lifetime. Cu ions content is demonstrated critical to the mixture instability when H2O2 presents. Chemical degradation mechanism is also discussed.

The Optimization of Metal Hard-Mask Based All-in-One Etch

Metal hard-mask based all-in-one etch scheme has been extensively integrated with Cu interconnects for its significant improvement in terms of the line sidewall roughness, the reduction of ultra low-k material damage and the enhancement of lithography process window. In this paper, we investigated the trade-off relationship between electromigration (EM) and time-dependence break-down (TDDB) on one AMEC (Advanced Micro-fabrication Equipment Company) test vehicle. This etcher features the special switchable rf-power at bottom electrode. Results indicate the dynamic ESC (electrostatic chuck) is imperative to meet the quite different temperature demands between via etch and trench etch step, thus reducing the via encroachment on metal hard-mask while no metallic residue is detected at trench bottom. Meanwhile, the tunable edge ring coupled with the optimization of trench etch gases are also critical to deliver the on-target Rc and reliability performance. In brief, we successfully demonstrated the partial SAV (self-aligned via) could deliver the on-target WAT and reliability performance on AD-RIE.

Low-k films modification under EUV and VUV radiation

Modification of ultra-low-k films by extreme ultraviolet (EUV) and vacuum ultraviolet (VUV) emission with 13.5, 58.4, 106, 147 and 193 nm wavelengths and fluences up to 6 × 1018 photons cm−2 is studied experimentally and theoretically to reveal the damage mechanism and the most ‘damaging’ spectral region. Organosilicate glass (OSG) and organic low-k films with k-values of 1.8–2.5 and porosity of 24–51% are used in these experiments. The Si–CH3 bonds depletion is used as a criterion of VUV damage of OSG low-k films. It is shown that the low-k damage is described by two fundamental parameters: photoabsorption (PA) cross-section σPA and effective quantum yield φ of Si–CH3 photodissociation. The obtained σPA and φ values demonstrate that the effect of wavelength is defined by light absorption spectra, which in OSG materials is similar to fused silica. This is the reason why VUV light in the range of ∼58–106 nm having the highest PA cross-sections causes strong Si–CH3 depletion only in the top part of the films (∼50–100 nm). The deepest damage is observed after exposure to 147 nm VUV light since this emission is located at the edge of Si–O absorption, has the smallest PA cross-section and provides extensive Si–CH3 depletion over the whole film thickness. The effective quantum yield slowly increases with the increasing porosity but starts to grow quickly when the porosity exceeds the critical threshold located close to a porosity of ∼50%. The high degree of pore interconnectivity of these films allows easy movement of the detached methyl radicals. The obtained results have a fundamental character and can be used for prediction of ULK material damage under VUV light with different wavelengths.

Pore sealing of k 2.0 dielectrics assisted by self-assembled monolayers deposited from vapor phase

Self-assembled monolayers (SAMs) derived from 11-cyanoundecyltrichlorosilane precursor are deposited in vapor phase and characterized on ultra-low-k Chemical Vapor Deposition (CVD) dielectric films (k=2.0) with open porosity up to 50% and pore diameter as large as 3.5nm. Two surface preparation methods, such as Ar/H2 and Ar/N2 plasma pretreatments, are investigated and the pore sealing efficiency after SAM deposition is quantified from the experimental determination of open porosity and pore size measurements derived from toluene adsorption isotherms. In parallel, low-k damage is evaluated after surface preparation and SAM deposition by XPS depth profiling and by monitoring the change in refractive index, thickness and k value together with the –CH3 and –CH2 normalized FTIR peak areas vs. the pristine dielectric. Subsequently, a 10nm HfO2 thin film was deposited by Atomic Layer Deposition (ALD) in order to assess the pore-sealing capability of the proposed approach. When combining surface activation, SAM deposition and ALD, it was possible to accomplish a wide range of pore sealing. By adequate optimization, it was possible to obtain complete pore sealing after ALD, without precursor penetration into the porous low-k film, but at the expense of a 37% k increase for a 90nm dielectric thickness.

Ultra Low-k Damage Control and k Recovery for 28nm RC Improvement

To improve resistance-capacitance delay, porous ultra low-k dielectric materials are used in advanced copper damascene integration. However, the BEOL processes often lead to low-k film damage by removing the hydrophobic groups Si-CH3, and convert partially low-k materials surface from hydrophobic to hydrophilic one. During the wet related processes, the hydrophilic porous low-k film surface is easy to absorb moisture and potentially increase k-value. In this work, we developed the processes that can maintain ultra low-k film k-value either by repairing low-k damage or by removing moistrue. Dry etch plasma process is one of the main steps to result in low-k film damage. Post etch treatment (PET) was optimized to repair porous low-k film surface due to the etch damage. This improved process with less low-k damage can significantly reduced the moisture absorption in the following wet process and improve the capacitance by about 10%. Various thermal treatments post wet and post CMP processes were studied, including temperature, gases and pressures. From our results, post wet clean heat treatment can improve capacitance by about 5% and post CMP heat treatment can improve capacitance by about 10%. To decrease moisture absorption from atmosphere after the wafers were processed thru CMP, queue time from CMP to NDC deposition also was studied and the safe specification was also defined.

Formation of Porous Low-K Dielectric Interconnect Structure on Advanced Dielectric-Reactive Ion Etcher

Porous low-k dielectrics have been extensively integrated into back-end-of-line (BEOL) for its significant improvement of chip resistance-capacitance (RC) delay performance. However, Metal hard-mask (MHM) has to be introduced to reduce the low-k damage from radicals and photons during plasma strip. We investigated the formation of porous low-k dielectric interconnect structure on advanced dielectric reactor ion etcher (AD-RIE) of AMEC (Advanced Micro-fabrication Equipment Company) from the point of view of etch profile, wafer acceptance test (WAT), RC delay performance and reliability (RE). Scanning electron microscope (SEM) results exhibit the desired etch profiles for both trench and via. The WAT electrical results, RC delay and RE performances can be well improved by etch profile control. In brief, all of these demonstrate AD-RIE is capable of delivering the qualified porous low-k dielectric structure as main-stream etchers did.

Review of Plasma-Based Etch Treatment in Dielectric Etch Processes

This work mainly focuses on the post-etch treatment (PET) in dielectric etch processes from contact etch, trench etch to all-in-one etch. PET step is optimized not only to efficiently remove the byproducts formed on the sidewall/bottom of contact/via hole during etch proceses but also to eliminate the surface corrosion of the etched metal comprising feature. Besides, we also leveraged PET to repair low-k damage and prevent the formation of mositure on film surface by modifing film from hydrophilic to hydrophobic, especially for low-k/ultra low-k dielectric processes. Results show the actual effect of PET in terms of reliability performance highly relies on the specific etch recipe, wet clean condition and substrate material in back end of line (BEOL). We also addressed the pre-etch treatment to effectively reduce the impact of photo-resist scumming in contact etch. In brief, plasma-based etch treatment is imperative to extend the tightened process window margin.

WAT and VBD Distribution Improvement on Low-K Trench All-in-one Process

WAT (Wafer Acceptance Test) and VBD (Voltage Breakdown) distribution are not merely a function of critical dimension and oxide thickness as were seen on conventional BEOL process on larger technology node. The complexity of electrical and reliability parameter becomes more on advanced technology node, i.e. 65nm and sub 65nm, as its k value and Cu surface plays some significant role on the parametric distribution result. This study is addressed to improve the WAT and VBD distribution by minimizing the Cu surface and low-k damage, such that the impact to the electrical parameter is small enough that can be negligible, hence the WAT and VBD will be more predictable and controllable. Optimization on this study would be focused on the chemical selection of the PR stripping and PET (Post Etch Treatment) steps, which are the critical steps for low-k and Cu surface damages.