Low Interfacial Density Research Articles

Electrical Characteristics of HfO2 Dielectrics with Ru Metal Gate Electrodes

Hafnium dioxide, , thin films were prepared by radio frequency magnetron sputtering of thin hafnium layers, followed by an oxidation process. Ru was deposited on the as the gate electrode. An equivalent oxide thickness of 12.5 Å was obtained in metal oxide semiconductor (MOS) capacitor with a low leakage current density of at in accumulation. The work function of Ru gate extracted from capacitance-voltage analysis was 5.02 eV, suggesting Ru has the appropriate work function for p-MOSFETs. Using the conductance method, a high interface state density of from the conduction band edge to the near midgap of Si was obtained in MOS, compared to low interface density level of in poly MOS. To evaluate the thermal stability, the samples were subjected to a rapid thermal anneal in an argon ambient up to 900°C. The electrical characteristics of MOS capacitor are discussed in detail with post-metal annealing temperatures.

Thermodynamic stability of Ga2O3(Gd2O3)∕GaAs interface

Ga 2 O 3 ( Gd 2 O 3 ) ∕ Ga As heterostructures have been annealed up to ∼780°C. Studies using x-ray reflectivity and high-resolution transmission electron microscopy have shown that the samples annealed under ultrahigh vacuum have maintained smooth and abrupt interfaces with the interfacial roughness being less than 0.2nm. The oxide remains amorphous, an important parameter for device consideration. Current–voltage and capacitance–voltage measurements have shown low leakage currents (10−8–10−9A∕cm2), a high dielectric constant of 15, and a low interfacial density of states (Dit) between gate dielectrics and GaAs. The attainment of a smooth interface between the gate dielectric and GaAs, even after high temperature annealing for activating implanted dopant, is a must to ensure the low (Dit) and to maintain a high carrier mobility in the channel of the metal–oxide–semiconductor field-effect transistor.

The influence of a material microstructure on the behaviour of dopants

Dopants, when introduced into a host lattice, can influence profoundly the properties of a material. It is therefore desirable in the design of new materials with improved or indeed optimised properties to understand the behaviour of such dopants. Most previous simulations have explored the structure and segregation of dopants in a ‘perfect’ host lattice, or, more recently, within a host lattice comprising a single additional structural feature such as a vacancy or dislocation. However, real materials are likely to comprise a complex microstructure. Here, we present simulations which explore the behaviour and segregation of dopant ions within a material which comprises such a complex microstructure. Specifically, we consider Ca-doped SrO thin films supported on MgO. Microstructural features of the host SrO lattice include: heterointerfaces, dislocation networks, defects (vacancies, substitutionals, and interstitials) and defect clusters, interfacial and epitaxial configurations, low interfacial densities, surface structures and morphologies. Our simulations suggest that the dopant Ca ions segregate to the surface of the SrO thin film, accommodate lattice positions within dislocation cores and migrate across the SrO/MgO heterointerfacial boundary. Such models can then be used as realistic starting configurations to calculate pertinent physical properties as performed previously (‘Synthesis, structure and ionic conductivity in nanopolycrystalline BaF2/CaF2 heterolayers’: D.C. Sayle et al., Chem. Commun., 2003, 1804 [ref. 1]). The strategy provides therefore a framework for using simulation techniques predictively to design systems with tailored properties.

High quality atomic-layer-deposited ultrathin Si-nitride gate dielectrics with low density of interface and bulk traps

Interface trap and bulk trap densities of atomic-layer-deposited (ALD) Si-nitride dielectrics have been evaluated by bipolar-voltage-pulse-induced current and electrical-stress-induced leakage-current measurements, respectively. In comparison with the conventional SiO2 dielectrics, significantly lower (∼1/3) interface trap density near the conduction band edge is observed in the ALD Si-nitride dielectrics. Moreover, the observed lower interface and bulk trap generations consistently explain the soft-breakdown-free phenomena observed in capacitors with the ALD Si-nitride gate dielectrics. Enhanced dielectric reliability and several other significant features have made the ALD Si-nitride gate dielectrics a front line candidate for extremely thin (equivalent oxide thickness ∼1 nm) gate dielectrics of sub-100-nm technology nodes.

Schottky barrier height and interfacial state density on oxide-GaAs interface

Photoreflectance (PR) and Raman spectra were employed to investigate the interfacial characteristics of a series of oxide films on GaAs. The barrier heights across the interfaces and the densities of interfacial states are determined from the PR intensity as a function of the pump power density. The oxide-GaAs structures fabricated by in situ molecular beam epitaxy exhibit low interfacial state densities in the low 1011 cm−2 range. The density of the interface states of the Ga2O3(Gd2O3)–GaAs structure is as low as (1.24±0.14)×1010 cm−2. The Ga2O3(Gd2O3) dielectric film has effectively passivated the GaAs surface. Additionally, Raman spectra were used to characterize the structural properties of the oxide films.

Tailoring the Material and Electronic Properties of Ultra-Thin ZrO2 Films for Microelectronics Application

ZrO2 thin film was investigated in this work to replace SiO2 as the gate dielectric material in future metal-oxide-semiconductor field effect transistors (MOSFET). ZrO2 thin film was deposited on planar Si (100) wafers by an atomic layer chemical vapor deposition (AL-CVD) process using a zirconium (IV) t-butoxide Zr(OC4H9)4 precursor and oxygen. Atomic layer controlled deposition of ZrO2 was achieved at 300°C to 400°C where the reaction was thermally activated with an activation energy of 29 kcal/mol, consistent with a β-hydride elimination mechanism leading to ZrO2 deposition. The deposited ZrO2 thin film was stoichiometric, amorphous, uniform, smooth, and conformal. An interfacial zirconium silicate formation was observed by the high-resolution transmission electron microscopy. The characterized electrical properties of ZrO2 including its high dielectric constant, small C- V hysteresis, and low interfacial density, are ideal for the MOSFET application.

High κ Gate Dielectrics For Si And Compound Semiconductors By Molecular Beam Epitaxy

ABSTRACTThe ability of controlling the growth and interfaces of ultrathin dielectric films on Si and compound semiconductors by ultrahigh vacuum physical vapor deposition has led to comprehensive studies of gate stacks employing the high κ gate oxide Ga2O3(Gd2O3), and the rare earth oxides Gd2O3and Y2O3. The epitaxy and the interfaces of Gd2O3on GaAs, GaN, and Si were characterized with atomic precision, and show strong tendency to conform to the underlying substrate, thus providing insight into the fundamental mechanism for low interfacial state density and effective passivation of GaAs and GaN surfaces. These Gd2O3and Y2O3gate stacks of abrupt interfaces and controlled microstructures were employed as a model system to elucidate critical issues of materials integration in CMOS scaling.

High κ Gate Dielectrics For Si And Compound Semiconductors By Molecular Beam Epitaxy

ABSTRACTThe ability of controlling the growth and interfaces of ultrathin dielectric films on Si and compound semiconductors by ultrahigh vacuum physical vapor deposition has led to comprehensive studies of gate stacks employing the high κ gate oxide Ga2O3(Gd2O3), and the rare earth oxides Gd2O3and Y2O3. The epitaxy and the interfaces of Gd2O3on GaAs, GaN, and Si were characterized with atomic precision, and show strong tendency to conform to the underlying substrate, thus providing insight into the fundamental mechanism for low interfacial state density and effective passivation of GaAs and GaN surfaces. These Gd2O3and Y2O3gate stacks of abrupt interfaces and controlled microstructures were employed as a model system to elucidate critical issues of materials integration in CMOS scaling.

Rapid thermal chemical vapor deposition of zirconium oxide for metal-oxide-semiconductor field effect transistor application

ZrO 2 is investigated in this work to replace SiO2 as the gate dielectric material in metal-oxide-semiconductor devices for its high dielectric constant, good thermal stability on silicon, and large band gap. ZrO2 films were deposited on p-Si(100) wafers by a rapid thermal chemical vapor deposition process using a zirconium (IV) t-butoxide Zr(OC4H9)4 precursor and oxygen. At temperatures between 300 and 400 °C, the reaction was thermally activated with an activation energy of 29 kcal/mol, consistent with a β-hydride elimination mechanism leading to ZrO2 deposition. In this regime at substrate temperatures below 350 °C, one atomic layer of ZrO2 can be deposited after each alternating exposure to the precursor and oxygen, ideal for achieving conformal coverage of ZrO2 over high aspect ratio features. Stoichiometric, uniform, and amorphous ZrO2 was obtained, and highly conformal step coverage of the deposited ZrO2 was observed on 300 nm features with an aspect ratio of 4. The dielectric constant of ZrO2 achieved in this work ranged from 15 to 18 depending upon process conditions and small C–V hysteresis and low interfacial state density were observed, ideal for metal-oxide-semiconductor field effect transistor application.

Initial growth of Ga2O3(Gd2O3) on GaAs: Key to the attainment of a low interfacial density of states

Growth of the first few layers of an oxide mixture Ga2O3(Gd2O3) on GaAs (100) substrate, electron-beam evaporated from a Ga5Go3O12 source, was found to be a single crystal. Reflection high-energy electron diffraction and x-ray diffraction studies show that the thin oxide film is epitaxially grown on GaAs with the surface normal (110) and in-plane axis [001] parallel to (100) and [011] of GaAs, respectively, and has a structure isomorphic to Mn2O3. Studies using high-resolution transmission electron microscopy on the oxide–GaAs interface indicate some atomic registry between the oxide and GaAs during the initial growth. The chemical composition of the oxide film was determined by x-ray photoelectron spectroscopy to be unequivocally pure Gd2O3.

Insulator/GaN Heterostructures of Low Interfacial Density of States

ABSTRACTA review is given on insulators (oxides and nitrides) which have been deposited on GaN to form metal-insulator (oxides and nitrides)-semiconductor (MOS or MIS) diodes with a low interfacial density of states (Dit). These insulators include AlN, SiO2, Si3N4, SiO2/Ga2O3, and Ga2O3(Gd2O3). Techniques for depositing these insulators and methods for cleaning GaN surfaces prior to the insulator deposition are discussed. Recent progress on GaN MOSFET's (with SiO2/Ga2O3, and Ga2O3(Gd2O3) as gate dielectrics) and MISFET's (with AlN as a gate dielectric) is also reviewed. When exposed to room air, GaN surface is not as robust as previously thought. Therefore, preparation of a clean GaN surface for deposition of oxides and nitrides is necessary to achieve a low Dit. By heating GaN samples in UHV to clean the surfaces followed by deposition of Ga2O3(Gd2O3) and SiO2, we have achieved a low Ditwith negligible hysteretic loops in the capacitance-voltage curves

Understanding the limits of ultrathin SiO 2 and SiON gate dielectrics for sub-50 nm CMOS

In spite of its many attributes such as nativity to silicon, low interfacial defect density, high melting point, large energy gap, high resistivity, and good dielectric strength, SiO 2 suffers from one disadvantage, low dielectric constant (K=3.9). Thus, ultrathin SiO 2 gate dielectric layers are required to generate the high capacitance and drive current required of sub-50 nm transistors. The silicon industry roadmap dictates 4 nm SiO 2 gate dielectrics for 0.25 μm technology today, and calls for <1 nm equivalent SiO 2 thickness for 0.05 μm technology in 2012. SiO 2 layers in this thickness range may suffer from boron penetration, reduced drive current, reliability degradation, and high gate leakage current. We will argue that none of these problems are limitations for thicknesses greater than about 1.3 nm. Below that thickness, the fundamental problems of high tunneling current and reduced current drive will prevent further scaling, unless alternate gate dielectrics are introduced.

Passivation of GaAs using (Ga2O3)1−x(Gd2O3)x, 0⩽x⩽1.0 films

The Ga2O3(Gd2O3) dielectric film was previously discovered to passivate the GaAs surface effectively. We have investigated the systematic dependence of the dielectric properties of (Ga2O3)1−x(Gd2O3)x on the Gd (x) content. Our results show that pure Ga2O3 does not passivate GaAs. Films with x⩾14% are electrically insulating with low leakage current and high electrical breakdown strength. Furthermore, a low interfacial density of states was attained in films with x⩾14%. The results show the important role of Gd2O3 in the (Ga2O3)1−x(Gd2O3)x dielectric films for effective passivation of GaAs.

Epitaxial cubic gadolinium oxide as a dielectric for gallium arsenide passivation

Epitaxial growth of single-crystal gadolinium oxide dielectric thin films on gallium arsenide is reported. The gadolinium oxide film has a cubic structure isomorphic to manganese oxide and is (110)-oriented in single domain on the (100) gallium arsenide surface. The gadolinium oxide film has a dielectric constant of approximately 10, with low leakage current densities of about 10(-9) to 10(-10) amperes per square centimeter at zero bias. Typical breakdown field is 4 megavolts per centimeter for an oxide film 185 angstroms thick and 10 megavolts per centimeter for an oxide 45 angstroms thick. Both accumulation and inversion layers were observed in the gadolinium oxide-gallium arsenide metal oxide semiconductor diodes, using capacitance-voltage measurements. The ability to grow thin single-crystal oxide films on gallium arsenide with a low interfacial density of states has great potential impact on the electronic industry of compound semiconductors.

The (Ga2O3)1−x(Gd2O3)x, Oxides with x = 0–1.0 for GaAs Passivation

ABSTRACTGa2O3(Gd2O3) film was previously discovered to effectively passivate GaAs surface, and the employment of this oxide as gate dielectric has led to the first demonstration of the enhancement-mode GaAs metal oxide semiconductor field effect transistors (MOSFETs) with inversion. In order to gain insight into the passivation mechanism and elucidate the role of Gd2O3, we have carried out a systematic study of the dependence of the structural and dielectric properties of (Ga2O3)1−x(Gd2O3) on the Gd (x) content. Our studies indicate that it is necessary to have the Gd addition exceeding 14% in order to form an electrically insulating dielectric with low interfacial state density. Furthermore, we found that pure Gd2O3 film grows epitaxially on GaAs in the single domain, (110) oriented Mn2O3 structure. This new crystalline dielectric has a dielectric constant ∼10, and shows excellent dielectric properties with low leakage and high breakdown strength even for films as thin as 2.5 nm. We expect that epitaxial growth of the Mn2O3 structure can be extended to other rare earth oxides, and to other semiconductor substrates like Si.

Amorphous Hydrogenated Silicon Films for Solar Cell Application Obtained with 55 kHz Plasma Enhanced Chemical Vapor Deposition

In this work, a‐Si:H films with good electronic properties in spite of an inhomogeneous structure were prepared by the 55 kHz plasma enhanced chemical vapor high‐rate deposition technique. The structural analysis using infrared spectroscopy and atomic force microscopy has shown that these films possess two dominant types of microstructural inhomogeneities, which differ by size. To analyze the influence of a 55 kHz plasma on the properties of intrinsic a‐Si:H film, the density of states in the a‐Si:H mobility gap was estimated by modeling of the temperature dependence of the photoconductivity and from electron paramagnetic resonance measurements. Investigated capacitance‐voltage characteristics showed that a‐Si:H/c‐Si heterostructures have low interface density of states and can be considered as an ideal abrupt heterojunction.

Oxide–GaAs interfacial electronic properties characterized by modulation spectroscopy of photoreflectance

Built-in electric fields and interfacial state densities (Dit) in a series of oxide–GaAs heterostructures fabricated by in situ molecular beam epitaxy were studied using room temperature photoreflectance. The samples investigated were air-, Al2O3–Ga2Ox–, and Ga2O3(Gd2O3)–GaAs. We found that the built-in electric fields are 48, 44, and 38 kV/cm for air-, Al2O3-, and Ga2Ox–GaAs samples, respectively. For the Ga2O3(Gd2O3)–GaAs sample, the built-in electric field is negligibly small, indicating a very low interfacial state density. Estimated by the low field limit criterion, Dit is less than 1×1011 cm−2 eV−1. Our results on the Ga2O3(Gd2O3)–GaAs sample are consistent with the data obtained previously using capacitance–voltage measurements in quasistatic/high frequency modes and photoluminescence measurements.

Memory effects of SrBi2Ta2O9 capacitor on silicon with a silicon nitride buffer

The memory effects of SrBi2Ta2O9 (SBT) films deposited on Si substrates with an ultra-thin silicon nitride buffer layer have been investigated. The Capacitance-Voltage (C-V) measurements indicate low densities of interface traps, suggesting a good interface between the silicon nitride buffer layer and the Si substrate. The C-V characteristics show hysteresis that is consistent with the polarization of the SBT film, but opposite to that due to the electron injection/trapping effect. When swept back and forth between -7V and + 7V, a sizable hysteresis window of ± 2V is observed. The results from a single-pulse programming experiment suggest that the switching time is shorter than 8 ns, the shortest pulse available for the experiment. These results are all obtained on samples that exhibit remanent polarizations as low as 0.15 μC/cm2. Fatigue tests show only modest degradation of the memory window after 1011 switching cycles. Results from forming gas annealing experiments indicate no degradation up to 400°C of annealing temperature.

Making silicon nitride film a viable gate dielectric

To extend the scaling limit of thermal SiO/sub 2/ in the ultrathin regime when the direct tunneling current becomes significant, members of this author's research team at Yale University, in collaboration with the Jet Process Corporation, embarked on a program to explore the potential of silicon nitride as an alternative gate dielectric. In this paper, high-quality silicon nitride (or oxynitride) films made by a novel jet vapor deposition (JVD) technique are described. The JVD process utilizes a high-speed jet of light carrier gas to transport the depositing species onto the substrate to form the desired films. The film composition has been determined to consist primarily of Si and N, with some amounts of O and H. Metal-nitride-Si (MNS) capacitors based on the JVD nitride films deposited directly on Si exhibit relatively low densities of interface traps, fixed charge, and bulk traps. The interface traps at the nitride/Si interface exhibit different properties from those at the SiO/sub 2//Si interface in several aspects. In contrast to the conventional CVD silicon nitride, the high-field I-V characteristics of the JVD silicon nitride fit the Fowler-Nordheim (F-N) tunneling theory over four to five orders of magnitude in current, but do not fit at all the Frenkel-Poole (F-P) transport theory. This is consistent with the much lower concentration of electronic traps in the JVD silicon nitride. Results from the carrier separation experiment indicate that electron current dominates the gate current with very little hole contribution. Both theoretical calculation and experimental data indicate that the gate leakage current in JVD silicon nitride is significantly lower than that in silicon dioxide of the same equivalent oxide thickness. The breakdown characteristics of the JVD nitride are also respectable. Compared to their MOSFET counterparts, MNS transistors exhibit reduced low-field transconductance but enhanced high-field transconductance, perhaps due to the presence of border traps. As expected, the JVD silicon nitride films exhibit very strong resistance to boron penetration and oxidation at high temperatures. These properties, coupled with its room-temperature deposition process, make JVD silicon nitride an attractive candidate to succeed thermal SiO/sub 2/ as an advanced gate dielectric in future generations of ULSI devices.

GaAs MOSFET using MBE-grown Ga2O3 (Gd2O3) as gate oxide

An enhancement mode GaAs metal-oxide-semiconductor field effect transistor (MOSFET) with Ga/sub 2/O/sub 3/ (Gd/sub 2/O/sub 3/) as gate dielectric has been successfully fabricated. The low interface density Ga/sub 2/O/sub 3/ (Gd/sub 2/O/sub 3/) oxide and GaAs n-channel layer were grown by in situ molecular beam epitaxy (MBE). The fabricated n-channel MOSFET with 20 nm-thick oxide and 2 /spl mu/m-long gate operated both in enhancement and depletion modes, with a peak transconductance of 40 mS/mm in the enhancement mode. While operating with gate voltages ranging from -1 to 5 V, the device showed a drain current drift of 10.5% for a duration of 10/sup 4/s, a limited amount of hysteresis and negligible dispersion of transconductance from 10 Hz to 1 MHz.