Low Interface State Density Research Articles

Impact of La2O3/InGaAs MOS Interfaces on the Performance of InGaAs MOSFETs

The impact of La2O3/InGaAs MOS interfaces on the performance of InGaAs MOSFETs is systematically investigated. The low interface state density ( ${D}_{{\text {it}}}$ ) of La2O3/InGaAs MOS interfaces is attributable to the formation of an intermixing layer between InGaAs and La2O3, which is rich in As2O3. The La2O3/InGaAs MOSFETs exhibit smaller subthreshold slope with the minimum value of 93 mV/dec than HfO2/InGaAs MOSFETs and smaller carrier trapping properties than Al2O3/InGaAs and HfO2/InGaAs MOSFETs. In the channel mobility analysis, it is found that La2O3/InGaAs MOSFETs have higher Coulomb scattering probability due to the higher oxide fixed charge density and resulting degradation of the channel mobility, while have smaller surface roughness than Al2O3/InGaAs MOSFETs.

Improved Interfacial and Electrical Properties of GaAs Metal–Oxide–Semiconductor Capacitor by Using Fluorine-Plasma-Treated Interfacial Passivation Layer

ZrON gate-dielectric GaAs metal–oxide–semiconductor capacitors with a LaSiON interfacial passivation layer (IPL) and different fluorine-plasma-treatment methods are fabricated and investigated. Compared to using plasma-treating a GaAs surface or no plasma treatment, the sample with plasma-treated IPL exhibits the lowest interface-state density ( ${1.08 \times 10^{12}}$ cm−2eV−1), highest ${k}$ value (18.3) and smallest gate-leakage current ( ${1.62 \times 10^{-5}}$ A/cm2 at ${V_{fb}}$ + 1 V). The fact that plasma-treating IPL can effectively reduce the defect-related Ga/As–O and As–As bonds at GaAs surface and also incorporate more F into the gate stack to passivate the defects in it and at/near IPL/GaAs interface should be responsible for these.

Effect of the Ti/Si ratio of spin coating solutions on surface passivation of crystalline silicon by TiOx–SiOx composite films

Passivation films or antireflection coatings are generally prepared using costly vacuum or high-temperature processes. Thus, we report the preparation of TiOx–SiOx composite films by novel spin coatable solutions for the synthesis of low-cost passivation coating materials. The desired films were formed by varying the mixing ratios of TiOx and SiOx, and the resulting films exhibited excellent surface passivation properties. For the p-type wafer, an optimal effective surface recombination velocity (Seff) of 93 cm/s was achieved at , while a surface recombination current density (J0s) of 195 fA/cm2 was obtained. In contrast, for the n-type wafer, an Seff of 27 cm/s and a J0s of 38 fA/cm2 were achieved at . This excellent surface passivation effect could be attributed to the low interface state density and high positive fixed charge density. Furthermore, the thickness of the interfacial SiOx layer was determined to be important for obtaining the desired surface passivation effect.

Properties of SiO<sub>2</sub>/4H-SiC Interfaces with an Oxide Deposited by a High-Temperature Process

This work reports on the physical and electrical characterization of the oxide/semiconductor interface in MOS capacitors with the SiO2 layer deposited by a high temperature process from dichlorosilane and nitrogen-based vapor precursors and subjected to a post deposition annealing process in N2O. Low interface state density (Dit ≈ 9.0×1011cm-2eV-1) was found at 0.2 eV from EC, which is comparable to the values typically obtained in other lower temperature deposited oxides (e.g., TEOS). A barrier height of 2.8 eV was derived from the Fowler-Nordheim plot, very close to the ideal value expected for SiO2/4H-SiC interface. Basing on these preliminary results, the integration in MOSFETs devices can be envisaged.

Suppressed charge trapping characteristics of (NH4)2Sx passivated GaN MOS device with atomic layer deposited HfAlOx gate dielectric

The charge trapping behaviors of ammonium poly-sulfide, (NH4)2Sx, passivated GaN MOS device with atomic layer deposited HfAlOx gate dielectric and DC-sputtered TiN gate electrode are investigated and compared with those of GaN MOS device with hydrochloric acid, HCl, passivation. Compared to non-S passivated device, higher peak capacitance (>20% @1MHz), reduced frequency dispersion (~30% ↓), lower hysteresis (~34% ↓), higher breakdown (1.3×), lower stress induced flat-band voltage (VFB) shift (~30% ↓), and lower interface state density (Dit), stronger immunity Dit generation (ΔDit) against gate bias voltage are attained with S-passivated device. Further improved characteristics are observed with post deposition annealing at 400°C for 10min. These behaviors are mainly attributed to higher bond strength energy of SO and SN than those of ClO and ClN bonds.

Ultrahigh-Temperature Oxidation of 4H-SiC(0001) and an Impact of Cooling Process on SiO<sub>2</sub>/SiC Interface Properties

This paper reviews our recent work on ultrahigh-temperature oxidation of 4H-SiC(0001) surfaces. Our rapid thermal oxidation experiments demonstrated the reaction-limited linear growth at temperatures ranging from 1200 to 1600°C. The Arrhenius plot of linear growth rate of thermal oxidation can be fitted by a linear line, and the activation energy of oxide growth in dry O2 oxidation was estimated to be 2.9 eV. We also found that unintentional oxidation during the cooling down process severely degrades SiO2/SiC interface properties, resulting in positive flatband voltage shift (VFB) and hysteresis in capacitance-voltage (C-V) characteristics regardless of oxidation temperature. By effectively suppressing oxide growth during the cooling process, we have clarified that SiO2/SiC interface properties depend on oxidation temperature and the lowest interface state density was obtained for the oxide formed at 1450°C.

Reduction of slow trap density of Al2O3/GeOx/n-Ge MOS interfaces by inserting ultrathin Y2O3 interfacial layers

The realization of Ge gate stacks with thin equivalent oxide thickness (EOT), low interface state density (Dit) and small hysteresis is a crucial issue for Ge CMOS. In this study, we propose a new Al2O3/ultrathin Y2O3/GeOx/Ge MOS interface, formed by atomic layer deposition (ALD) Al2O3/Y2O3/Ge MOS structures with plasma post oxidation (PPO) for introducing Y into GeOx and mitigating slow trapping. Both Dit and slow trap density (ΔNst) in the Al2O3/Y2O3/Ge system are reduced by PPO. A 1.5-nm-thick Al2O3/0.63-nm-thick Y2O3/GeOx/Ge interface can provide a 36% lower amount of ΔNst at Eox of 3×106V/cm with maintaining similar levels of Dit than the control Al2O3/GeOx/Ge interface. It is found that the optimum Y2O3 thickness exists for minimizing ΔNst.

The Effect of Defects on Time Dependent Dielectric Breakdown Acceleration in TiN/ZrO2/Al2O3/p-Ge Gate Stacks

Introduction of a thin GeO2 as the interfacial layer (IL) seems to be beneficial for formation of high-k gate stacks on germanium substrate. The thickness of GeO2/GeOx impacts the overall equivalent oxide thickness (EOT) because of its low dielectric constant compared to high-k layer. Current trends indicate that the formation of appropriate thickness of GeOx or GeO2 between high-k and Ge substrate seems to have low interface state density (D it). Since ZrO2 showed lower leakage current than HfO2 with similar dielectric high-k stack, ZrO2/Al2O3 bilayer as gate dielectric is becoming popular. Even though excellent gate stacks on germanium substrate has been demonstrated the reliability and the impact of interfacial layer is still unknown. This work investigates the p-Ge/Al2O3/ZrO2/TiN gate stacks with thin GeO2 or GeOx layer, formed when the gate stack was exposed to pre- or post-deposition slot plane antenna plasma oxidation (SPAO). The post Al2O3/ZrO2 deposition SPAO forms relatively thicker GeO2 and post Al2O3 deposition SPAO forms thinner GeO2 whereas pre-deposition SPAO forms thin fragmented GeOx layer at the interface. We have observed that the relatively thicker GeO2 interfacial layer formed after the post Al2O3/ZrO2 deposition SPAO degraded faster during time dependent dielectric breakdown (TDDB) measurements on substrate injection mode compared to the thin GeO2 or GeOx interfacial layers (Fig. 1). The improvement in TDDB degradation for thinner interfacial layer thickness suggests that electrons tunnel through the thinner GeOx IL, and TDDB measured the quality of Al2O3 rather than IL. The TDDB characteristics in gate injection mode suggests that the SPAO can significantly affect the TDDB characteristics GEI mode (Fig. 1). The SPAO treatment effectively removes the trap centers in ZrO2 and Al2O3 layers when SPAO was performed after the gate stack deposition. By employing carrier transport mechanisms as a function of temperature in both gate and substrate injection mode we were able to identify the traps that contributes to the TDDB degradation. The trap center (f t1 = 0.13 eV) observed in the ZrO2 when ZrO2 is not subjected to the SPAO, i.e. pre-deposition SPAO. This trap f t1 (0.13 eV) was eliminated for post Al2O3/ZrO2 deposition SPAO. While defects in the ZrO2 layer determines the TDDB characteristics in gate injection mode the GeO2 or GeOx interfacial layer thickness determines the TDDB degradation in substrate injection mode. Figure 1

Improvement on the electrical characteristics of Pd/HfO2/6H-SiC MIS capacitors using post deposition annealing and post metallization annealing

HfO2 as a gate dielectric enables high electric field operation of SiC MIS structure and as gas sensor HfO2/SiC capacitors offer higher sensitivity than SiO2/SiC capacitors. The issue of higher density of oxygen vacancies and associated higher leakage current necessitates better passivation of HfO2/SiC interface. Effect of post deposition annealing in N2O plasma and post metallization annealing in forming gas on the structural and electrical characteristics of Pd/HfO2/SiC MIS capacitors are reported in this work. N2O plasma annealing suppresses crystallization during high temperature annealing thereby improving the thermal stability and plasma annealing followed by rapid thermal annealing in N2 result in formation of Hf silicate at the HfO2/SiC interface resulting in order of magnitude lower density of interface states and gate leakage current. Post metallization annealing in forming gas for 40min reduces interface state density by two orders while gate leakage current density is reduced by thrice. Post deposition annealing in N2O plasma and post metallization annealing in forming gas are observed to be effective passivation techniques improving the electrical characteristics of HfO2/SiC capacitors.

Improved Interfacial and Electrical Properties of GaAs MOS Capacitor With LaON/TiON Multilayer Composite Gate Dielectric and LaON as Interfacial Passivation Layer

GaAs metal–oxide–semiconductor capacitors are fabricated by alternately depositing La oxynitride (LaON)/TiON or TiON/LaON or first depositing a LaON interlayer and then alternately depositing LaON/TiON, and their interfacial and electrical properties are investigated and compared. Experimental results show that the sample with LaON interlayer exhibits better interface quality and electrical performance than the other two samples: lower interface-state density ( $1.05 \times 10^{12}$ cm $^{-2}$ eV $^{-1})$ , smaller gate leakage current ( $2.33 \times 10^{-5}$ A/cm2 at $\text{V}_{\mathrm {fb}} + 1$ V), larger equivalent dielectric constant (25.3), and better high-field reliability. The involved mechanism lies in the fact that the LaON interlayer on the GaAs surface can effectively reduce the defective states at/near the interface by blocking the Ti/O in-diffusion and As/Ga out-diffusion, thus improving the interfacial and electrical properties of the device.

A crystalline oxide passivation on In0.53Ga0.47As (100)

The passivation of In0.53Ga0.47As surfaces is highly desired for transistor performance. In this study, the feasibility of a crystalline oxide passivation on In0.53Ga0.47As (100) is demonstrated experimentally. The (3 × 1) and (3 × 2) crystalline oxide reconstructions are formed on the de-capped In0.53Ga0.47As (100) surfaces through the control of the surface oxidation states. By monitoring the evolution of chemical states and associated structures of the In0.53Ga0.47As (100) surfaces upon O2 and subsequent atomic hydrogen exposure, we find that the control of the Ga oxide states is critical to the formation of the crystalline oxide reconstructions. The stability of the crystalline oxide layers upon the atomic layer deposition of HfO2 is investigated as well. Furthermore, the capacitance voltage behavior of metal oxide semiconductor capacitors with an HfO2 dielectric layer reveals that the crystalline oxide reconstructions result in a decrease in the density of interface traps (Dit) from ∼1 × 1013 cm−2 eV−1 to ∼1 × 1012 cm−2 eV−1 compared with the de-capped surface. The crystalline oxide passivation offers a platform to develop In0.53Ga0.47As devices with a low density of interface states.

High-performance GaAs metal-oxide-semiconductor capacitor by using NbAlON as high-k gate dielectric

A GaAs metal-oxide-semiconductor (MOS) capacitor using NbAlON as a gate dielectric with different Nb contents is fabricated. Experimental results show that the k value and crystallization temperature of the AlON dielectric can be improved by Nb incorporation, together with reduction in negative oxide charges. However, the interface quality and gate leakage become poorer as the Nb content increases, as confirmed by TEM and X-ray photoelectron spectroscopy results. Therefore, through comprehensively considering the advantages and disadvantages, the sample with a Nb/(Al+Nb) atomic ratio of 62.5% exhibits the best characteristics: high k value (23.3), low interface-state density (2.7 × 1012 cm−2/eV), small hysteresis (55 mV), small frequency dispersion, and low gate leakage current (2.66 × 10−5A/cm2 at Vfb + 1 V). By comparing with reported GaAs MOS devices with different high-k gate dielectrics, it can be suggested that NbAlON is a promising gate dielectric material to achieve excellent electrical performance for GaAs MOS devices.

Interfacial and Electrical Properties of GaAs Metal-Oxide-Semiconductor Capacitor with ZrAlON as the Interfacial Passivation Layer**Supported by the National Natural Science Foundation of China under Grant Nos 61176100, 61274112 and 61404055.

The ZrTiON gate-dielectric GaAs metal-oxide-semiconductor (MOS) capacitors with or without ZrAlON as the interfacial passivation layer (IPL) are fabricated and their properties are investigated. The experimental results show that the GaAs MOS capacitor with the ZrAlON IPL exhibits better interfacial and electrical properties, including lower interface-state density ( cm−2eV−1), smaller gate leakage current ( A/cm2 at +1 V), smaller capacitance equivalent thickness (1.5 nm), and larger k value (26). The involved mechanisms lie in the fact that the ZrAlON IPL can effectively block the diffusion of Ti and O towards the GaAs surface, thus suppressing the formation of interfacial Ga-/As-oxides and As-As dimers, which leads to improved interfacial and electrical properties for the devices.

Further analysis of high-voltage ZnO varistor prepared from novel chemically aided method

Based on previous work, this study further investigated the high-voltage varistor materials prepared from chemically aided method. Microstructural characterization and electrical measurement results showed that the sample possessed more homogeneous microstructure and ultrahigh drop voltage per grain boundary (Vgb) than the conventional sample. The obtained ultrahigh value of Vgb is connected with the much lower donor concentration (Nd) and density of interface states (NIS) of the samples, which resulted from the increased number of active grain boundaries per unit volume. The improved homogeneous microstructure, together with the smaller grain size and narrower size distribution are essential to obtain high-voltage ZnO varistor.

Passivation of InGaAs interface states by thin AlN interface layers for metal-insulator-semiconductor applications

The passivation of InGaAs by thin AlN layers allows a significant reduction of the interface state density compared to that of the widely used Al2O3/InGaAs structure. The influence of the AlN layer thickness on the interface electrical properties, as well as the role of the post-deposition annealing, was carefully examined. Ultrathin AlN layers (∼1 nm) provide high quality interfacial electrical properties after a mild anneal (400 °C). Thick AlN passivation layers require annealing at higher temperature (500 °C) to achieve low interface states density. Possible explanations of the observed trend are suggested.

Improved interfacial and electrical properties of HfLaON gate dielectric Ge MOS capacitor by NbON/Si dual passivation layer and fluorine incorporation

Ge metal-oxide-semiconductor (MOS) capacitor with HfLaON/(NbON/Si) stacked gate dielectric and fluorine-plasma treatment is fabricated, and its interfacial and electrical properties are compared with its counterparts without the Si passivation layer or the fluorine-plasma treatment. The experimental results show that the HfLaON/(NbON/Si) Ge MOS device treated by fluorine plasma exhibits excellent performance: low interface-state density (4.3 × 1011 cm−2 eV−1), small flatband voltage (0.22 V), good capacitance-voltage behavior, small frequency dispersion and low gate leakage current (4.18 × 10−5 A/cm2 at Vg = Vfb + 1 V). These should be attributed to the suppressed growth of unstable Ge oxides on the Ge surface during gate-dielectric annealing by the NbON/Si dual interlayer and fluorine incorporation, thus reducing the defective states at/near the NbSiON/Ge interface and improving the electrical properties of the device.

Improving Thermal Stability and Interface State Density of High- $\kappa $ Stacks by Incorporating Hf into an Interfacial Layer on p-Germanium

We propose a new HfGeO x interfacial layer (IL) for the high- $\kappa $ gate-stacks on p-type germanium substrate with improved thermal stability as compared with that of conventional GeO x IL. We inserted an additional HfO2 layer after the formation of GeO x in the HfO2/Al2O3/GeO x /Ge gate-stack by using plasma-enhanced atomic layer deposition. Through the use of post-deposition annealing and post-metal annealing, the new system exhibited greater thermal immunity and was stable up to 600 °C. We speculate that the improvement originates from the formation of HfGeO x through the combination of HfO2 and GeO x , according to the thermodynamic data. By incorporating Hf into interfacial layer, the fabricated high- $\kappa $ gate-stack with an equivalent oxide thickness of 1.2 nm, a low interface states density ( $D_{\mathrm {it}}$ ) of approximately $3.3 \times 10^{11}$ eV $^{\mathrm {-1}}$ cm $^{\mathrm {-2}}$ , and an impressive gate leakage current of approximately $ 2.2 \times 10^{\mathrm {-6}}$ A/cm2 at $V_{\mathrm {FB}} -1\text{V}$ .

Modulation of electrical properties and current conduction mechanism of HfAlO/Ge gate stack by ALD-derived Al2O3 passivation layer

HfAlO/Ge gate stack with Al2O3 passivation layer and different Al2O3 concentration in HfAlO layer has been deposited on Ge substrate by atomic layer deposition. Based on measurements from capacitance-voltage and current density-voltage curves, the evolution of the electrical properties of Ge-based MOS capacitors based on HfAlO/Al2O3/Ge gate stack has been determined as functions of precursor ratio and annealing temperature. It has been found that high annealing temperature and high Al2O3 incorporation in HfAlO films can obtain improved electrical properties such as low hysteresis, low flat-band, low flat-band shift and low interface-state density. However, the oxide-charge density obviously increases with rising the annealing temperature and decreasing Al2O3 incorporation in HfAlO film. By analysis and calculation, it can be noted that the samples annealed at 500 °C holds the lowest leakage current density and the change of the precursor ratio has no apparent effect in 500 °C-annealed Ge MOS capacitor. To investigate current conduction mechanism of Ge MOS capacitors employing HfAlO/Al2O3 gate stacks, current density-voltage measurements have been carried out as functions of annealing temperature and precursor ratio. The involved leakage current conduction mechanisms of the as-deposited and 500 °C-annealed HfAlO/Al2O3/Ge MOS capacitors for substrate injection also have been discussed in detail.

Ultrahigh-temperature rapid thermal oxidation of 4H-SiC(0001) surfaces and oxidation temperature dependence of SiO2/SiC interface properties

Ultrahigh-temperature rapid thermal oxidation of 4H-SiC(0001) surfaces in dry O2 ambient was performed at temperatures up to 1700 °C. The temperature dependence of the reaction-limited linear growth rate of a thermal SiO2 layer revealed that not active but passive oxidation is dominant even at 1600 °C, and its activation energy was estimated to be 2.9 eV. We also found that high-temperature oxidation is beneficial in improving SiO2/SiC interface properties, but unintentional oxidation during the cooling down process causes interface degradation. By effectively suppressing the oxide growth during the cooling process, the lowest interface state density was obtained for the oxide formed at 1450 °C.

Electrical, optical, structural and chemical properties of Al2TiO5 films for high-к gate dielectric applications

In search of alternate gate dielectrics for electronic applications, aluminum titanate (Al2TiO5) thin films were deposited at room temperature by DC reactive magnetron sputtering and characterized for their structural, chemical, optical and dielectric properties. To realize the potentiality of these films for gate dielectric applications, we investigated the influence of annealing temperature on these properties. From X-ray photoelectron spectroscopic studies, it has been observed in the as-deposited films that the presence of Al3+ and Ti4+ oxidation states which correspond to Al2O3 and TiO2 respectively. After annealing at 400°C in oxygen ambient, the binding energies of Al 2p, Ti 2p and O 1s were shifted by ~1eV and it remains constant with further increase of annealing temperature from 400 to 800°C. This indicates the formation of an intermediate compound of Al2O3 and TiO2. The extracted Al, Ti and O ratio was 2:1:5 which confirms the formation of Al2TiO5. XRD studies indicate that the as-deposited films were amorphous. After annealing at 400°C, a diffraction peak (200) corresponds to aluminum titanate (Al2TiO5) started appearing, and its intensity increases with increase of annealing temperature. Metal-Oxide-Semiconductor (MOS) capacitors were fabricated and characterized to estimate the dielectric properties of the films. The as-deposited films shows high dielectric constant (к=27.0 at 100kHz) and high leakage current density values (J=0.33A/cm2 at 1MV/cm), high oxide traps (5.5×1013cm−2) and high interface state density (1.5×1013cm−2eV−1). After annealing the films show improved dielectric constant and leakage current density values. The films annealed at 600°C in oxygen ambient show better dielectric constant (к=11.2 at 100kHz) and leakage current density values (J=2.23×10−9A/cm2 at 1MV/cm), low oxide traps (1.4×1012cm−2) and low interface state density (7.1×1011cm−2eV−1) compared with the other films. This suggests that the optimum annealing temperature is required to achieve better device properties.