Low Hardware Complexity Research Articles

Secure VANET Authentication Protocol (SVAP) Using Chebyshev Chaotic Maps for Emergency Conditions

It is crucial to support emergency applications provided by vehicular adhoc network (VANET) through enabling vehicles to quickly access to the infrastructure and consequently request rescue services. Additionally, the communication channels between vehicles and the infrastructure lack various security features due to the inferior wireless characteristics of their environment. However, most of the existing authentication schemes which are used to fix the security drawbacks lead to heavy computations and large storage burdens on the vehicle onboard unit (OBU). These schemes utilize secure channels while distributing the network parameters between the various participants. Yet, it is not efficient to establish secure channels during the interactions between entities. Furthermore, lightweight cryptography is an efficient security solution which is adequate for OBU to maintain a reasonable efficiency with low computational and communication costs. Two basic demerits for lightweight authentication protocols are highlighted as follows: Firstly, symmetric key-based authentication protocols dismiss achieving non-repudiation feature, leading to several security attacks in VANET. Secondly, public key-based authentication schemes are relied on elliptic curve cryptography (ECC) which makes the protocol implementation more difficult. Hence, this paper introduces a novel authentication protocol that utilizes Chebyshev chaotic maps to secure connectivity between the vehicles and infrastructure without using secure channels to distribute the network parameters. The new protocol combines the concept of the symmetric key cryptography with the public key signature to satisfy both the lightweight property and non-repudiation feature. Thus, this protocol introduces a novel network model which is the lowest hardware complexity, compared with others. The performance analysis is performed by Wolfram Mathematica, proving that the proposed protocol is superior in terms of security and performance aspects; its computation and storage costs of OBU are enhanced with 24.09% and 16.99%, respectively, compared to the most competing scheme. Besides, the Scyther simulation confirms the security of the protocol.

Direction-of-Arrival Estimation for Large Antenna Arrays With Hybrid Analog and Digital Architectures

The large antenna arrays with hybrid analog and digital (HAD) architectures can provide a large aperture with low cost and hardware complexity, resulting in enhanced direction-of-arrival (DOA) estimation and reduced power consumption. This paper investigates the trade-off between DOA estimation and power consumption in large antenna arrays with HAD architectures. Particularly, the DOA estimation problem of fully-connected, sub-connected (SC), and switches-based (SE) hybrid architectures is formulated into a unified expression, with the compression matrix in a time-varying form. Based on this model, we derive a dynamic maximum likelihood (D-ML) estimator that is suitable for both HAD and conventional fully digital (FD) structures, and the closed-form expression of Cramér-Rao bound (CRB) to evaluate the performance limit of the D-ML estimator for different HAD structures. The theoretical CRB analysis in the single-source case reveals that, the SC structure has the ability to achieve approximately the same performance as the FD structures at DOAs around zero, but suffers from the inherent angle ambiguity because of the antenna grouping. In addition, we propose a dynamic SC (D-SC) structure that is proved to eliminate the angle ambiguity with time-varying phase shifters, and a switch optimization (SWO) algorithm to minimize the CRB of SE structures. Finally, we introduce a new metric, DOA efficiency, to measure the trade-off between the DOA estimation performance and power consumption of different structures. Simulation results verify our theoretical analysis and the superiority of the proposed D-SC structure and the SWO algorithm.

Fuzzy System Design Using Current Amplifier for 20 nm CMOS Technology

In the recent decade, different researchers have performed hardware implementation for different applications covering various areas of experts. In this research paper, a novel analog design and implementation of different steps of fuzzy systems with current differencing buffered amplifier (CDBA) are proposed with a compact structure that can be used in many signal processing applications. The proposed circuits are capable of wide input current range, simple structure, and are highly linear. Different electrical parameters were compared for the proposed fuzzy system when using different membership functions. The novelty of this paper lies in the electronic implementation of different steps for realizing a fuzzy system using current amplifiers. When the power supply voltage of CDBA is 2 V, it results in 155 mW, power dissipation; 4.615 KΩ, input resistance; 366 KΩ, output resistances; and 189.09 dB, common-mode rejection ratio. A 155.519 dB, voltage gain, and 0.76 V/μs, the slew rate is analyzed when the power supply voltage of CDBA is 3 V. The fuzzy system is realized in 20 nm CMOS technology and investigated with an output signal of high precision and high speed, illustrating that it is suitable for real-time applications. In this research paper, a consequence of feedback resistance on the adder circuit and the defuzzified circuit is also analyzed and the best results are obtained using 100 K resistance. The structure has a low hardware complexity leading to a low delay and a rather high quality.

Joint Identification, Detection and Channel Estimation in Industrial IoT

Rapid identification and analysis of faulty or degraded sensors and devices are key challenge in Industrial Internet of Things (IIoT). Wireless communication is emerging as a viable solution to support the massive sensors and devices with sporadic fault due to low construction cost, low latency and high reliability. For future massive machine-type communications, Media-Based Modulation (MBM) is regarded as a promising technique to achieve high data rate with low-complexity hardware implementation. In this paper, only the sensors or devices with fault are activated to transmit data which use MBM to carry more fault information. A compressive sensing (CS)-based joint adaptively fault machine identification, data detection and channel estimation algorithm is proposed by taking full consideration of the prior information such as sparsity structure and physical variables correlation. The simulation results demonstrate that the proposed algorithm is superior to the state-of-the-art identification and detection methods.

Adaptive Scheduling for Joint Communication and Radar Detection: Tradeoff Among Throughput, Delay, and Detection Performance

In this paper, we focus on the tradeoff design between communication and radar detection for a joint communication and radar (CommRadar) system by leveraging a low-complexity hardware architecture. To achieve this, we exploit the communication traffic diversity to design an adaptive scheduling policy. Through adjusting the CommRadar mode selection, radar steering direction and communication user scheduling, and time allocation between communication and radar detection, we could better utilize the un-occupied transmission time to improve radar detection performance when the data traffic is light, and balance the time allocation between communication and radar detection when the data traffic is heavy. Moreover, for our adaptive scheduling method, we have provided a quantitative performance bound for data throughput, queueing delay, and radar detection performance of both short-term and long-term. By conducting extensive simulation studies, we have demonstrated that our method could greatly reduce the communication performance loss when integrating the radar functionality, while still guaranteeing radar detection performance.

Unambiguous BPSK-like CSC Method for Galileo Acquisition

Galileo will be Europe’s own Global Navigation Satellite System (GNSS), which is aiming to provide highly accurate and guaranteed positioning services. Galileo E1 system has a code period of 4ms which is quadruple that of GPS C/A code. In other words, due to the large number of hypotheses in code phase at acquisition stage, a longer searching time or more hardware resource is required. It is difficult to acquire Galileo signal because of longer code length and the multiple peaks of autocorrelation function of BOC modulation. In this paper, the cyclically shift-and-combine (CSC) and BPSK-like architectures are employed to resolve the unambiguous acquisition for BOC modulation and acquires these satellite signals with hardware complexity reduction. The concept of CSC code is to modify the code structure and shorten the code period such that the acquisition burden can be decreased. Simulation results show that our proposed search algorithm can provide better performances in terms of low hardware complexity for acquiring these satellite signals and detection probability at the low value of CNR.

Underwater navigation using a single beacon based on the time delays of the direct signals and the surface-reflected signals

Underwater navigation using a single beacon has been widely discussed and used because of the lower hardware complexity and installation accuracy compared with the long baseline (LBL) and the ultra-short baseline (USBL) methods, respectively. The existing navigation methods are mainly dependent on the time delays of the direct signals (DS) from the beacon to the autonomous underwater vehicle (AUV). Considering that the underwater acoustic channel is a multipath channel, this paper proposes a novel single beacon navigation method based on the time delays of the direct signals and the surface-reflected signals (SRS). The precision analysis proves that the proposed DS-SRS-based method can achieve a higher navigation precision than the DS-based method. Moreover, a tracking method based on the DS and the SRS is also presented to smooth the navigation results, and the corresponding observability analysis is given. Several simulations validate the effectiveness of the proposed methods.

FRaC: FMCW-Based Joint Radar-Communications System Via Index Modulation

Dual function radar communications (DFRC) systems are attractive technologies for autonomous vehicles, which utilize electromagnetic waves to constantly sense the environment while simultaneously communicating with neighbouring devices. An emerging approach to implementing DFRC systems is to embed information in radar waveforms via index modulation (IM). Implementation of DFRC schemes in vehicular systems gives rise to strict constraints in terms of cost, power efficiency, and hardware complexity. In this paper, we extend IM-based DFRC systems to utilizing sparse arrays and frequency modulated continuous waveforms (FMCWs), which are popular in automotive radar for their simplicity and low hardware complexity. The proposed FMCW-based radar-communications system (FRaC) operates at reduced cost and complexity by transmitting with a reduced number of radio frequency modules, combined with narrowband FMCW signalling. This is achieved via array sparsification in transmission, formulating a virtual multiple-input multiple-output array by combining the signals in one coherent processing interval, in which the narrowband waveforms are transmitted in a randomized manner. Performance analysis and numerical results show that the proposed radar scheme achieves similar resolution performance compared with a wideband radar system operating with a large receive aperture, while requiring less hardware overhead. For the communications subsystem, FRaC achieves higher rates and improved error rates compared to dual-function signalling based on conventional phase modulation.

Multilayer Extreme Learning Machine as Equalizer in OFDM-based Radio-over-fiber Systems

Mobile/wireless networks aim to support diverse services with numerous and sophisticated requirements, such as energy efficiency, spectral efficiency, negligible latency, robustness against time and frequency selective channels, low hardware complexity, among others. From the central station to the base stations, radio-over-fiber orthogonal frequency division multiplexing (RoF-OFDM) schemes with direct-detection are then implemented. Unfortunately, laser phase noise, chromatic fiber dispersion, and carrier frequency offset impair the orthogonality of the subcarriers; hence, deteriorating the performance of the RoF-OFDM system. In order to take all the processing tasks to the cognitive level (the last goal in the telecommunication industry), various extreme learning machines (ELMs), composed by only a single hidden layer, have been recently adopted as equalizers. The reason behind this trend comes from the lower computational complexity, higher detection accuracy, and minimum human intervention of the ELM algorithms. In this article, we introduce a multilayer ELM-based receiver for RoF schemes transmitting phase-correlated OFDM signals affected by phase and frequency errors. Results report that by appropriately setting the hyper-parameters of the multilayer ELMs, the ELM with 3 hidden layers outperforms most of the ELMs reported in the literature (the ELM with 2 hidden layers, original ELM, regularized ELM, and 2 fully-independent ELMs defined in the real domain), as well as the benchmark pilot-assisted equalizer in terms of bit error rate. Nevertheless, this benefit comes with excessive computational cost. Finally, we show that the fully-complex ELM is still the best equalizer taking into account several key metrics.

Performance Analysis of Dipole Antenna Based Planar Arrays With Mutual Coupling and Antenna Position Error in mmWave Hybrid System

In this work, a hybrid architecture called fully connected sub-array (FCSA) is considered for uplink data decoding with mutual coupling and space constraints at the base station (BS). The above architecture achieves the same system performance with a lower hardware complexity than a fully connected array. The packing of many antenna elements on a small surface area leads to the mutual coupling effect. Moreover, having antenna elements at the BS with finite directivity is more practical than having isotropic antenna elements at the BS. In the present work, we have considered uplink data decoding with dipole antennas arranged in a uniform planar array (UPA) grid at the BS with the error in separation between the antenna elements and mutual coupling as additional impairments. An approximate expression for the mutual coupling matrix (MCM) is derived and verified. A geometry-based stochastic model (GBSM) for the channel is considered between the user equipment (UE) and the BS. The performance of the hybrid architecture in terms of spectral efficiency (SE) and bit error rate (BER) of the system, with the mutual coupling effect and antenna separation error, is analyzed. Numerical simulations show that when the BS has no information on the MCM, SE and the system's BER performances with the FCSA architecture degrade. In the absence of any information on the coupling effect, the system performs better when a more extensive array size is used at the BS. Both the SE and BER degraded when longer dipoles were used in the array.

Editorial to Special Issue “Remote Sensing Data Compression”

A huge amount of remote sensing data is acquired each day, which is transferred to image processing centers and/or to customers. Due to different limitations, compression has to be applied on-board and/or on-the-ground. This Special Issue collects 15 papers dealing with remote sensing data compression, introducing solutions for both lossless and lossy compression, analyzing the impact of compression on different processes, investigating the suitability of neural networks for compression, and researching on low complexity hardware and software approaches to deliver competitive coding performance.

Portable and Highly Versatile Impedance Meter for Very Low Frequency Measurements

Electrical Impedance Spectroscopy (EIS) is a characterization technique that is gaining more and more importance in various fields of research and applications. The frequency range of investigation varies according to the type of application. In some fields (biology, medicine, energy) it is useful to be able to perform measurements at very low frequency values (down to a few mHz or even below). While impedance meters operating at frequencies in the range from a few tens of Hz up to a few MHz can be regarded as quite standard pieces of instrumentation commonly available in many laboratories, instrumentation for measurements at very low frequencies, although commercially available, is less common. The subject of this work is the design, realization and testing of a low frequency impedance measurement platform that has the advantage of being portable, rather inexpensive, and yet highly versatile. In our approach, we exploit a personal computer and a soundboard as a powerful system for digital signal generation and analysis that, with the help of low complexity and low-cost external hardware and a public domain software for the implementation of the core system, allow to tailor the platform for targeting specific applications with minimal effort. As an example, we will demonstrate the application of the system to the investigation of polypyrrole-based supercapacitor structures.

Theoretical total harmonic distortion evaluation based on digital to analogue converter mismatch to improve the linearity of successive approximation register analogue to digital converter

Mismatch in the binary-weighted capacitive digital-to-analog converter (DAC) greatly affects the linearity of the successive-approximation-register (SAR) ADC by deteriorating the total harmonic distortion (THD). In this study, a theoretical relationship between the THD and the mismatch error of DAC array in SAR ADC is derived through discrete Fourier transform (DFT) analysis of the time-based integral error (TIE) of the ADC's output codes, which has no specific requirement on the type of the input signals. Guided by the theoretical THD expression, the trade-off among the linearity, design complexity, power consumption and chip area can be balanced easily. The presented formula is verified by a design example of 12-bit SAR ADC with dynamic-element-matching (DEM) technique, where the 3-bit LSBs from the SAR ADC are used to generate the randomised DEM state according to the previous THD evaluation. The linearity is enhanced by 9 dB approximately with very low hardware complexity and extremely small extra power consumption of 2 μW.

Boosted Model Tree-Based Behavioral Modeling for Digital Predistortion of RF Power Amplifiers

In this article, we propose a new behavioral modeling approach, called boosted model tree, to characterize and compensate for the complex nonlinear distortions induced by wideband high-efficiency radio frequency power amplifiers. With the proposed model, the input data are classified into different zones by decision trees and each zone is assigned separate submodels. We also employ a model boosting technique to build multiple parallel tree structures that jointly model the desired nonlinear behavior. By designing dedicated optimization procedures, both tree structures and submodel coefficients can be efficiently identified. It is demonstrated that the combination of piecewise and parallel structures provides a powerful and hardware-efficient way to model nonlinear memory effect and cross terms. Based on the experimental results, the proposed method can achieve improved linearization performance with low hardware complexity under challenging wideband predistortion scenarios.

Automatic epileptic seizure detection approach based on multi-stage Quantized Kernel Least Mean Square filters

Epilepsy is one of the most common neurological disorders of the brain all over the world. For its detection, Electroencephalogram (EEG) is an important noninvasive diagnostic approach. This paper proposes a new automated real-time approach for EEG epileptic seizure detection based on serial concatenation of Quantized Kernel Least Mean Square (QKLMS) adaptive filters. The QKLMS filter is employed in the proposed system to achieve accurate real-time diagnosis with low hardware complexity. In the proposed serial concatenation filter design, the energy of prediction signal is investigated to detect the seizure interval on the EEG records and to classify healthy, epileptic inter-ictal, and epileptic ictal cases. The Grey Wolf Optimizer (GWO) algorithm is employed to find the optimum values of the energy threshold and the parameters of the QKLMS algorithm. The performance of the proposed QKLMS technique is compared with other adaptive filters, and the results reveal the superior performance of the QKLMS algorithm. The proposed system is examined with real EEG records taken from the Bonn University database, and the experimental results show that the proposed epileptic seizure detection system outperforms other state-of-the-art systems with an accuracy of 97.88 %, sensitivity of 98.80 %, specificity of 97.65 %, and computational time of 0.58 sec. This demonstrates that the proposed approach can be used to assist neurologists in enhancing the accuracy of epileptic seizure detection and speeding-up the diagnosis process without the need for visual inspection or analysis of a large volume of EEG data.

Amplitude, phase, and quadrant (APQ) modulation for indoor visible light communications

The main challenge in visible light communications (VLC) is the low modulation bandwidth of light-emitting diodes (LEDs). This forms a barrier towards achieving high data rates. Moreover, the implementation of high order modulation schemes is restricted by the requirements of intensity modulation (IM) and direct detection (DD), which demand the use of real unipolar signals. In this paper, we propose a novel amplitude, phase and quadrant (APQ) modulation scheme that fits into the IM/DD restrictions in VLC systems. The proposed scheme decomposes the complex and bipolar symbols of high order modulations into three different symbols that carry the amplitude, phase and quadrant information of the intended symbol. The constructed symbols are assigned different power levels and are transmitted simultaneously, i.e. exploiting the entire bandwidth and time resources. The receiving terminal performs successive interference cancellation to extract and decode the three different symbols, and then uses them to decide the intended complex bipolar symbol. We evaluate the performance of the proposed APQ scheme in terms of symbol-error-rate and achievable system throughput for different setup scenarios. The obtained results are compared with generalized spatial shift keying (GSSK). The presented results show that APQ offers a higher reliability compared to GSSK across the simulation area, while providing lower hardware complexity.

A High-Accuracy Stochastic FIR Filter with Adaptive Scaling Algorithm and Antithetic Variables Method

Digital filter is an important fundamental component in digital signal processing (DSP) systems. Among the digital filters, the finite impulse response (FIR) filter is one of the most commonly used schemes. As a low-complexity hardware implementation technique, stochastic computing has been applied to overcome the huge hardware cost problem of high-order FIR filters. However, the stochastic FIR filter (SFIR) scheme suffers from long processing latency and accuracy degradation. In this paper, the bit stream representation noise is theoretically analyzed, and an adaptive scaling algorithm (ASA) is proposed to improve the accuracy of SFIR with the same bit stream length. Furthermore, a novel antithetic variables method is proposed to further improve the accuracy. According to the simulation results on a 64-tap FIR filter, the ASA and AV methods gain 17 dB and 6 dB on the signal-to-noise ratio (SNR), respectively. The hardware implementation results are also presented in this paper, which illustrates that the proposed ASA-AV-SFIR filter increases 4.6 times hardware efficiency with respect to the existing SFIR schemes.

VLSI Implementation of Multi-Channel ECG Lossless Compression System

Electrocardiogram (ECG) is used to record the electrical activity of heart. If the instrument monitoring the signal for a long time, it will produce large amount of data. So, the effective lossless ECG compression system can help to reduce the storage space. This brief presents a hardware architecture of multi-channel lossless ECG compression system. The system is based on the algorithm including multi-channel linear prediction and adaptive linear prediction. Also, Golomb rice code (GRC) is used for entropy coding. The hardware implementation has been designed with low hardware complexity usage while using optimum hardware resources. And the architecture can process multiple channels in parallel that can obtain the high throughput. PTB database has been used for verification and testing purposes. This design was implemented in TSMC 180nm. The implementation results show the gate count is 476K and power consumption is 69.18μW while working frequency is 1 KHz.

A New Approach for a Unified Architecture for Type IV DCT/DST with an Efficient Incorporation of Obfuscation Technique

This paper aims at solving one challenging problem in designing VLSI chips, namely, the security of the hardware, by presenting a new design approach that incorporates the obfuscation technique in the VLSI implementation of some important DSP algorithms. The proposed method introduces a new approach in obtaining a unified VLSI architecture for computing type IV discrete cosine transform (DCT-IV) and type IV discrete sine transform (DST-IV), with an efficient integration of the obfuscation technique, while maintaining low overheads. The algorithms for these two transforms were restructured in such a way that their structures are fairly similar, and thus they can be implemented on the same VLSI chip and on the same hardware with very few modifications, with the latter being attributed to the pre-processing and post-processing stages. The design proposed uses the regular and modular structures, which are named quasi-correlation, and the architecture is inspired by the paradigm of the systolic array architecture. Thus, the introduced design benefits the security, for the hardware, and also the advantages introduced by the use of the regular and modular structures. A very efficient, unified VLSI architecture for type IV DCT/DST can be obtained, which allows the computation of the two algorithms on the same hardware, allowing an efficient incorporation of the obfuscation technique with very low overheads, and it can be very efficiently implemented, offering high-speed performances and low hardware complexity, with the latter being attributed to the efficient use of the hardware resources for the computation of these two algorithms.

Novel Low-Complexity Polynomial Multiplication Over Hybrid Fields for Efficient Implementation of Binary Ring-LWE Post-Quantum Cryptography

Post-quantum cryptography (PQC) refers to the cryptosystem that can resist the attacks launched from mature quantum computers in the not far future and has recently gained intensive attention from the research community as most of the existing public-key cryptosystems are vulnerable to attacks from quantum computers. Ring-Learning-with-Errors (Ring-LWE)-based scheme is an essential type of the lattice-based PQC due to its strong security proof and ease of implementation. As the latest variant of the Ring-LWE, the binary Ring-LWE (BRLWE)-based scheme possesses even smaller computational complexity and thus is more suitable for resource-constrained applications. However, the existing works have not well covered various aspects related to this new scheme, especially on the low-complexity hardware implementation. In this paper, we aim to present a novel implementation of the BRLWE-based scheme on the hardware platform with very low-complexity with this point of view. To carry out the specified work in a successful manner, we have proposed mainly four layers of coherent interdependent efforts: (i) we have provided the necessary algorithmic derivation process in detail to formulate the desired algorithm for the polynomial multiplication over hybrid fields, which is the major arithmetic component of the BRLWE scheme; (ii) we have presented the corresponding hardware architecture in a thorough format with sufficient description of the internal structures; (iii) we have also provided the complexity analysis and implementation-based comparison to demonstrate the superior performance of the proposed polynomial multiplication over the state-of-the-art design; (iv) finally, we have extended the proposed low-complexity polynomial multiplication to the major operational phase of the BRLWE scheme. We have shown that the proposed BRLWE structure involves significantly lower area-time complexities over the existing design, e.g., the proposed design has at least 66.01% less area-delay product (ADP) than the newly reported (Straix V device). Overall, the proposed design and implementation strategies are highly efficient, and the proposed BRLWE structure is desirable for many emerging applications.