Low Gate Leakage Current Density Research Articles

High‐Current‐Density Enhancement‐Mode Ultrawide‐Bandgap AlGaN Channel Metal–Insulator–Semiconductor Heterojunction Field‐Effect Transistors with a Threshold Voltage of 5 V

Enhancement‐mode ultrawide‐bandgap Al0.65Ga0.35N/Al0.4Ga0.6N metal–insulator–semiconductor heterojunction field‐effect transistors are demonstrated using fluorine‐plasma treatment for threshold voltage control and Al2O3 as gate dielectric. The device exhibits a threshold voltage of 5 V, a maximum drain current density of 105 mA mm−1, and a transconductance of 19 mS mm−1. In addition, the capability to achieve low off‐state current density at 3–4 × 10−9 mA mm−1, an exceptionally low gate leakage current density of 1.4 × 10−8 mA mm−1 even at a high forward gate bias of VGS = 12 V, and a current on/off ratio >1010 is shown. Small signal measurement shows that the device has a unity current gain cutoff frequency fT of 3.8 GHz and power gain cutoff frequency fmax of 4.5 GHz.

Charge trap layer enabled positive tunable Vfb in β -Ga2O3 gate stacks for enhancement mode transistors

β-Ga2O3 based enhancement mode transistor designs are critical for the realization of low loss, high efficiency next generation power devices with rudimentary driving circuits. A large positive flatband voltage (Vfb) of 10.6 V in β-Ga2O3 metal-oxide-semiconductor capacitors, with the ability to fine-tune it between 3.5 V and 10.6 V, using a polycrystalline AlN charge trap layer has been demonstrated. This can enable enhancement mode operation over a wide doping range. An excellent Vfb retention of ∼97% for 104 s at 55 °C was exhibited by the gate stacks after charge trapping, hence reducing the requirement of frequent charge injection cycles. In addition, low gate leakage current density (Jg) for high negative gate voltages (Vg ∼−60 V) indicates the potential of this gate stack to enable superior breakdown characteristics in enhancement mode transistors.

NrGO Floating Gate/SiOXNY Tunneling Layer Stack for Nonvolatile Flash Memory Applications

This paper presents an ultra–thin silicon oxynitride (SiOXNY, 4 nm) tunneling layer, nitrogen functionalized reduced graphene oxide (NrGO, 3–5 layer) floating gate (FG) and poly (methyl methacrylate) (PMMA, 60 nm) blocking layers based Al/PMMA/NrGO/SiOXNY/p–Si/Au, non–volatile flash memory (NVFM) structures. The ultra–thin SiOXNYhelps in improving the interface with Si, resulting in lower gate leakage current density and considerable enhanced retention characteristics. The nitrogen engineered GO followed by reduction to NrGO under UV illumination attributes to the modification of the physiochemical properties, hence beneficial for non-volatile memory applications. The uniform, stress free and low temperature processing advocates the potential of PMMA as blocking layer for improved memory characteristics. The electrical characterizations on the fabricated Al/PMMA/NrGO/SiOXNY/p–Si/Au gate stack demonstrates a memory window ( ${\delta }\text{W}$ ) of ~1.25 V @ ± 3 V and ~2.6 V @ ± 5 V, low gate leakage current density (J) ~10 nA/cm2@ −1 V, retention $\sim 3 \times 10^{11}$ sec (> 10 years with extrapolation) and endurance of more than 100 cycles.

Low Equivalent Oxide Thickness and Leakage Current of pGe MOS Device by Removing Low Oxidation State in GeOx With H2 Plasma Treatment

A low equivalent-oxide-thickness of 0.58 nm and a low gate leakage current density of $\sim 2\times 10^{-{5}}$ A/cm2 at VG = VFB – 1 V in p-substrate Ge (pGe) MOS device can be simultaneously achieved by a hydrogen plasma (H*) treatment on GeO2 interfacial layer (IL). It is found that the removal of GeOx with low oxidation state in GeO2 IL play crucial roles on electrical characteristics of pGe MOS device. Through a H* treatment, the electrical and reliability characteristics are improved by a GeO2 IL with high oxidation state. Therefore, a GeO2 IL with H* treatment is promising for high performance pGe MOS devices.

On the Threshold Voltage and Performance of ZnO-Based Thin-Film Transistors with a ZrO2 Gate Dielectric

In the past few years, thin-film transistor (TFT) technology has experienced a rapid transition from amorphous silicon- (a-Si:H) and polysilicon-based TFTs to zinc oxide (ZnO)-based TFTs, and because of this transition, transparent TFTs have become a reality. In ZnO TFTs, which operate in accumulation mode, the threshold voltage has remained ambiguous due to the existence of grain boundary traps in the polycrystalline semiconducting channel. This paper provides an analytical relationship of threshold voltage with grain boundary trap density by assuming the grain boundary is a continuous one-dimensional line charge. A high density of grain boundary traps leads to a high threshold voltage. However, its effect can be minimized by employing a high-κ gate dielectric. In this work, we have demonstrated the reduction of threshold voltage in a ZnO TFT by using ZrO2 as a gate dielectric. A study of a ZnO/ZrO2 interface is reported by fabricating a metal–insulator–semiconductor capacitor structure. This interface is studied using capacitance–voltage (C–V) and current–voltage (I–V) characteristics. The ZnO TFT with a ZrO2 gate dielectric exhibits a low subthreshold slope (131 mV decade−1), low gate leakage current density (2.94 × 10−7 A cm−2) and low threshold voltage (1.2 V). However, it also exhibits a counterclockwise hysteresis of −1.4 V, which is attributed to the existence of oxygen vacancies.

Alternate lanthanum oxide/silicon oxynitride-based gate stack performance enhancement due to ultrathin oxynitride interfacial layer for CMOS applications

Metal–insulator–semiconductor (MIS)-based Pt/La2O3/SiOXNY/p-Si/Pt structures are fabricated using ultrathin silicon oxynitride (SiOXNY ~ 4 nm) interfacial layer underneath of lanthanum (III) oxide (La2O3 ~ 7.8 nm) with Pt as gate electrode for CMOS applications. Capacitance–voltage (C–V) characteristics of Pt/La2O3/SiOXNY/p-Si/Pt at 500 kHz showed a positive gate bias threshold voltage (Vth) shift of ~ 0.43 V (~ 43.8%) and flat-band (Vfb) shift of ~ 1.24 V (~ 42.3%) as compared to Pt/La2O3/p-Si/Pt MIS structures, attributing to the reduction in effective positive oxide charges at La2O3/SiOXNY/Si gate stack. Likewise, conductance–voltage (G–V) characteristics show ~ 0.56 (~ 44.4%) reduction in FWHM for Pt/La2O3/SiOXNY/p-Si/Pt as compared to Pt/La2O3/p-Si/Pt MIS structures revealing the reduction in interface states at La2O3/SiOXNY/Si interface. There is a considerable reduction of effective oxide charge concentration (Neff) ~ 3.99 × 1010 cm−2 by (~ 15.2%) and ~ 56.8% lower gate leakage current density ~ 4.47 × 10−7 A/cm2 (|J|–V) at − 1 V for SiOXNY based MIS structures w.r.t its counterpart. Capacitance–time (C–t) characteristics, constant voltage stress (CVS) and temperature measurements for C–V and |J|–V demonstrate the considerable retention ~ 12 years, electrical improvement and reliability of MIS structures. The depth profile analysis X-ray photoelectron spectroscopy (XPS) for SiOXNY/Si gate stack clearly reveals that less nitrogen concentration in bulk than SiOXNY/Si interface. Atomic force microscopy (AFM) micrographs of La2O3/Si and SiOXNY/Si showed the significantly lesser r.m.s roughness of ~ 1.11 ± 0.39 nm and ~ 0.97 ± 0.11 nm, respectively. Thus, the ultrathin SiOXNY interfacial layer underneath of La2O3 demonstrates a significantly improved electrical performance and prelude the gate stack strong potential for reliable CMOS logic devices and integrated circuits.

GaAs Metal–Oxide–Semiconductor Capacitor With Nd-Based High-k Oxynitrides as Gate Dielectric and Passivation Layer

GaAs metal–oxide–semiconductor capacitors with NdTaON as gate dielectric and NdAlON, NdON or AlON as interfacial passivation layer (IPL) are fabricated, and their interfacial and electrical properties are compared with their counterpart without IPL. Experimental results show that owing to the suppressed hygroscopicity of NdON by Al incorporation, best improvements in electrical properties and reliability are achieved for the sample with NdAlON IPL (low interface-state density ( $8 \times 10^{11}$ cm−2/eV), small flatband voltage (0.72 V), negligible hysteresis (43 mV), small frequency dispersion, and low gate leakage current density ( $2.56 \times 10^{-6}$ A/cm2 at Vfb + 1 V). These should be attributed to suppressed growth of unstable Ga and As oxides on the GaAs surface and reduced in-diffusion of elements from the gate dielectric to the GaAs surface by the NdAlON IPL during gate-dielectric annealing.

Low Gate Leakage Current and Interface State Density of Atomic Layer Deposition Al2O3 SiC MOS Device with NH3 Plasma Treatment

This work was supported by the Nano Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2015M3A7B7045496) as well as the Human Resources Development program grant (No. 20144030200580) of the Korea Institute of Energy Technology Evaluation and Planning (KETEP) funded by the Korean government Ministry of Trade, Industry and Energy.

Improved interfacial and electrical properties of Ge MOS capacitor by using TaON/LaON dual passivation interlayer

The effects of TaON/LaON dual passivation interlayer on the interfacial and electrical properties of Ge metal-oxide-semiconductor (MOS) capacitor with HfO2 gate dielectric are investigated. As compared to its counterpart with only LaON as passivation interlayer, the formation of HfGeOx and LaHfOx, which would degrade the interfacial quality, is effectively suppressed due to the strong blocking role of the TaON barrier layer against Hf diffusion. As a result, excellent interfacial and electrical properties are achieved for the Ge MOS device with the TaON/LaON dual passivation interlayer: high k value (20.9), low interface-state density (5.32 × 1011 cm−2 eV−1) and oxide-charge density (−3.90 × 1012 cm−2), low gate leakage current density (1.77 × 10−4 A/cm2 at Vg = Vfb + 1 V), and high reliability under high-field stress.

Electrical properties of GaN-based heterostructures adopting InAlN/AlGaN bilayer barriers

Electrical properties of GaN-based heterostructures adopting InAlN/AlGaN bilayer barriers are investigated by Hall-effect and current–voltage measurements. It is found that this structure possesses both merits of high two-dimensional electron gas (2DEG) density and low gate leakage current density, while maintaining high 2DEG mobility. Furthermore, temperature dependence of the 2DEG density in this structure is verified to follow a combined tendency of InAlN/GaN (increase) and AlGaN/GaN (decrease) heterostructures with increasing temperature from 90K to 400K, which is mainly caused by superposition of the effects from carrier thermal activation induced by extrinsic factors in InAlN layer and the reduced conduction-band discontinuity.

High-permitivity cerium oxide prepared by molecular beam deposition as gate dielectric and passivation layer and applied to AlGaN/GaN power high electron mobility transistor devices

High-κ cerium oxide (CeO2) was applied to AlGaN/GaN high-electron-mobility transistors (HEMTs) as a gate insulator and a passivation layer by molecular beam deposition (MBD) for high-power applications. From capacitance–voltage (C–V) measurement results, the dielectric constant of the CeO2 film was 25.2. The C–V curves showed clear accumulation and depletion behaviors with a small hysteresis (20 mV). Moreover, the interface trap density (Dit) was calculated to be 5.5 × 1011 eV−1 cm−2 at 150 °C. A CeO2 MOS-HEMT was fabricated and demonstrated a low subthreshold swing (SS) of 87 mV/decade, a high ON/OFF drain current ratio (ION/IOFF) of 1.14 × 109, and a low gate leakage current density (Jleakage) of 2.85 × 10−9 A cm−2 with an improved dynamic ON-resistance (RON), which is about one order of magnitude lower than that of a conventional HEMT.

Determination of optical constant and electrical properties of sputtering-derived HfTiON gate dielectrics

Nitrogen content dependent optical constant and electrical properties of sputtering-derived HfTiON gate dielectrics on Si substrate have been investigated. By means of characterization of ultraviolet–visible spectroscopy, reduction in band gap of HfTiON film has been detected with the increase in nitrogen concentration. Electrical measurements of MOS capacitor based on Al/HfTiON/Si gate stacks have indicated that a low interface-state density with almost ignorable frequency dispersion at applied gate voltage of 1V have been obtained for all samples. With increasing the nitrogen concentration, the improved electrical performance has been observed. For the sample with Ar/N2 flow ratio of 20/5, rapid thermal annealing (RTA) treatment at 200°C achieves relatively favorable excellent electrical properties in terms of low gate leakage current density and oxide charge density (Qox). The conduction mechanism for 200°C-annealed sample has been analyzed systematically.

Comparison of microstructure and electrical characteristics of sputtering-derived HfGdO/HfTiO and HfTiO/HfGdO gate stacks

Abstract The effect of post deposition annealing on the electrical characteristics of metal-oxide-semiconductor capacitors based on HfGdO/HfTiO and HfTiO/HfGdO gate stacks fabricated by sputtering have been investigated. Microstructure and interface chemistry of HfGdO/HfTiO/Si and HfTiO/HfGdO/Si gate stacks have also determined by X-ray diffraction (XRD) and Fourier transform infrared spectroscopy (FTIR) measurements. Comparison with HfTiO/HfGdO, it has been found that HfGdO/HfTiO gate stack has a distinct advantage for avoiding the formation of an undesired interfacial layer. In agreement with FTIR analyses, electrical measurements of MOS capacitor with HfGdO/HfTiO gate stacks indicate much more improved electrical performance than that of as-deposited and 300 °C-annealed HfTiO/HfGdO gate stacks in terms of lower gate leakage current density and high permittivity. The involved leakage current conduction mechanisms for metal-oxide-semiconductor (MOS) capacitors based on sputtered HfGdO/HfTiO and HfTiO/HfGdO gate stacks with optimal annealed temperature also have been discussed in detail.

High-Performance In0.23Ga0.77 As Channel MOSFETs with High Current Ratio Ion/Ioff Grown on Semi-insulating GaAs Substrates by MOCVD

We demonstrate high-performance In0.23 Ga0.77 As channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with high on-current to off-current (Ion/Ioff) ratio grown on semi-insulating GaAs wafers by metal-organic chemical vapor deposition (MOCVD). The 2 μm channel-length devices exhibit a peak extrinsic transconductance of 150 mS/mm and a drain current up to 500 mA/mm. The maximum effective mobility is 1680 cm2/Vs extracted by the split C-V method. Furthermore, the Ion/Ioff ratio is significantly improved from approximately 4.5 × 103 up to approximately 4.32 × 104 by controlling the etch thickness of In0.49 Ga0.51 P. The high drain current and high Ion/Ioff ratio of the In0.23 Ga0.77 As channel MOSFETs are achieved due to the high effective mobility and the low gate leakage current density.

ALD TiN Barrier Metal for pMOS Devices With a Chemical Oxide Interfacial Layer for 20-nm Technology Node

We propose the use of atomic layer deposition (ALD) TiN barrier to replace physical vapor deposition TiN barrier for high- k last/gate last pMOS devices with a chemical oxide interfacial layer in 20-nm technology node. It was found that the pMOS devices with ALD TiN exhibit lower gate leakage current density (Jg) and equivalent oxide thickness. Furthermore, it was found that we could achieve larger flat-band voltage (Vfb) and larger equivalent work function from the pMOS devices with ALD TiN barrier. It was also found that we could further improve the performances of the fabricated pMOS devices by increasing the ALD TiN thickness from 2 to 3 nm.

Electrical, optical and micro-structural properties of ultra-thin HfTiON films

Nitrogen is incorporated with different contents into ultra-thin HfTiO dielectric films deposited on Si (100) substrate by radio frequency (RF) magnetron sputtering under a N2 atmosphere. The improved thermal stability and surface microstructure are demonstrated by X-ray diffraction (XRD) and atomic force microscope (AFM) due to the incorporation of nitrogen. The optical characterization of the ultra-thin HfTiON films exhibits a large band gap attributed to nitrogen doping, and a reduction in band gap with increase of N-doped concentration. More importantly, electrical properties of ultra-thin HfTiON films related to different nitrogen-incorporated content are systematically investigated. The N-doped content of HfTiON films deposited under Ar/N2 flow ratio of 30/15 (sccm) has been proved to be an optimal amount, based on which HfTiON films through 500°C rapid thermal annealing (RTA) treatment further achieve the most favorably excellent electrical properties in terms of a lower gate leakage current density of 7.72×10−6A/cm2 and a higher permittivity of 35.31. Moreover, the dominant conduction mechanisms of Pt/HfTiON/p-Si structures for both as-deposited and annealed HfTiON films are discussed by data fitting method in details.

High‐performance In–Zn–O thin‐film transistors with a soluble processed ZrO2 gate insulator

AbstractSpin‐coated zirconium oxide films were used as a gate dielectric for low‐voltage, high performance indium zinc oxide (IZO) thin‐film transistors (TFTs). The ZrO2 films annealed at 400 °C showed a low gate leakage current density of 2 × 10–8 A/cm2 at an electric field of 2 MV/cm. This was attributed to the low impurity content and high crystalline quality. Therefore, the IZO TFTs with a soluble ZrO2 gate insulator exhibited a high field effect mobility of 23.4 cm2/V s, excellent subthreshold gate swing of 70 mV/decade and a reasonable Ion/off ratio of ∼106. These TFTs operated at low voltages (∼3.0 V) and showed high drain current drive capability, enabling oxide TFTs with a soluble processed high‐k dielectric for use in backplane electronics for low‐power mobile display applications. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Enhancement-mode InAlN/GaN MISHEMT with low gate leakage current

We report an enhancement-mode InAlN/GaN MISHEMT with a low gate leakage current by a thermal oxidation technique under gate. The off-state source-drain current density is as low as ∼10−7 A/mm at VGS = 0 V and VDS = 5 V. The threshold voltage is measured to be +0.8 V by linear extrapolation from the transfer characteristics. The E-mode device exhibits a peak transconductance of 179 mS/mm at a gate bias of 3.4 V. A low reverse gate leakage current density of 4.9 × 10−7 A/mm is measured at VGS = −15 V.

Titania/alumina bilayer gate insulators for InGaAs metal-oxide-semiconductor devices

We describe the electrical properties of atomic layer deposited TiO2/Al2O3 bilayer gate oxides which simultaneously achieve high gate capacitance density and low gate leakage current density. Crystallization of the initially amorphous TiO2 film contributes to a significant accumulation capacitance increase (∼33%) observed after a forming gas anneal at 400 °C. The bilayer dielectrics reduce gate leakage current density by approximately one order of magnitude at flatband compared to Al2O3 single layer of comparable capacitance equivalent thickness. The conduction band offset of TiO2 relative to InGaAs is 0.6 eV, contributing to the ability of the stacked dielectric to suppress gate leakage conduction.

High-Performance Ge MOS Capacitors by $\hbox{O}_{2}$ Plasma Passivation and $\hbox{O}_{2}$ Ambient Annealing

Very promising capacitance-voltage (C-V) characteristics of capacitors on both p- and n-type Ge substrates are demonstrated by using an in situ O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma passivation and an O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ambient annealing. The capacitors exhibited a small equivalent oxide thickness of ~1.5 nm and a low D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> (<; 6 * 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ) energy distribution covering the major part of the Ge bandgap (>; 0.51 eV). The surface potential modulation efficiency was estimated to be ~80% from Hatband to strong inversion on both types of Ge. C-V hysteresis was less than 10 mV with positive bias up to 1.5 V. A low gate leakage current density of <; 9 * 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> ± 1 V indicates high quality of the HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate stacks. Excellent comprehensive properties suggest that a combination of O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma passivation and O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ambient annealing provides a promising technology for GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based CMOS devices.