Low-gain Opamps Research Articles

A 34.3 dB SNDR, 2.3GS/s, Sub-radix pipeline ADC using incomplete settling technique with background radix detector

A 6-bit 2.3 GS/s single-channel sub-radix pipeline ADC using an incomplete settling concept is presented. A radix detector is proposed to detect stage gain in the background so that low gain and low bandwidth opamps can be utilized to conserve power. The raw ADC output codes can be reconstructed with the detected radix to retrieve its accuracy. The simulated results show that the prototype ADC in 40 nm CMOS process exhibits an SNDR of 34.3 dB at Nyquist input frequency with the conversion rate of 2.3 GS/s. It consumes 94 mW at 1 V supply and occupies an active chip area of 0.12 mm2.

Efficiency‐enhanced and high‐precision of input common‐mode feedback control using OSA–CLS technique

Efficiency-enhanced and high-precision input common-mode feedback control (ICMFB) is proposed for a fully differential readout circuit of the MEMS capacitive sensor. This ICMFB improves the efficiency and performance of input common-mode voltage control using a smaller feedback capacitor. The noise performance of the readout circuit is improved as a decrease of a feedback capacitor. The correlated level shift (CLS) technique is used to improve the output swing of the amplifier therefore reduce the value of a feedback capacitor. Also, the oversampling successive approximation (OSA) technique is used to improve the accuracy of input common-mode voltage control using a low-gain op-amp. Simulation results show that the input common-mode voltage error decreases to 0.01% when the value of the feedback capacitor is the same as the MEMS sensor. Also, the noise power spectral density of the readout circuit increases by 10 dB.

A Calibration-Free 14-b 0.7-mW 100-MS/s Pipelined-SAR ADC Using a Weighted- Averaging Correlated Level Shifting Technique

This article presents a 14-b 100-MS/s single-channel pipelined-successive-approximation register (SAR) ADC using a weighted-averaging correlated level shifting (WACLS) technique. For a closed-loop residue amplification, the error voltage due to the finite operational amplifier (opamp) gain can be ideally removed by the proposed WACLS technique with a low-gain opamp. In addition, the opamp bandwidth degradation, by an extra level-shift capacitor (CLS) in two-phase amplification CLS-based circuits, can be relaxed and minimized in WACLS. Furthermore, a speed-enhancement scheme is provided to alleviate the speed degradation owing to one extra amplification phase and long bit-cycling time from two-phase amplification and SAR circuits, respectively. A modified reference swapping (RS) technique is applied to diminish the capacitor mismatch error without any calibration. A quick startup ring amplifier design is introduced for duty-cycled control power saving. The chip is implemented in the 28-nm CMOS technology and occupies an active area of 0.018 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . At 100 MS/s and Nyquist-rate input, the measured SNDR is 71.7 dB with 0.7-mW power consumption only. The calibration-free ADC achieves Walden and Schreier figure-of-merit of 2.2 fJ/conversion-step and 180.2 dB, respectively. Compared with the prior-art ADCs with sampling frequency 100 MS/s and SNDR 65 dB, this work advances the state-of-the-art by 3× and 5.3 dB, respectively.

Background calibration of integrator leakage in discrete-time delta-sigma modulators

This work develops an integrator-leakage calibration technique for the switched-capacitor integrators in a delta-sigma modulator (DSM). Integrators that are realized with low-gain opamps are lossy. A DSM that uses lossy integrators exhibits a degraded signal-to-quantization-noise ratio. In the calibration of an integrator, its integration leakage is determined in the digital domain, and the leakage compensation is applied to the same integrator in the analog domain. The proposed scheme can be used to calibrate all of the integrators in a discrete-time DSM of any form. It can be performed in the background without interrupting the normal operation of the DSM.

Accuracy‐enhanced switched‐capacitor stages using low‐gain opamps

A charge compensation technique is proposed for switched capacitor stages with low-gain opamps. It cancels the error charge flow during the operation phase, thus enhancing the accuracy. A capacitive T-network can be employed to implement the resulting large capacitor ratio. A switched-capacitor integrator and a sample-and-hold stage were designed and simulated to verify the proposed technique.

A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC

A 10-b 320-MS/s pipeline analog-to-digital converter (ADC) with low dc gain opamps, as low as 30.6 dB based on simulations, in its multiplying digital-to-analog converters (MDACs) is presented. A foreground self-calibration technique is proposed to reduce stage gain error by adjusting feedback factor with a calibration capacitor array. The prototype in 90-nm low-power CMOS technology achieves conversion rate of 320 MS/s with peak SFDR and SNDR of 66.7 and 54.2 dB, respectively. The total power dissipation is 42 mW, and it occupies an active chip area of 0.21 mm2 including the calibration circuit. It results in a figure-of-merit (FOM) of 442 fJ/conversion-step. Only 168 clock cycles are used, and no external precise reference sources are needed for the calibration.

High-precision switched-capacitor integrator using low-gain opamp

A high-precision switched-capacitor integrator using a low-gain opamp is proposed. The circuit contains a main signal path and a predictive signal path which makes the correlated double sampling more effective. The proposed integrator was simulated using SPICE parameters for a 180 nm CMOS process with a supply voltage of 1.2 V. The circuit exhibited much lower harmonic distortion than those described in earlier works.

Area and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs

Digital calibration techniques are widely utilized to linearize pipelined analog-to-digital converters (ADCs). However, their power dissipation can be prohibitively high, particularly when high-order gain calibration is needed. This paper demonstrates the need for high-order gain calibration in pipelined ADCs designed using low-gain opamps in scaled digital CMOS. For high-order gain calibration, this paper then proposes a design methodology to optimize the data precision (number of bits) within the digital calibration unit. Thus, the power dissipation and chip area of the calibration unit can be minimized, without affecting the ADC linearity. A 90-nm field-programmable gate array synthesis of a second-order gain calibration unit shows that the proposed optimization methodology results in 53% and 30% reductions in digital power dissipation and chip area, respectively.

74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain

This paper presents a new multi-loop delta-sigma modulator which overcomes the necessity of high DC gain opamps that were needed in previous multi-loop modulators. Enabling the use of low gain opamps also allows low-voltage operation due to the reduced number of transistors between the power supply rails. In addition, all the digital filters are removed from the output of this modulator to minimize the overall system requirement. Instead, an in-loop digital addition facilitates the desired noise transfer functions of both loops. This combines stability advantage of the multi-loop structure with relaxed circuit requirement of the single-loop modulator. A fourth order modulator is implemented in a 0.18 mum CMOS technology to demonstrate this concept. Measurement results show that, with open-loop opamp gain of less than 35 dB, the implemented prototype IC achieves over 74 dB SNDR at an oversampling ratio of 16. The sampling frequency is 20 MHz and the total power dissipation is 3.2 mW at 1.2 V supply.

A 10.7-MHz BiCMOS high-Q double-sampled SC bandpass filter

A fundamental block in telecommunication systems is the high-selectivity bandpass filter centered at the intermediate frequency (IF). In this paper, a BiCMOS high-Q (Q=29) 10.7-MHz switched-capacitor (SC) bandpass filter to be used in the FM receiver channel has been developed. The filter uses low-gain large-bandwidth opamps. The opamp finite gain effects have been compensated using an SC integrator suited for high-Q filters. The particular SC finite-gain compensation scheme allows the implementation of double sampling to relax opamp bandwidth requirements. To reduce total output noise, noisy T-cell networks (often used in other cases) have been avoided. The resulting large capacitors (the largest capacitor is 8.5 pF) are driven by a Class AB output buffer. In a 1.2-/spl mu/m BiCMOS technology, the filter prototype has an area of about 1.6 mm/sup 2/ and a power consumption of 17 mW. The in-band noise density is 380 nV//spl radic/Hz, and the dynamic range is about 68 dB for a 3% IM.