A 34.3 dB SNDR, 2.3GS/s, Sub-radix pipeline ADC using incomplete settling technique with background radix detector

Abstract

A 6-bit 2.3 GS/s single-channel sub-radix pipeline ADC using an incomplete settling concept is presented. A radix detector is proposed to detect stage gain in the background so that low gain and low bandwidth opamps can be utilized to conserve power. The raw ADC output codes can be reconstructed with the detected radix to retrieve its accuracy. The simulated results show that the prototype ADC in 40 nm CMOS process exhibits an SNDR of 34.3 dB at Nyquist input frequency with the conversion rate of 2.3 GS/s. It consumes 94 mW at 1 V supply and occupies an active chip area of 0.12 mm2.