Low Phase Noise Frequency Research Articles

High-Power, Ultra-Low Noise Hybrid Lasers for Microwave Photonics and Optical Sensing

This paper describes the design, fabrication, and excellent performance achieved with prototype hybrid lasers incorporating a high performance gain chip coupled into a fiber external cavity including a novel fiber Bragg grating (FBG) reflector. Packaged ultra-low noise (ULN) hybrid lasers operating at 1550 nm and at 1319 nm with high output power, >100 mW, and extremely low relative intensity noise (RIN) are described. Devices provide extremely stable singlemode output with high side-mode suppression ratio (SMSR), typically above 70 dB, with worst case measured RIN at microwave frequencies (1–20 GHz) being below –165 dBc/Hz. Operation of these high power, low RIN devices within an analog optical link demonstrates a Spurious Free Dynamic Range as high as 114.6 dB.Hz 2/3. In addition to high power and very low RIN, the ULN hybrid lasers provide extremely small low frequency phase noise, with Lorentzian linewidths down to 15 Hz, enabling key Microwave Photonics and Optical Sensing applications. A comparison of the phase noise and Lorentzian linewidth of ULN lasers with different FBG designs / external cavity lengths is described, demonstrating the novel hybrid approach for achieving extremely low phase noise lasers.

Design of c-band telecontrol transmitter local oscillator for UAV data link

A C-band local oscillator of an Unmanned Aerial Vehicle (UAV) data link radio frequency (RF) transmitter unit with high-stability, high-precision and lightweight was designed in this paper. Based on the highly integrated broadband phase-locked loop (PLL) chip HMC834LP6GE, the system performed fractional-N control by internal modules programming to achieve low phase noise and small frequency resolution. The simulation and testing methods were combined to optimize and select the loop filter parameters to ensure the high precision and stability of the frequency synthesis output. The theoretical analysis and engineering prototype measurement results showed that the local oscillator had stable output frequency, accurate frequency step, high spurious suppression and low phase noise, and met the design requirements. The proposed design idea and research method have theoretical guiding significance for engineering practice.

A frequency multiplier for reference frequency in frequency synthesizer systems

A low jitter frequency multiplier, which requires less power, area, and design complexity than reference multiplying PLL or DLL circuits can be used to generate the reference frequency for a low phase noise frequency synthesizer. This paper proposes a mixed signal solution based on the fact that the average DC value of a signal is proportional to its duty cycle. The solution uses a feedback loop with coarse and fine delay resolution to generate a $$90^{\circ }$$ phase shifted clock that is used to produce a doubled frequency signal with 50% duty cycle. This method can be used to multiply the input frequency of 40 MHz by multiples of 2, up to 16. The design is implemented in 65 nm UMC CMOS process. Operating from 1.2-V supply, it dissipates 0.46 to 1.2 mA at output frequencies 80–640 MHz, achieving − 162.3 and − 139 dBc/Hz phase noise at 1 MHz offset, respectively.

低位相雑音・広周波数レンジの電圧制御発振器の最適設計法(アナログ・デジアナ・センサ, 通信用LSI)

低位相雑音・広周波数レンジの電圧制御発振器の最適設計法(アナログ・デジアナ・センサ, 通信用LSI)

Low Phase Noise Frequency Synthesis for Ultrastable $X$ -Band Oscillators

In this letter, the design of a low phase noise frequency synthesizer is presented. The synthesizer was designed to produce four frequencies: 10 MHz, 100 MHz, 1 GHz and 10 GHz. The 1-GHz signal is produced by frequency division whereas the 100-MHz output is generated by phase-locking a low phase noise oscillator to the 1-GHz signal, hence significantly reducing its phase noise. Both residual and total phase noise measurements are presented.

Robust Study and Design of a Low Power CMOS CSVCO using 45nm Technology

This paper consist of the design and detailed study of a three stage Current Starved Voltage Controlled Oscillator having a very low voltage supply of 1V with low phase noise. The Three stage CSVCO is designed. This work is being done on Cadence virtuoso analog and digital IC design tools with gpdk 45nm CMOS technology process. The voltage supply is taken to be 1V which is low and quite useful according to the latest trends. The center frequency is taken to be 2.4 GHz which is best suitable for satellite and many other applications. The proposed CSVCO consumes low power, low area, low phase noise and high oscillation frequency. The design procedure adopted and the simulation results acquired are illustrated. This CSVCO is suitable for a fast locking PLL, for frequency synthesizer, for clock generation and recovery etc. The results obtained are compared with the previous works and improvements are observed. The Phase noise of the proposed CSVCO is less as compared to the other works.

Testing Time and Frequency Fiber-Optic Link Transfer by Hardware Emulation of Acoustic-Band Optical Noise

Abstract The low-frequency optical-signal phase noise induced by mechanical vibration of the base occurs in field-deployed fibers. Typical telecommunication data transfer is insensitive to this type of noise but the phenomenon may influence links dedicated to precise Time and Frequency (T&F) fiber-optic transfer that exploit the idea of stabilization of phase or propagation delay of the link. To measure effectiveness of suppression of acoustic noise in such a link, a dedicated measurement setup is necessary. The setup should enable to introduce a low-frequency phase corruption to the optical signal in a controllable way. In the paper, a concept of a setup in which the mechanically induced acoustic-band optical signal phase corruption is described and its own features and measured parameters are presented. Next, the experimental measurement results of the T&F transfer TFTS-2 system’s immunity as a function of the fibre-optic length vs. the acoustic-band noise are presented. Then, the dependency of the system immunity on the location of a noise source along the link is also pointed out.

Universal set of dynamically protected gates for bipartite qubit networks: Soft pulse implementation of the [[5,1,3]] quantum error-correcting code

We model repetitive quantum error correction (QEC) with the single-error-correcting five-qubit code on a network of individually controlled qubits with always-on Ising couplings. We use our previously designed universal set of quantum gates based on sequences of shaped decoupling pulses. In addition to being accurate quantum gates, the sequences also provide dynamical decoupling (DD) of low-frequency phase noise. The simulation involves integrating the unitary dynamics of six qubits over the duration of tens of thousands of control pulses, using classical stochastic phase noise as a source of decoherence. The combined DD and QEC protocol dramatically improves the coherence, with the QEC alone being responsible for more than an order of magnitude infidelity reduction.

Low phase noise frequency tripled microwave signal generation using external optical modulation

ABSTRACTA high purity low phase noise frequency tripled microwave signal at 6 GHz is generated by applying a 2‐GHz electrical drive signal to a quadrature biased Mach Zehnder intensity modulator (MZM). Frequency tripled signal is found advantageous compared to frequency doubled generation in terms of increased dynamic range of input electrical drive power and bias voltage stability of MZM. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1082–1085, 2016

X-band low phase noise push–push oscillator utilizing High-Q differential transmission line loaded with multiple split-ring resonator

In this study, a low phase noise X-band push–push oscillator is presented employing the differential transmission lines (TLs) loaded with multiple split-ring resonator (M-SRR). In order to enhance the coupling strength between TL and resonator cell, the single M-SRR is replaced by the coupled M-SRR cell-pair in differential TL to obtain high-frequency selectivity and deep insertion loss. The resonance properties of the differential TL have been discussed with different coupling configurations and coupling strengths of the M-SRR cell-pair, and the geometries of the proposed structure are investigated to obtain the optimum resonance properties. The loaded Q-factor of the proposed differential TL adopting 3-stages cascaded array of M-SRR cell-pairs configuration is 892 from measured results. Due to the high-Q and anti-phase current properties of the differential TL, a X-band push–push oscillator with low phase noise and superior fundamental frequency suppression performances is realized. The fabricated push–push oscillator operates at 9.52 GHz with an output power of 2.7 dBm and a fundamental frequency suppression of −54.55 dBc. It shows a measured phase noise of −115.48 dBc/Hz at 100 kHz offset frequency and a figure of merit of −201.23 dBc/Hz.

낮은 위상잡음 특성을 갖는 0.5~4 GHz 주파수 합성기 설계 및 제작

낮은 위상잡음 특성을 갖는 0.5~4 GHz 주파수 합성기 설계 및 제작

Hybrid voltage-controlled oscillator with low phase noise and large frequency tuning range

A transformer LC oscillator utilizing the low phase noise of spiral LC oscillator and the large frequency tuning range of active inductors is proposed to yield both a large frequency range and low phase noise. The oscillator is a passive transformer LC oscillator with the primary winding of the transformer connected to the oscillating nodes of the oscillator and the secondary winding loaded with an active inductor. The contribution of the noise of the active inductor is minimized by adjusting the coupling of the transformer such that the overall phase noise of the oscillator is much lower as compared with that of corresponding active inductor oscillators while the frequency tuning range of the oscillator is much larger than that of passive transformer oscillators. The VCO has been designed in an IBM 130 nm 1.2V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3 device models. For purpose of comparison, an active inductor LC oscillator and a spiral inductor LC oscillator have also been designed and analyzed. The phase noise of the active inductor, spiral transformer, and hybrid oscillators at 1 MHz frequency offset from their nominal oscillation frequency is $$-$$-80.18, $$-$$-106.9, and $$-$$-100.5 dBc/Hz, respectively. The power consumption of the spiral inductor, active inductor, and hybrid oscillators is 4.8, 30, and 34.8 mW, respectively.

Design of the X-Band Frequency Source Based on the Multiplying Technology

The phase noise performance of frequency source has a direct impact on the target measurement such as the adjacent channel interference of the electronic system, the transmission quality of information, the resolution of radar. In this paper, we achieved an X-band high stability, low phase noise frequency source which based on the DDS combination with frequency doubling technology. The test result shows that when the output of the frequency source is at 8.544GHz, the phase nosie is-103.58dBc/Hz at 1kHz and-101.94dBc/Hz at 10kHz.

A 220–1100 MHz low phase-noise frequency synthesizer with wide-band VCO and selectable I/Q divider

This paper presents a low phase-noise fractional-N frequency synthesizer which provides an in-phase/quadrature-phase (I/Q) signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation (WIA) applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator (VCO) is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 kHz loop bandwidth, lowest measured phase noise is −106 dBc/Hz at a 10 kHz offset and −131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm2, consumes only 15 mW from the 1.8 V power supply, and settles within 13.2 μs. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.

KU-BAND 저 위상잡음 주파수 합성기 설계에 관한 연구

In the proposed paper, we designed low phase noise frequency synthesizer for Ku-band. The proposed up-mixing frequency synthesizer consists of narrow local oscillation part and variable frequency oscillation part. To improve the phase noise of frequency synthesizer, we analyze how the configuration of frequency synthesizer affect the phase noise. The implemented frequency synthesizer reduce the phase noise. The phase noise is -95.18dBc/Hz at 7kHz frequency offset in 16GHz and -94.27dBc/Hz at 7kHz frequency offset in 16.125GHz.

A Low Phase Noise and Low Spurious Frequency Source based on Programmable Frequency Dividers

In this paper, based on the programmable frequency dividers HMC394 and AD company's integer PLL chip ADF4107, in the premise of not reducing the phase detector frequency, improved the frequency resolution and effectively inhibits the phase stray. Designed a frequency source with high performance index: high resolution is 10kHz, low phase noise is-91.27dBc/Hz @10kHz, low spurious is less than-60dBc, high harmonic suppression is less than-60dBc,the design method is simple, low cost, flexible control, high performance and widely used.

Investigation of Phase-Shifting and Frequency Conversion Sinusoidal Signal Generator Based on DDS and FPGA

The direct digital frequency synthesis (DDS) technology has high frequency resolution, fast frequency switching, low phase noise and higher frequency stability, so it is widely used in communications, aerospace, instrumentation and other fields. In this paper, the DDS system was designed based on Field Programmable Gate Array (FPGA) and hardware design language (VHDL). The experimental and simulation results show that the system has stable output frequency, high frequency accuracy, adjustable frequency and phase.

Measuring the universal synchronization properties of driven oscillators across a Hopf instability

When a driven oscillator loses phase-locking to a master oscillator via a Hopf bifurcation, it enters a bounded-phase regime in which its average frequency is still equal to the master frequency, but its phase displays temporal oscillations. Here we characterize these two synchronization regimes in a laser experiment, by measuring the spectrum of the phase fluctuations across the bifurcation. We find experimentally, and confirm numerically, that the low frequency phase noise of the driven oscillator is strongly suppressed in both regimes in the same way. Thus the long-term phase stability of the master oscillator is transferred to the driven one, even in the absence of phase-locking. The numerical study of a generic, minimal model suggests that such behavior is universal for any periodically driven oscillator near a Hopf bifurcation point.

Low-noise parametric frequency comb for continuous C-plus-L-band 16-QAM channels generation

A low phase noise frequency comb generated from a continuous-wave seed is experimentally demonstrated across continuous C- and L-bands. Parametrically generated carriers with optical signal-to-noise ratio in excess of 45 dB were used to generate 16-ary quadrature amplitude modulated signals. We characterize 20 GBaud channels' performance that was varied by only 1.7 dB across the combined C/L band.

A low phase noise and low spur PLL frequency synthesizer for GNSS receivers

A low phase noise and low spur phase locked loop (PLL) frequency synthesizer for use in global navigation satellite system (GNSS) receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector (PFD) produces four control signals, which can reach the charge pump (CP) simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is −127.65 dBc/Hz and the reference spur is −73.58 dBc.