Low Flicker Research Articles

A Single-Chip CMOS UHF RFID Reader Transceiver for Chinese Mobile Applications

UHF RFID reader transceiver for Chinese local standard (840-845 MHz and 920-925 MHz), in concord with the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000-6C, is presented. A highly linear RF front-end with low flicker noise, an on-chip self-jammer cancellation (SC) circuit with fast time-varying cut-off frequency and a DC-offset cancellation (DCOC) circuit are proposed to deal with the large self-jammer in the receiver. In the presence of 22 dBm PA output power, the receiver achieves a sensitivity of -79 dBm including the 15 dB loss of the directional coupler. A CMOS class-AB PA is integrated in the transmitter, with 22 dBm output power and 35% PAE. The spectrum mask achieves ACPR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> of -45 dBc and ACPR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> of -60 dBc . A sigma-delta fractional-N PLL with a single <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> VCO is also implemented for good phase noise (-126 dBc/Hz @ 1 MHz offset) and high frequency resolution within 1 kHz. This single-chip is fabricated in a 0.18 standard CMOS process. It occupies a silicon area of 13.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and dissipates 203 mW from a 1.8 V supply voltage when transmitting 7.5 dBm output power.

Low-phase-noise frequency synthesizer for the trapped atom clock on a chip

We report on the realization of a 6.834-GHz synthesis chain for the trapped atom clock on a chip (TACC) that is being developed at LNE-SYRTE. The chain is based on the frequency multiplication of a 100-MHz reference signal to obtain a signal at 6.4 GHz. It uses a comb generator based on a monolithic GaAs nonlinear transmission line. This is a novelty in the fabrication of high-stability microwave synthesizers. Measurements give a low flicker phase noise of -85 dBrad(2)/Hz at 1-Hz offset frequency and a white phase noise floor < -115 dBrad(2)/Hz. Based on these results, we estimate that the performance of the synthesizer is at least one order of magnitude better than the stability goal of TACC. This ensures that the synthesizer will not be limiting the clock performance.

Comparison of 24 GHz receiver front-ends using active and passive mixers in CMOS

This study compares the key parameters of two integrated receiver front-end architectures: low noise amplifier (LNA) with active mixer against LNA with passive mixer. The authors discuss the differences in the performance and their impact on system characteristics for radar applications. A low-IF down-conversion receiver implementation is considered. The results are compared in measurement for two 24 GHz receiver front-end chips realised in a 0.13 mum digital CMOS process. Both circuits have been characterised over automotive temperature range -40 to 125degC. The front-end with an active mixer offers lower LO power dependence and exhibits better temperature stability, whereas the front-end with a passive mixer has the advantage of better input-referred linearity and lower flicker noise.

Auto-oscillation and narrow spectral lines in spin-torque oscillators based on MgO magnetic tunnel junctions

We demonstrate spin-torque induced coherent auto-oscillation in magnetic tunnel junctions of composition PtMn/CoFe/Ru/CoFeB/MgO/CoFeB and of low resistance-area product. At the generation threshold, we observe a strong line narrowing down to 6 MHz at 300 K and a dramatic increase in oscillator power, yielding spectrally pure oscillations with extremely low flicker noise. The induced auto-oscillations are observed even at zero applied field. The frequency of the oscillation mode, and its dependence with easy and hard axis fields are consistent with an acoustical excitation of the two layers of the synthetic ferrimagnet subsystem. Setting the synthetic ferrimagnet into auto-oscillation requires the current polarity that transfers electrons from the synthetic ferrimagnet to the free layer. In auto-oscillation mode, line jitter is observed such that it is the line envelope that is measured in most cases. The line properties for applied fields near the instability boundaries of the Stoner astroid of the free layer indicate that the phase coherence of the auto-oscillation is likely to be affected by the free layer magnetic noise.

Current-Reused Ultra Low Power, Low Noise LNA${+}$Mixer

A current-reused ultra low power, low flicker noise direct-conversion low noise amplifier (LNA)+ mixer architecture is proposed. Measurements of the proposed LNA+mixer applied for 2.4 GHz Zigbee system using 0.18 mum CMOS technology shows 21 dB voltage gain, 6 dB noise figure, and approximately 300 KHz flicker noise corner frequency while dissipating 0.9 mA from a 1.8 V supply.

Low-frequency electronic noise in the double-gate single-layer graphene transistors

The authors report the results of an experimental investigation of the low-frequency noise in the double-gate graphene transistors. The back-gate graphene devices were modified via addition of the top gate separated by ∼20 nm of HfO2 from the single-layer graphene channels. The measurements revealed low flicker noise levels with the normalized noise spectral density close to 1/f (f is the frequency) and Hooge parameter αH≈2×10−3. The analysis of noise spectral density dependence on the top and bottom gate biases helped to elucidate the noise sources in these devices. The obtained results are important for graphene electronic and sensor applications.

A 5 GHz Differential Colpitts CMOS VCO Using the Bottom PMOS Cross-Coupled Current Source

A low phase noise differential Colpitts voltage-controlled oscillator (VCO) with the bottom series PMOS cross-coupled current source is presented. The core Colpitts VCO adopts a pair of PMOS as the biased current source at the bottom, instead of a conventional NMOS topology, to achieve a better phase noise performance as the PMOS has lower flicker and white noise than those of NMOS and the output power spectral density of PMOS operated in bottom-biased type is further less than that in top-biased one in the same power consumption. The fabricated VCO operates from 4.9 to 5.46 GHz with 10.6% tuning range when the power consumption is below 6.4 mW with a supply voltage of 1.8 V. The measured phase noise at 100 kHz offset is -100.3 dBc/Hz at 5.46 GHz and achieves a good FOM performance of -187 dBc/Hz.

A Noise Optimized Passive Mixer for Charge-Domain Sampling Applications

This paper presents a circuit design technique, based on a CMOS charge-domain passive mixer, for WLAN applications in a 2.4 GHz band. The CMOS passive mixer is designed to mitigate the critical flicker noise problem that is frequently encountered in constitution of direct conversion receivers. The charge-domain method is employed to improve the high frequency performance and noise characteristic. The designed circuit is composed of a trans-conductance amplifier and a passive mixer with a capacitive charge storing load. Fabricated in 0.13 μm CMOS process, this charge-domain mixer achieves a low flicker noise with corner frequency of under 100 kHz, 8.1 dB noise figure, 10.6 dB conversion voltage gain, 2.5 dBm IIP3, and –5.7 dBm P1dB with 2.4 GHz LO driving at 5 dBm. It consumes 4.31 mA from 1.5 V supply.

Direct conversion RF front-end with a low-power consumption technique for 2.4 GHz ISM band

The implementation and performance measurements of RF front-end are presented. The low-power RF front-end designed in TSMC 0.18 µm process for 2.4 GHz ISM band direct conversion is presented. The proposed RF front-end is comprised of the folded mixer, fully differential low-noise amplifier (LNA) and interstage matching network. Gilbert-cell mixers using the folded technique and current reused LNA are designed for low power consumption. The folded mixers are implemented by using PMOS devices in the switching stage of mixers with a resonating inductor for low flicker noise. The proposed RF front-end consumes 7.2 mW from the 1.2 V supply and a conversion gain of 23 dB is achieved. The third-order intercept point (IIP3) is −10.5 dBm, and the proposed RF front-end has good linearity. By using PMOS devices and the folded technique, low flicker noise of 10 dB at 10 kHz is achieved, and thus the proposed RF front-end can be used in the direct conversion receiver for narrow bandwidth.

CMOS Direct-Conversion RF Front-End Design for 5-GHz WLAN

Direct-conversion RF front-end for 5-GHz WLAN is implemented in <TEX>$0.18-{\mu}m$</TEX> CMOS technology. The front-end consists of a low noise amplifier, and low flicker noise down-conversion mixers. For the mixer, an inductor is included to resonate out parasitic tail capacitances in the transconductance stage at the operating frequency, thereby improves the flicker noise performance of the mixer, and the overall noise performance of the front-end. The receiver RF front-end has 6.5 dB noise figure, - 13 dBm input IP3, and voltage conversion gain of 20 dB with the power consumption of 30 mW.

The contribution of rapid visual and auditory processing to the reading of irregular words and pseudowords presented singly and in contiguity

This study examined the relative involvement of rapid auditory and visual temporal resolution mechanisms in the reading of phonologically regular pseudowords and English irregular words presented both in isolation and in contiguity as a series of six words. Seventy-nine undergraduates participated in a range of reading, visual temporal, and auditory temporal tasks. The correlation analyses suggested a general timing mechanism across modalities. There were more significant correlations between the visual temporal measures and irregular word reading and between the auditory measures and pseudoword reading. Auditory gap detection predicted pseudoword reading accuracies. The low temporal frequency flicker contrast sensitivity measure predicted the accuracies of isolated irregular words and pseudowords presented in contiguity. However, when a combined speed-accuracy score was used, visible persistence at both low and high spatial frequencies and auditory gap detection were active in the reading of pseudowords presented in contiguity. Sensory processing skills in both visual and auditory modalities accounted for some of the variance in the reading performance of normal undergraduates, not just reading-impaired students.

The Influence of Cognitive Tasks on Different Frequencies Steady-state Visual Evoked Potentials

Previous studies suggested that there exists different neural networks for different frequency bands of steady-state visual evoked potential (SSVEP). What is the effect of the same cognitive task on different frequency SSVEPs? In this work, when a subject was conducting a graded memory task, a 8.3 or 20 Hz flicker was used as a background stimulation. The recorded EEGs were analyzed by the method of steady-state probe topography (SSPT), the results showed that SSVEPs under these two flicker conditions were similar to each other in the various stages of memory process, and were similar to the result of a high alpha band SSVEP as reported before. However, the SSVEP amplitude and latency in the lower frequency band is more clear and stable than that in the higher frequency band. These results suggest that the same cognitive task affects the different frequency SSVEP in a similar way, and the low frequency flicker is a better choice than the high frequency one in such as working memory study.

Direct-current and radio-frequency characterizations of GaAs metal-insulator-semiconductor field-effect transistors enabled by self-assembled nanodielectrics

Direct-current and radio-frequency characterizations of GaAs metal-insulator-semiconductor field-effect transistors (MISFETs) with very thin self-assembled organic nanodielectrics (SANDs) are presented. The application of SAND on compound semiconductors offers unique opportunities for high-performance devices. Thus, 1μm gate-length depletion-mode n-channel SAND/GaAs MISFETs exhibit low gate leakage current densities of 10−2–10−5A∕cm2, a maximum drain current of 260mA∕mm at 2V forward gate bias, and a maximum intrinsic transconductance of 127mS∕mm. These devices achieve a current cutoff frequency (fT) of 10.6GHz and a maximum oscillation frequency (fmax) of 6.9GHz. Nearly hysteresis-free Ids-Vgs characteristics and low flicker noise indicate that a high-quality SAND-GaAs interface is achieved.

Broad tuning ultra low phase noise dielectric resonator oscillators using SiGe amplifier and ceramic-based resonators

This paper describes the design of very low noise, tunable, X-band dielectric resonator oscillators (DROs) demonstrating phase-noise performance of -135 dBc/Hz at 10 kHz offset. SiGe transistors are used for the oscillator sustaining amplifiers that offer a circulating power of 12 dBm and a gain of 5.4 dB per stage as well as a low flicker noise corner of 40 kHz. A variety of resonator configurations utilising BaTiO 3 resonators are presented demonstrating unloaded Qs from 10 000 to 22 000. These resonators are optimised and coupled to the amplifiers for minimum phase noise where Q L /Q 0 = 1/2, and hence S 21 = -6 dB. To incorporate tuning with low additional phase noise, a phase shifter is also investigated. The theory for the low noise oscillator design is included; experimental results demonstrate close correlation with the theory.

Shaping the pupil’s response to light in the hooded rat

The contribution of iris muscle steady state and dynamic response characteristics to the shaping of the pupil response to light in the hooded rat were studied using electrical stimulation of the parasympathetic fibers in the III nerve. The waveforms of pupillary contractions to single or brief trains of electrical impulses applied to the III nerve were virtually identical to those elicited with short duration light flashes. Individual contractions could be resolved at stimulation rates of 2 Hz and below, and the size of the contractions increased with the decrease in frequency. The pupil responded to long trains of stimuli above 2 Hz with smooth tonic contractions. Steady state contraction amplitude was linearly related to log stimulation frequency. The mean time constant of pupil constriction to stimulus trains was 1.41 s (SD +/- 0.71 s) and the shortest mean latency was 292 ms (SD +/- 30 ms). The fastest mean latency of pupil constriction to the brightest light flash used was 295 ms. In contrast, the time constant of pupillary dilation was 7 s (SD +/- 1.4 s) and the shortest latency was 485 ms (SD +/- 74 ms). Therefore, the sluggish dynamic properties of the iris musculature are responsible for the asymmetries in pupil contraction, dilation, and latencies as well as low flicker fusion frequency and constriction amplitude characteristics of pupil responses to light.

65 nm LP/GP mix low cost platform for multi-media wireless and consumer applications

A complete 65 nm CMOS platform, called LP/GP Mix, has been developed employing thick oxide transistor (IO), Low Power (LP) and General Purpose (GP) devices on the same chip. Dedicated to wireless multi-media and consumer applications, this new triple gate oxide platform is low cost (+1mask only) and saves over 35% of dynamic power with the use of the low operating voltage GP. The LP/GP mix shows competitive digital performance with a ring oscillator (FO = 1) speed equal to 7 ps per stage (GP) and 6T-SRAM static power lower than 10 pA/cell (LP). Compatible with mixed-signal design requirements, transistors show high voltage gain, low mismatch factor and low flicker noise. Moreover, to address mobile phone demands, excellent RF performance has been achieved with F T = 160 GHz for LP and 280 GHz for GP nMOS transistors.

Close-in phase-noise enhanced voltage-controlled oscillator employing parasitic V-NPN transistor in CMOS process

This paper presents a voltage-controlled oscillator (VCO) with low close-in phase noise by exploiting a parasitic vertical NPN transistor (V-NPN) as a tail current source in a 0.18-/spl mu/m CMOS process. V-NPN has an inherently low flicker noise (1/f noise) profile compared to CMOS devices. Simple dc and ac characteristics of V-NPN are measured and extracted for design convenience. The proposed VCO that used a V-NPN current source instead of nMOS is verified using a 0.18-/spl mu/m deep n-well CMOS process. Test results of the designed VCO show good figure-of-merit of -87.4 dBc/Hz, -111 dBc/Hz of phase noise at 10 kHz, and 100-kHz offsets while consuming only 540 /spl mu/W from the 1.8-V supply.

３Ｄ物体の鉛筆画風画像の生成

A simple technique is presented for generating pencil drawing images resembling hand-drawn sketches of 3D objects. We devised a method for extracting edge enhancement components by using division of an input image by its blurred one instead of conventional subtraction methods. Depth images are used for completion of edge enhancement components, which are impossible to extract from shading images. Edges are enhanced by removing one side of the edge enhancement shading. Thus, the obtained edge-enhanced shading images are transformed to stippling images using the point redistribution method presented by Secord et al. This stippling image is then anisotropically smoothed to produce a hatching image. We also applied this technique to moving images. One merit of our method is that it can produce movies with very low flicker without any specific overhead processing.

An Implantable CMOS Front-End System for Nerve-Signal Sensors

An analog front-end dedicated to processing of cuff-recorded human nerve signals is presented in this paper. The system is comprised of a low-noise preamplifier and an A/D converter (ADC) for quantizing the recorded nerve signal. The instrumentation amplifier utilizes CMOS transistors biased in the weak/moderate inversion region at a relatively high current for low thermal noise performance and achieves low flicker noise performance through chopper stabilization. The resulting measured equivalent input referred thermal noise is 6.6 nV/?Hz at a chopping frequency of 20 kHz. A two-stage design is implemented which achieves a measured amplification of 72.5 dB over a signal bandwidth of 4 kHz. For the ADC, a third order ??-modulator employing a continuous-time (CT) loopfilter was implemented. Each of the integrators in the loop-filter are implemented as Gm?C elements. For a sampling frequency of 1.4 MHz, the measured SNDR for the ADC is 62 dB, whereas the dynamic range (DR) is 67 dB over a 4 kHz bandwidth, equivalent to a resolution of 10 bits. The system draws a current of 196 ?A from a 1.8 V supply thus consuming approximately 350 ?W excluding buffers and bias circuitry.

A High Performance CMOS Direct Down Conversion Mixer for UWB System

This paper presents a high performance wideband CMOS direct down-conversion mixer for UWB based on 0.18μm CMOS technology. The proposed mixer uses the current bleeding technique and an extra resonant inductor to improve the conversion gain, noise figure (NF) and linearity. Also, with an extra inductor and the careful choosing of transistor sizes, the mixer has a very low flicker noise. The shunt resistor matching is applied to have a 528 MHz bandwidth matching at 50 Ohm. The simulation results show the voltage conversion gain of 20.5 dB, the double-side band NF of 5.6 dB. Two-tone test result indicates 11.25 dBm of IIP3 and higher than 70 dBm of IIP2. The circuit operates at the supply voltage of 1.8 V, and dissipates 11.5 mW.