Close-in phase-noise enhanced voltage-controlled oscillator employing parasitic V-NPN transistor in CMOS process

Abstract

This paper presents a voltage-controlled oscillator (VCO) with low close-in phase noise by exploiting a parasitic vertical NPN transistor (V-NPN) as a tail current source in a 0.18-/spl mu/m CMOS process. V-NPN has an inherently low flicker noise (1/f noise) profile compared to CMOS devices. Simple dc and ac characteristics of V-NPN are measured and extracted for design convenience. The proposed VCO that used a V-NPN current source instead of nMOS is verified using a 0.18-/spl mu/m deep n-well CMOS process. Test results of the designed VCO show good figure-of-merit of -87.4 dBc/Hz, -111 dBc/Hz of phase noise at 10 kHz, and 100-kHz offsets while consuming only 540 /spl mu/W from the 1.8-V supply.