Low EMI Noise Research Articles

A Novel Trench IGBT With N-P-N Polysilicon Gate Structure for Low EMI Noise and High Robustness

A Novel Trench IGBT With N-P-N Polysilicon Gate Structure for Low EMI Noise and High Robustness

Low Loss and Low EMI Noise Trench IGBT with Shallow Emitter Trench Controlled p-Type Dummy Region

Low Loss and Low EMI Noise Trench IGBT with Shallow Emitter Trench Controlled p-Type Dummy Region

Device Design Direction of CSTBT for Low Loss and EMI Noise

Device Design Direction of CSTBT for Low Loss and EMI Noise

Low On-State Voltage and EMI Noise 4H-SiC IGBT With Self-Biased Split-Gate pMOS

A 15-kV-scale 4H-SiC insulated-gate bipolar transistor (IGBT) with a self-biased split-gate pMOS (SGPMOS) is proposed and simulated in this work. By introducing the SGPMOS, the proposed IGBT forms a hole barrier in the ON-state and a hole extraction path during the turn-on and turn-off transient, respectively. Compared to GS IGBT, the ON-state voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ON}}{)}$ </tex-math></inline-formula> of the SGPMOS IGBT is decreased by 54.95% for the same turn-off loss ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {off}}$ </tex-math></inline-formula> ). Meanwhile, compared with pMOS IGBT, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> and gate charge ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}_{g}{)}$ </tex-math></inline-formula> characteristics exhibit that the Miller capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {gc}}{)}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}_{g}$ </tex-math></inline-formula> of the SGPMOS IGBT are reduced by 56.60% and 35.85%, respectively. Moreover, SGPMOS can extract the hole accumulated both under the gate oxide and in the P-shield region during the turn-on transient. This diminishes reverse displacement current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{G\_{}{\text {dis}}}{)}$ </tex-math></inline-formula> , contributing to low electromagnetic interference (EMI) noise. Simulation results demonstrate that, compared to pMOS IGBT, the SGPMOS IGBT achieves better controllability in peak turn-on current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {max}}{)}$ </tex-math></inline-formula> and turn-on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{d}{I}_{C}/\text{d}{t}$ </tex-math></inline-formula> , featuring a 52.75% lower maximum reverse recovery <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{d}{V}_{\text {KA}}/\text{d}{t}$ </tex-math></inline-formula> for the same turn-on loss ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {on}}{)}$ </tex-math></inline-formula> .

A novel 3300 V trench IGBT with P-N-doped polysilicon split gate for low EMI noise

A novel 3300 V trench insulated gate bipolar transistor (IGBT) with p-n-doped polysilicon split gate (PNSG-IGBT) is proposed for low electromagnetic interference noise. The reverse-biased polysilicon PN junction is laterally depleted and charged by displacement current during the turn-off transient, which raises electrostatic potential in n-region of the polysilicon PN junction (V N) and electrostatic potential under the gate oxide (V ACC) simultaneously. By technology computer aided design simulation, during the turn-on transient, the maximum dV ACC /dt is 57.1% lower than that of the split gate (SG)-IGBT with the same R G and the excess V GE overshoot caused by reverse displacement current is effectively suppressed. Moreover, for the same E ON, the maximum reverse recovery dV KA /dt of the freewheeling diode can be reduced by 77.3% and 30.7% compared with that of the floating P region-IGBT and the SG-IGBT respectively, which is of great merit in suppressing dV/dt noise. Consequently, the PNSG-IGBT shows less common-mode noise at high frequency, especially in the range of 20–40 MHz.

Low Loss and Low EMI Noise CSTBT With Split Gate and Recessed Emitter Trench

A novel carrier stored trench bipolar transistor (CSTBT) with split gate (SG) and recessed emitter trench (SGRET CSTBT) is proposed. The proposed device features a SG structure with thicker oxide layer under the trench gate and recessed trench emitter, respectively. Compared with the conventional CSTBT with recessed emitter trench (RET CSTBT), the proposed device not only significantly reduces the gate-collector capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C} _{\mathrm{ GC}}$ </tex-math></inline-formula> ) but also alleviates the negative impact of the heavily doped n-type carrier stored layer on the breakdown voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BV</i> ). Simulation results show that with the similar <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BV</i> of about 650V, the on-state voltage drop ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\mathrm{ ceon}}$ </tex-math></inline-formula> ) at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${J} _{\mathrm{ ce}}$ </tex-math></inline-formula> =200A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for the proposed SGRET CSTBT is only 1.11V, which is 0.19V lower than that of the conventional RET CSTBT. Moreover, compared with the conventional RET CSTBT, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C} _{\mathrm{ GC}}$ </tex-math></inline-formula> at the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\mathrm{ ce}}$ </tex-math></inline-formula> of 25V, total gate charge ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q} _{\mathrm{ G}}$ </tex-math></inline-formula> ) and miller plateau charge ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q} _{\mathrm{ GC}}$ </tex-math></inline-formula> ) for the proposed device are reduced by 84.3%, 38.6% and 51.6%, respectively. As a result, the trade-off relationship between the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\mathrm{ ceon}}$ </tex-math></inline-formula> and turn-off loss ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E} _{\mathrm{ off}}$ </tex-math></inline-formula> ) as well as trade-off relationship between the turn-on loss ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E} _{\mathrm{ on}}$ </tex-math></inline-formula> ) and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{d}{V} _{\mathrm{ ak}} / \text{d}{t}$ </tex-math></inline-formula> of the free-wheeling diode (FWD) are significantly improved for the proposed device. At the same <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\mathrm{ ceon}}$ </tex-math></inline-formula> of 1.16V, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E} _{\mathrm{ off}}$ </tex-math></inline-formula> is reduced from 9.2mJ/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of the conventional one to 3.3mJ/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of the proposed device. At the same <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E} _{\mathrm{ on}}$ </tex-math></inline-formula> of 8.3mJ/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{d}{V} _{\mathrm{ ak}} / \text{d}{t}$ </tex-math></inline-formula> of FWD for the proposed device is reduced by 24.5% compared with that of the conventional RET CSTBT, which significantly suppresses the EMI noise.

The TAIPEI Rectifier—A New Three-Phase Two-Switch ZVS PFC DCM Boost Rectifier

A new, three-phase, two-switch, power-factor-correction (PFC) rectifier that can achieve less than 5% input-current total harmonic distortion (THD) and features zero-voltage switching (ZVS) of all the switches over the entire input-voltage and load ranges is introduced. The proposed rectifier also offers automatic voltage balancing across the two output capacitors connected in series, which makes it possible to use downstream converters designed with lower voltage-rated component that offer better performance and are less expensive than their high-voltage-rated counterparts. In addition, the proposed rectifier also exhibits low common-mode EMI noise. The performance of the proposed rectifier was evaluated on a 2.8-kW prototype with a 780-V output that was designed to operate in 340-520-VL-L, RMS input-voltage range.

Transient current build-up ZVS converter using control of synchronous switch

A new synchronous switch controlled transient current build-up zero voltage switching (TCB-ZVS) forward converter is proposed. The proposed converter is suitable for low-voltage and high-current applications. The features of the proposed converter are low conduction loss of magnetising current, no additional circuit for the ZVS operation, high efficiency, high power density and low EMI noise throughout all load conditions.