Low Dynamic Power Research Articles

Low Power Dynamic and Asymmetric Inductive Wireless Power Transfer System to an Endoscopic Capsule

Low Power Dynamic and Asymmetric Inductive Wireless Power Transfer System to an Endoscopic Capsule

Survey on Power and Area efficient FIR Filter Architecture in Digital Encephalography System

In the process of Electroencephalogram (EEG) acquisition, the electrical signals from the brain are contaminated by numerous noise sources and artifacts. American Clinical Neurophysiology Society recommends digital filtering of acquired EEG signals with an upper cut-off frequency of 70 Hz before display in digital encephalography systems. We propose a linear symmetrical FIR filter architecture for filtering EEG signals using approximate computation techniques. Approximate computation techniques result in lower hardware resources and lower power consumption with some compromise in quality. Software tools used for this study include MATLAB (and its FDA tool) and Xilinx ISE 14.7. The chosen target platform is the Spartan-3e starter FPGA board. We propose the architecture for an Approximate Dadda Tree Multiplier. The proposed approximate multiplier consumes 25% lesser slices and 35.18% lower dynamic power than state-of-the-art approximate multipliers. The proposed FIR filter consumes 19.77% lesser LUTs and 34.97% lower power than state-of-the-art symmetric FIR filter architectures.

Power and area efficient FIR filter architecture in digital encephalography systems

In the process of Electroencephalogram (EEG) acquisition, the electrical signals from the brain are contaminated by numerous noise sources and artifacts. American Clinical Neurophysiology Society recommends digital filtering of acquired EEG signals with an upper cut-off frequency of 70 Hz before display in digital encephalography systems. We propose a linear symmetrical FIR filter architecture for filtering EEG signals using approximate computation techniques. Approximate computation techniques result in lower hardware resources and lower power consumption with some compromise in quality. Software tools used for this study include MATLAB (and its FDA tool) and Xilinx ISE 14.7. The chosen target platform is the Spartan-3e starter FPGA board. We propose the architecture for an Approximate Dadda Tree Multiplier. The proposed approximate multiplier consumes 25% lesser slices and 35.18% lower dynamic power than state-of-the-art approximate multipliers. The proposed FIR filter consumes 19.77% lesser LUTs and 34.97% lower power than state-of-the-art symmetric FIR filter architectures.

New Zero Power Memristor Emulator Model and Its Application in Memristive Neural Computation

We present here a simple three P-type MOSFET-based grounded memristor emulator model. The model is designed to achieve zero static power dissipation and is done so by eliminating the external DC supply i.e., no DC bias. The proposed memristor emulator model has extremely low dynamic power dissipation as well which comes to around 175 nW i.e., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim ~67\%$ </tex-math></inline-formula> improvement compared to recent work. A mathematical analysis is carried out to present the relevance of this design. Simulations were done on Cadence Virtuoso 90 nm technology node and fingerprints of the proposed memristor emulator were obtained. The layout area occupied by the model is approx <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1154.69~\mu \text{m}^{2}$ </tex-math></inline-formula> and an external capacitor is connected to add tunability to the circuit. Furthermore, Monte Carlo and corner analysis validate the robust nature of the design. Besides, simulations have been experimentally verified using CD-4007 CMOS integrated circuit (IC) to make the design practically feasible. Furthermore, the design offers advantages such as extremely less overall power consumption and smaller chip area that could possibly pave the path for fabrication using standard CMOS technologies. At last, an application of the proposed model depicting in-memory computation through a memristor emulator crossbar array is presented in brief.

Energy Efficient and Low dynamic power Consumption TCAM on FPGA

Artificial Intelligence [AI] and networking applications extensively incorporate Field Programmable Gate Arrays [FPGA] - based Ternary Content Addressable Memories [TCAM]. Since FPGAs cannot support TCAMs, they must be emulated with SRAM-based memories, requiring FPGA resources. Compared to state-of-the-art designs, the proposed FPGA-based TCAM implementation will save significant resources. This methodology makes use of the Lookup Table RAMS (LUTRAMs), slice carry-chains, and flip-flops (FF) allowing simultaneous mapping of rules and deeper pipelining respectively. The TCAM implementation results in lower power consumption, lesser delays, and lower resource utilization. It outperformed conventional FPGA-based TCAMs in terms of energy efficiency (EE) and performance per area (PA) by at least 3.34 and 8.4 times respectively, and 56% better than existing FPGA designs. The proposed method outperforms all previous approaches due to its low dynamic power consumption when considering the huge size of TCAM emulation on SRAM-based FPGAs.

Low Power Trellis Coded Modulation (TCM) Decoder by Using Modified Resource Sharing Method for IoT Enabler

This paper proposes a new pre-computation approach based on the auxiliary trellis of the TCM decoder's ACSU (add compare select unit). The suggested method is based on pre-computation of path metrics and resource sharing of the ACSU unit. The Viterbi decoder itself is a power-consuming module of the communication system that comprises the TMU (transition metric unit) and ACSU (add compare select unit). By applying the suggested method, the authors would be able to achieve low dynamic power. The TCM decoder designed accordingly shows better SER/ BER results in comparison to the existing techniques. The 4D 8 PSK TCM encoder and decoder were implemented as per the design specifications given by consultative committee for space data system (CCSDS) for satellite applications. The simulations results are observed on 100 Mbps data for 8PSK modulation and the ¾ code rate of the TCM encoder. The results based on the new method show improved power-speed ratio with improved SER and BER.

FinFET-based 11T sub-threshold SRAM with improved stability and power

ABSTRACT This paper presents a single-ended 11T sub-threshold SRAM (SE11T) based on 10-nm FinFET technology. The performance of the proposed design is evaluated and compared with those of other state-of-the-art SRAMs namely 6T, 8T, DIRP10T, ST2, PPN10T, and FC11T at VDD = 0.3 V. The proposed design improves read stability by 2.08X/1.31X/1.03X compared to 6T/ST2/PPN10T due to the read-decoupling technique. Furthermore, it improves writability by 1.42X/2.85X/1.35X/1.28X compared to 6T/DIRP10T/ST2/PPN10T owing to feedback-cutting scheme. The use of write bitline free structure make the proposed SRAM consumes at least 2.79X lower dynamic power. The static power is reduced in the proposed SRAM by at least 1.09X. The reduction is because of the stacking of the transistors, the long path from power VDD to ground, and eliminated leakage in read path. The proposed SRAM works reliably even when exposed to extreme process variations. The proposed bitcell occupies a 1.46X/1.19X higher area than that of 6T/8T. The proposed design improves most of the design metrics and can be an efficient candidate for portable applications with budgeted power.

Inkjet‐Printed, Deep Subthreshold Operated Pseudo‐CMOS Inverters with High Voltage Gain and Low Power Consumption

AbstractOxide electronics has received increasing research and industrial attention in recent years. Solution‐processed/printed thin film transistors (TFTs) have rapidly matured to challenge its organic counterparts. However, when the n‐type oxides can demonstrate high mobility band transport, the performance of the p‐type ones is still weak. Consequently, examples of all‐oxide circuits are rare in the literature. Here printed amorphous indium‐gallium‐zinc oxide (a‐IGZO) based all‐oxide pseudo‐CMOS inverters, ring oscillators, and static random access memories (SRAMs), where the doping density and the device aspect ratio‐controlled deep‐subthreshold region offers sharp switching of the input signal is shown. For example, the signal gain (η) of pseudo‐CMOS 2T and 4T inverters is recorded as 285 and 329, respectively. Furthermore, the deep subthreshold operation ensures low dynamic power consumption, only few tens of nanowatts up to 1.5 V supply voltage. The inverters have demonstrated rail‐to‐rail swing up to 30 kHz and the 3‐stage ring oscillators recorded oscillation frequency of 6.7 kHz. The SRAM devices have shown satisfactory noise margins at HOLD‐, READ‐, and WRITE‐states, while their transient response is also recorded. These fully‐printed all‐oxide TFTs and circuits can be of large interest in portable/wearable electronics, display backplanes, interfacing circuits for sensors, etc.

A Minimal Buffer Router with Level Encoded Dual Rail-Based Design of Network-on-Chip Architecture

Asynchronous NOCs are most prominent in present SOC designs, due to their low dynamic power consumption, modularity, heterogeneous nature, and robustness to the process variations. Though asynchronous designs are proved efficient over synchronous counterparts, they have some severe drawbacks when area and speed are considered, due to complex handshake control circuits which increase the static power loss. Quasidelay insensitive (QDI) class of asynchronous NOCs based on 2-phase encoding is proved beneficial for speed and throughput enhancement but with complex design. The work has introduced lightweight minimal buffer router based on LEDR encoding to design a low power, high speed with compact NOC architecture. Then, minimal buffer router with FSM-based arbiter and priority assigner block is designed to enhance the speed, power, and area. This proposed work achieves zero dynamic power consumption with a total power consumption of less than 0.082 W with a router latency of 0.8 ns.

Design and investigation of stability‐ and power‐improved 11T SRAM cell for low‐power devices

AbstractThe modern system‐on‐chips require stable and low‐power SRAM cells due to technology scaling and limited sources of energy. Therefore, a stability‐ and power‐improved 11T SRAM cell is proposed in this study. The proposed cell core is composed of a strong cross‐coupled structure of a conventional inverter with a N‐type stacked transistor and a Schmitt‐trigger (ST) with a double channel‐length pull‐up network. This coupled with a separate read path enhances the read static noise margin (RSNM). Moreover, a feedback‐cutting N‐type transistor is placed inside the cell core to improve the write static noise margin (WSNM)/write margin (WM). Though the presence of stacked transistors in access paths increases read delay (TRA)/write delay (TWA), it reduces leakage. This metric further minimizes with the aid of a stacked structure of latch core and double channel‐length of pull‐up transistor in the ST inverter. The moderate read/write frequency and single‐ended structure of the suggested cell result in low dynamic power. Simulated results by using 16‐nm CMOS at VDD = 0.7 V show that the proposed cell has the second‐best RSNM/WSNM, which is 4.65/1.44 times higher than that of the fully differential 8T (FD8T) cell, as the basic cell. Moreover, it reduces leakage power by at least 2.01 times and consumes moderate read/write power, nearly 1.44/1.81 times lower than that of FD8T cell, at the cost of 1.61 times area overhead. The proposed cell can eliminate read/write‐half‐select‐disturbance issues to support bit‐interleaving architecture to increase soft error immunity.

Impact of Low Dynamic Logic Power SoCs on Energy Optimizing Techniques

Impact of Low Dynamic Logic Power SoCs on Energy Optimizing Techniques

A 2.63 μW ECG Processor With Adaptive Arrhythmia Detection and Data Compression for Implantable Cardiac Monitoring Device.

An ultra-low power ECG processor ASIC (application specific integrated circuit) with R-wave detection and data compression is presented, which is designed for the long-term implantable cardiac monitoring (ICM) device for arrhythmia diagnosis. An adaptive derivative-based detection algorithm with low computation overhead for potential arrhythmia recording is proposed to detect arrhythmia with the occasional abnormal heart beats. In order to save as much as possible cardiac information with the limited memory size available in the ICM device, a hierarchical data buffer structure is proposed which saves 3 types of data, including the raw ECG data segments of 2 seconds, compressed ECG data segments of 45 seconds, and R-peak values and interval lengths of >2000 beat cycles. A modified swinging-door-trending (SDT) method is proposed for the ECG data compression. The ASIC has been implemented based on fully-customized near-threshold standard cells using the thick-gate transistors in 65-nm CMOS technology for low dynamic power consumption and leakage. The ASIC core occupies a die area of 1.77 mm2. The measured total power is 2.63 μW, which is among the ECG processors with the lowest core power consumption. It exhibits a relatively high positive precision rate (P+) of 99.3% with a sensitivity of 98.2%, in contrast to the similar designs in literature with the same core power consumption level. Also, an ECG data compression ratio (CR) of up to 17.0 has been achieved, with a good trade-off between the compression efficiency and loss.

Numerical Investigation of the Stability and Spintronic Properties of Selected Quaternary Alloys

The use of electronic charge and spins (spintronics) has been proposed for much better data storage. This class of material is believed to have excellent capability for data integrity, low dynamic power consumption and high-density storage that showcases excellent protection against data loss. The spintronic and related properties have been investigated on four newly proposed quaternary alloys (NbRhGeCo, NbRhGeCr, NbRhGeFe and NbRhGeNi) through the first-principles calculation method of the Density Functional Theory (DFT). Specifically, the phonon frequencies, elastic stabilities, and the electronic structure were systematically studied in the full Heusler structure. The results predict that NbRhGeFe and NbRhGeCr are elastically and structurally stable. Both NbRhGeFe and NbRhGeCo are half-metals with ferromagnetic character, but NbRhGeCo is unfortunately elastically unstable. NbRhGeCr and NbRhGeNi are non-magnetic metallic alloys in their spin channels. All the results predict NbRhGeFe to be the only suitable among all the four alloys for spintronic application.

A compact time-to-amplitude converter for single-photon time-of-flight measurement

This work proposes a compact time-to-amplitude converter (TAC) for single-photon time-of-flight (TOF) measurement. Based on the principle of current mirror integration, the regulated cascode output structure is used to improve the integration linearity. Fabricated in 180 nm standard CMOS technology, the test results show that the proposed TAC achieves an integral nonlinearity of less than 1.1 LSB, and a timing resolution of 78 ps in a full-scale range (FSR) of 20 ns. Moreover, the readout voltage only varies by 1% during 1 ms hold-off time. The simple circuit structure make TAC occupy a small area of 120 µm2 and consume low dynamic power of 36.8 µW. The TOF measurement error is less than 5.2 cm, and the measurement precision is up to 1.61 cm at 150 cm. The presented TAC provides a compact implementation solution to realize high-density TOF sensors.

Fast OMP algorithm and its FPGA implementation for compressed sensing‐based sparse signal acquisition systems

Compressed sensing-based radio frequency signal acquisition systems call for higher reconstruction speed and low dynamic power. In this study, a novel low power fast orthogonal matching pursuit (LPF-OMP) algorithm is proposed for faster reconstruction of sparse signals from their compressively sensed samples and the reconstruction circuit consumes very low dynamic power. The searching time to find the best column is reduced by reducing the number of columns to be searched in successive iterations. A novel architecture of the proposed LPF-OMP algorithm is also presented here. The proposed architecture is implemented on field programmable gate array for demonstrating the performance enhancement. Computation of pseudoinverse in OMP is avoided to save time and storage requirement to store the pseudoinverse matrix. The proposed design incorporates a novel strategy to stop the algorithm without consuming any extra circuitry. A case study is carried out to reconstruct the RADAR test pulses. The design is implemented for K = 256, N = 1024 using XILINX Virtex6 device and supports maximum of K/4 iterations. The proposed design is faster, hardware efficient and consumes very less dynamic power than the previous implementations of OMP. In addition, the proposed implementation proves to be efficient in reconstructing low sparse signals.

A Time-to-Amplitude Converter With High Impedance Switch Topology for Single-Photon Time-of-Flight Measurement

This paper presents a novel time-to-amplitude converter (TAC) for single-photon direct time-of-flight (d-TOF) measurement. An innovative high impedance switch approach is proposed to significantly improve the stability of the integral current and to increase the swing of the timing voltage, enabling high linearity together with low power consumption on TAC. Implemented in a standard $0.18~\mu \text{m}$ CMOS technology, the TAC occupies only an area of $100~\mu \text{m}^{2}$ , featuring a compact configuration. The experimental results indicate that the presented TAC can acquire a 78 ps timing resolution in a 20 ns full-scale range (FSR) under the supply of 1.8 V. In particular, the TAC gains an excellent linearity characteristic with the very low differential nonlinearity (DNL) and integral nonlinearity (INL) within ±0.1 LSB and ±0.15 LSB, respectively. Additionally, the extremely low dynamic power consumption of $20~\mu \text{W}$ and the high pixel fill factor of 16 % are also achieved simultaneously. Thanks to the outstanding advantages of high-performance and compactness, the proposed TAC may be a promising candidate to realize high-density compact TOF-based imagers.

A Multi-Class Objects Detection Coprocessor With Dual Feature Space and Weighted Softmax

A critical mission for mobile robot vision is to detect and classify different objects with low power consumption. In this brief, a multi-class object detection coprocessor is proposed by using the Histogram of Oriented Gradient (HOG) and Local Binary Pattern (LBP) together with a weighted Softmax classifier. Its architecture is compact and hardware-friendly suitable for energy-constrained applications. Firstly, the cell-based feature extraction unit and block-level normalization reuse the SRAMs for storing one-row cell and one-row block. Meanwhile, the working frequency of the feature extraction and block-normalization unit is synchronized to the image sensor for low dynamic power. Then, a block-level one-time sliding-detection-window (OTSDW) mechanism is developed for partial classification with scalable object size. Finally, the Softmax classifier, which is implemented by the look-up table, linear fitting methods, and the fixed-point number, is tested in the Fashion MNIST dataset to evaluate its performance in multi-class classification problems and it reached an accuracy of over 86.2% with 10,180 parameters. The experimental result shows that the hardware-resource usage of the FPGA implementation is capable of 60 fps VGA video with 80.98 mW power consumption. This method uses similar or even fewer hardware resources than that of previous work using only the HOG feature and single-class classifier.

Low-energy complementary ferroelectric-nanocrack logic

Abstract Ferroelectric-based electronic devices have excellent low-energy characteristics due to the highly insulating property, in which the Joule heating can be neglected. The recent discovery of electrically switchable cracks in ferroelectric/alloy film heterostructure gave rise to a new way to construct transistor, where the opening and closing of crack switched the channel current off and on. Here, we observed the complementary switching of cracks for the first time, and demonstrated a complementary inverter without any additional process to set different types of transistors, which was implemented by forming the n- and p-type transistor in conventional complementary metal oxide semiconductor (CMOS) technology. The complementary states were generated spontaneously once the cracks were induced and varied with the change of applied input voltage polarity. The low ON resistance and near-zero OFF state leakage current result in the high current on/off ratio (~107) and allow for the low dynamic and static power dissipation. Further, the switching of cracks is coupled to the surrounding ferroelectric polarization states, offering the non-destructive readout operation. We believe that our work provides a very simple route to build complementary logic gates and paves a way for the energy-efficient electronic devices, while promoting the “crack nanoelectronics”.

Multi-mode nanoFETs: From low power to high performance on demand

Dynamic power management at the lowest design level of electronic hardware, i.e. at the device or transistor level, is still a novelty. Instead, energy saving is usually achieved at the circuit level by switching off high performance components and activating low leakage transistors in the current paths. We discuss here performance projections of field-effect transistors providing multiple power modes. A multi-mode (mm) FET can be configured from GHz performance to ultralow leakage by adjusting the charge injection into the transistor channel between thermionic and band-to-band tunnel injection. Nanodevices with ultrathin doping-free channels are the enabler of this novel device concept that requires excellent electrostatic control of the charge type and density. Moreover, nanomaterials with charge carriers of low effective mass will improve the mode tuning of mmFETs. TCAD simulations show that the device current can be switched through nine orders of magnitude at a supply voltage of . The mmFET can also operate in a low dynamic power mode with reduced drive currents but delay times that still allow sub-MHz operation. These properties make mmFETs a promising technology for low power circuitry supplied only by energy harvesters. The possibility to further decrease the supply voltage by integrating a ferroelectric layer in the capacitor stack is also addressed.

Design of power tester for HPLC power line carrier communication module

The current equipment used to test the power consumption of power line carrier communication modules not only has low dynamic power consumption, but also fails to meet the accuracy requirements for AC power tests. Based on a careful analysis of the key technologies of the dynamic power test of the communication module, this paper designs a power tester. This paper introduces the working principle of the power tester, discusses the corresponding circuit design scheme from two aspects of DC power consumption and AC power consumption, and analyzes the calculation methods of the two in detail. Finally, the test results of each test system are compared and analyzed. The power tester can achieve higher accuracy data testing.