Low-dropout Regulator Research Articles

A 65-nm CMOS Self-Supplied Power Management System for Near-Field Wirelessly Powered Biomedical Devices

This paper proposes a self-supplied power management system to efficiently rectify and regulate the AC voltage received from wireless power transmission techniques to power or recharge biomedical devices. The proposed power management system comprises three integrated functional units, namely, a fully cross-coupled rectifier, a self-biased reference voltage, and a capacitor-less low-dropout regulator (LDO). To reduce the current complexity of designing capacitor-less LDOs, a new architecture based on a pair of diode-connected transistors at the load of the LDO is devised which alleviates the need for a large load capacitor. The proposed power management system is implemented in a 65-nm CMOS process with an active chip area of 0.0810 mm2. Experimental results indicate that this system is capable of rectifying an AC signal up to 5 V at a frequency of 6.78 MHz. This rectified signal is then regulated to a fixed DC voltage of 1.75 V, while the load current can vary between 0 and 75 mA, with a maximum voltage dropout of 170 mV. Advantageously, the proposed power management system is significantly robust to temperature, as a 55 °C change in ambient temperature leads to only a 9% degradation in its overall performance. Furthermore, the ability of the power management system to drive low-power consumer electronics is demonstrated, and its superiority is evidenced by a performance comparison with the latest integrated power management systems presented in the literature.

Heterogeneous Integration of Monolithic LED-PD With Circuitry for Intensity Stabilization

The monolithic integration of a photodiode (PD) to a light-emitting diode (LED) enables the on-chip monitoring of light output intensity from the emitter. The light output intensity from the LED, which would fluctuate and degrade over time, can be stabilized with the aid of a driver circuit that reads the photocurrent from the on-chip PD as a feedback signal. Previous demonstration of such systems, implemented with feedback driver circuits built with microcontroller boards or analog circuit assembled on printed circuit boards (PCBs), showed that the intensity can be stabilized to within 0.03%, albeit with dimensions disproportionate to the LED-PD chip itself. A simplified circuit consisting of a transimpedance amplifier (TIA), proportional-integral (PI) controller and a low-dropout (LDO) regulator is heterogeneously integrated with the LED-PD as a system-in-package (SiP), making use of bare dies for the majority of components. Using this approach, the entire system is shrunk to a dimension of 4 mm × 5 mm, which is comparable to the size of the LED-PD chip. The reduced footprint facilitate practical applications of the LED-PD devices for intensity-stabilized lighting or displays. The stability is further improved to 0.01% on average over one-hour periods based on the on-chip PD photocurrent, while the power efficiency is improved to over 70%.

Low-Cost LED Driver Based on a Low-Dropout Current Regulator Combined With a Quasi-Resonant Buck Preregulator

Low-Cost LED Driver Based on a Low-Dropout Current Regulator Combined With a Quasi-Resonant Buck Preregulator

Relative Stability Analysis of Multi-Loop Low Dropout Regulators Using a Sub-Loop Superposition Method

Circuit designers favor open-loop stability analysis, which finds a breaking point in phase margin (PM) simulation. However, the conventional open-loop based method may not suit a multi-loop system that has multiple potential breaking points. It is unclear which breaking point is correct, or whether a correct breaking point exists. In this work, we first define “relative stability” from the worst stable sub-system of the original closed-loop system, and use it as a “reference”. Then, we examine and discuss the limitations of the conventional open-loop based method for a multi-loop system. The conventional method only indicates the “absolute stability” if the system has no common touching point. Subsequently, we propose a Sub-loop Superposition method for such a system, analyzing the “relative stability” in an open-loop way. We use the proposed method in two multi-loop low dropout regulators. The obtained PMs match the “reference”, verifying the effectiveness of the proposed method.

A Low Noise Neural Recording Frontend IC With Power Management for Closed-Loop Brain-Machine Interface Application.

Brain-machine Interface (BMI) with implantable bioelectronics systems can provide an alternative way to cure neural diseases, while a power management system plays an important role in providing a stable voltage supply for the implanted chip. a prototype system of power management integrated circuit (PMIC) with heavy load capability supplying artifacts tolerable neural recording integrated circuit (ATNR-IC) is presented in this work. A reverse nested miller compensation (RNMC) low dropout regulator (LDO) with a transient enhancer is proposed for the PMIC. The power consumption is 0.55 mW and 22.5 mW at standby (SB) and full stimulation (ST) load, respectively. For a full load transition, the overshoot and downshoot of the LDO are 110 mV and 71 mV, respectively, which help improve the load transient response during neural stimulation. With the load current peak-to-peak range is about 560 μA supplied by a 4-channel stimulator, the whole PMIC can output a stable 3.3 V supply voltage, which indicates that this PMIC can be extended for more stimulating channels' scenarios. When the ATNR-IC is supplied for presented PMIC through a voltage divider network, it can amplify the signal consisting of 1 mVpp simulated neural signal and 20 mVpp simulated artifact by 28 dB with no saturation.

A MOSFET subdivision, MOSFET-only subthreshold voltage and current reference for LDO applications

This paper proposes a MOSFET-only voltage and current reference circuit, which can simultaneously provide a 2 V reference voltage and 300 nA reference current. This design is mainly used in a low-power Low-Dropout Regulator (LDO) project, after simulation verification, which works well in LDO applications. The circuit is performed by SMIC.18 CMOS technology and simulation with the Cadence platform, with different threshold voltage MOSFET circuit design. The whole circuit works in the subthreshold area, and the overall circuit consists of the start-up circuit, the current reference circuit, the voltage reference circuit, the MOSFET subdivision circuit, and the current mirror output circuit. The circuit has the characteristics of high precision and low power consumption, with a layout size of only 0.015 mm2. Under a temperature range of -30 to 70 °C and a power voltage of 3.3 V, the simulation and post-simulation temperature coefficients (TC) of the circuit are 5.4 ppm/°C and 19.4 ppm/°C, respectively. The post-simulation output reference voltage at room temperature is 2.0008 V, and the working power voltage within the circuit error range is 3.2 V to 3.4 V. Excluding the current mirror output circuit part of the Current-Quiescent (IQ) being 530 nA, the power consumption is 1.75 μW when the supply voltage is 3.3 V, and the design goal is reached.

A 540-mA, 0.0487-ps-FOM Digital LDO based on Bi-directional Binary Search with Dual-loop Control

A dual-loop digital low-dropout regulator based on the bi-directional binary search method is implemented in a 0.18-μm CMOS process in this paper. To improve the transient response, a bi-directional successive approximation register without initialization is proposed in coarse loop. To speed up fine adjustment during heavy loads, a two-dimensional MOSFET array is adopted to improve fine regulation step. Simulation results demonstrate that, during load current steps between 540 mA and 40 mA, the undershoot/overshoot is 364 mV/161 mV, and the digital LDO settles within 210 ns. For a supply voltage of 1.4 V with 200 mV dropout, the current efficiency is as high as 99.99% and the figure of merit is as low as 0.0487 ps.

A Monolithically Integrated Low-Dropout Regulator Based on a-InGaZnO TFTs With Ultralow Power Consumption

A Monolithically Integrated Low-Dropout Regulator Based on a-InGaZnO TFTs With Ultralow Power Consumption

A Double-Edge-Triggered Digital LDO with Built-In Adaptive VCO Clock for Fast Transient Response and Low Power Consumption

A double-edge-triggered digital low dropout regulator (DLDO) is proposed with a built-in adaptive voltage-controlled oscillator (VCO) clock (AVC) for a system-on-chip (SoC) application. To achieve a fast transient response, the main comparator generates the comparison result at the rising edge of the AVC, and this result is sampled by the coarse or fine bidirectional shifter register at the falling edge of the AVC. Furthermore, the clock frequency can be boosted from 8 MHz at the steady state to 50 MHz by the AVC when the output current suffers from a sudden change, and it can also be adjusted in real-time according to the output voltage, which avoids the oscillation phenomenon and decreases the power consumption during the recovery process. To further lower the power consumption, the self-clock comparator replaces the conventional static comparator in the transient detector. The post-simulation results show that the proposed DLDO consumes a quiescent current of 95.13 μA in the steady state, and drives a maximum load current of 25 mA at the supply power of 0.6 V with an active area of 0.053-mm2 in a 180 nm CMOS process. When the load current jumps from 0.5 mA to 25 mA at the edge of 100 ps, the undershoot voltage and overshoot voltage are only 335 mV with the recovery time of 2.7 μs and 47.6 mV with the recovery time of 2.1 μs at the total on-chip capacitor of 50 pF, respectively, resulting in two competitive figures of merits (FoMs) than the previous works.

A Capacitorless LDO Regulator with Fast Feedback Loop and Damping-Factor-Control Frequency Compensation

A fast feedback loop (FFL) based on comparators is proposed in this paper. The FFL improves the transient response characteristics of the output-capacitorless low-dropout (OCL-LDO) regulator. When the load current switches between 1 mA and 100 mA with 1 μs edge time, the overshoot and undershoot are 33 mV and 37 mV, respectively, and recovery time is 1.2 μs and 1.6 μs, respectively. A damping-factor-control (DFC) frequency compensation circuit is used to ensure the stability of the OCL-LDO, and the simulation results show that the phase margin exceeds 50 degree in the entire load variation range. This design is based on 180 nm process, and the area of the chip is 0.068 mm2 (without pads). A band-gap reference circuit is also designed in this work; its output voltage is 1.2 V and its temperature coefficient is 7.96 ppm/∘C. The input voltage range of the proposed OCL-LDO is 2.5 V to 5 V with a linear regulation rate of 0.128 mV/V and a load regulation rate of 0.0017 mV/mA. In addition, the load range of the proposed OCL-LDO is 0 mA to 100 mA, and the minimum required external capacitance is 0 F. The power supply rejection ratio (PSRR) is −46 dB @ 1 kHz.

A 13.5-nA Quiescent Current LDO With Adaptive Ultra-Low-Power Mode for Low-Power IoT Applications

This brief presents a low-dropout regulator (LDO) for power-efficient Internet of Things (IoT) devices. When IoT devices are in low-power standby mode, the proposed LDO senses the load current and enters an ultra-low-power mode to enable an extremely low-power system. The proposed LDO alternates between two modes of operation. One is the ultra-low-power mode in which the core circuit of the LDO is turned off to save power, and the other is an active mode in which all circuit components are on. The successful operation of the proposed scheme is demonstrated by implementing and measuring silicon LDO chips, resulting in an extremely low-quiescent current of 13.5 nA and a superior figure-of-merit (FOM).

Hybrid low-dropout voltage regulator designed with TFET-MOSFET nanowire technologies

In this work, hybrid low-dropout voltage regulators (LDO) designed with a tunnel field-effect transistor (TFET)-MOSFET nanowire (NW) technologies are presented. The devices were modeled using Verilog-A with lookup tables based on experimental data of NW-TFETs and NW-MOSFETs fabricated in the same silicon vertical process flow. In all LDOs, the amplifier devices were biased with the same gm/I D = 9.5 V−1 for a maximum load current/capacitance of 1 mA/1 nF. In the hybrid regulators, the power transistors are designed with NW-MOSFETs to deliver the high load current, while the other devices are implemented with NW-TFET to provide high gain and low power consumption. Due to different onset voltages, two hybrid LDOs are proposed, one with symmetrical onset voltages implemented with a voltage shift (Hybrid-ΔV LDO) and one with a level-shift stage using the real characteristics of the devices (Hybrid-LS LDO). The hybrid circuits were compared to LDOs designed using only NW-TFETs and with only NW-MOSFETs. The Hybrid-ΔV LDO presents the best loop gain (62 dB) with a low quiescent current (7 nA), while the Hybrid-LS LDO shows a good gain-bandwidth product (700 Hz). In the transient analysis, the hybrid circuits showed a settling time close to the NW-MOSFET LDO but with higher undershoot/overshoot values in the case of a load transient. As demonstrated, the use of hybrid projects with TFET-MOSFET NW technologies enable LDOs with ultra-low power consumption and high loop gain, that are presented on TFET circuits and with a frequency response equivalent of MOSFET circuits.

A Low-Power Capacitorless LDO Regulator with Transient Enhancement Structure

In this paper, a portable low-power low dropout regulator (LDO) with no output capacitance has been designed in 0.18-[Formula: see text]m CMOS technology. In this paper, a PMOS power transistor is used and combined with an overshoot and undershoot suppression circuit to improve the transient response of the circuit. A modified Class-AB operational transconductance amplifier (OTA) is used to reduce power consumption and act as an error amplifier to eliminate low frequency poles. At the same time, a super source follower and a Miller capacitor are used for frequency compensation of the system. Finally, the system can provide a stable voltage for a load step from 0.2 to 25[Formula: see text]mA in 500[Formula: see text]ns edge-time for 140[Formula: see text]pF-load capacitance. The test results show that the circuit achieves a good voltage regulation rate and high transient response.

A wide input voltage range, high power supply rejection low‐dropout regulator with a closed‐loop charge pump for sensor front‐end circuits

SummaryThis paper presents a low dropout regulator (LDO) with a wide input voltage range and high power supply rejection (PSR) for Hall sensor front‐end circuits, which is fabricated with a 0.18 μm BCD process. A topology in which a closed‐loop charge pump biases the gate of two‐stage cascode NMOS pass transistors is proposed to increase immunity to electromagnetic interference (EMI) capability for automotive applications. Furthermore, a power‐down protection circuit is proposed to maintain the reliability of the system, and a novel implementation of the charge pump unit is presented to improve the influence of the body effect. Detailed derivation regarding the analyses of the simplified small‐signal model of the closed‐loop charge pump, the loop stability, and the PSR at various frequency bands is given. Simulation and measurement results show that the proposed LDO can operate with the input voltage from 5 to 40 V, providing up to 60 mA current drive capability, and its minimum operating voltage is 2.5 V with a 10 mA load capacity. Moreover, results verify that measured PSR is better than −45 dB at 1.5 kHz, and measured PSR is better than −30 dB at 15 MHz. The results confirm that the obtained parameters of line and load regulations are significantly improved to 1.86 mV/V and 1.75 mV/mA, respectively.

A Self-Triggered Digitally Assisted Hybrid LDO with 110 ns Settling Time in 65 nm CMOS

This article presents a self-triggered digitally assisted hybrid low-dropout regulator (LDO). The proposed architecture uses an analog LDO for steady-state operation and a digital LDO to track large output current changes. The dual loop has a loop controller for coherent operation, and the digital loop is only triggered when there is a large load step. Therefore, the proposed LDO inherits some of the advantages of both parts. It achieves a high power supply rejection ratio (PSRR) from the analog part. The digital loop has a faster settling time and consumes less static power than the analog loop. In this design, the maximum load is 200 mA. For heavy load conditions, PSRR is −40 dB at 1 MHz. The quiescent current is 200 μA. The undershoot/overshoot with the corresponding settling time measured under a load current step of 200 mA/10 ns are 82 mV/89 ns and 112 mV/110 ns, respectively. The proposed LDO achieves a competitive 4.48 ps figure of merit. In the TSMC 65 nm process, the active area is approximately 0.027 mm2.

Dynamically controllable current reference technique for current-feedback low dropout regulator

This paper proposes the dynamically controllable current reference (DCCR) technique for a wide input range, transient enhancement current-feedback low dropout regulator (WTELDO) to achieve transient enhancement. Combined with a transient enhanced current mirror (TE-CM) adopting an enhanced active resistance network, this technique which is designed based on dynamic bias improves the slewing rate of the power transistor gate but also increases the loop bandwidth. Finally, this WTELDO can reduce the minimum input voltage due to the current-feedback technique and improve the transient response under the condition of maintaining low quiescent current. This designed WTELDO was fabricated in SMIC 0.18μm CMOS process. The input voltage range is 0.8–2.2 V. The output voltage is 0.64 V. The maximum load current is 50 mA and the static current consumption is about 26 μA. Its maximum current efficiency is up to 99.948%. The test results show that the overshoot is 117.5 mV and the undershoot is 167.5 mV when the load current is switched between 0 mA and 50 mA within 300 ns under a 100 pF load capacitor.

Programmable 1 A ultra-low dropout LDO regulator for high-resolution camera sensors

In this article, design and realization of a high-performance linear low dropout regulator (LDO) capable of supplying 1 A of output current, designed and fabricated in 180 nm BCD technology of STMicroelectronics company, is described. The main purpose of this device is providing a stable output voltage for supplying high-resolution sensors of cameras in cellphones. The LDO is equipped with a big N-channel power transistor allowing an ultra-low dropout voltage around 50 mV at the maximal load current of 1 A even with a very low level of the output voltage of only 0.4 V. These features make the device suitable as a block following buck switching converters. Emphasis has been laid on assuring 1% accuracy of the output voltage across full temperature range and line and load conditions, very low quiescent current around 32 μA, necessary for battery powered applications such as cellphones, good transient response and a high power supply rejection ratio (PSRR) of more than 85 dB at 1 kHz. This combination of high-level parameters stands for an extraordinary device. The proposed LDO is a programmable device which means that the output voltage (up to 100 voltage versions in total) and other functions can be set via post-package electrical trimming. Last but not least, an efficient design for testability (DFT) is implemented in order to reduce the failed parts to a very low level, guaranteeing the highest quality level needed in the market.

Design of Destruction Protection and Sustainability Low-Dropout Regulator Using an Electrostatic Discharge Protection Circuit

In terms of sustainable power semiconductors, the embedding of an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) is an important aspect. In order for the semiconductor circuit to operate continuously or stably, a sufficient protection circuit against external surges must be configured. The purpose of this thesis is not only to effectively operate the low-dropout (LDO) regulator according to the load current, but to also secure high reliability against ESD situations by embedding an ESD protection circuit at the IC level. Moreover, the existence and nonexistence of an ESD protection circuit at the IC level is directly related to reliability. The proposed LDO regulator has high reliability against ESD situations using an embedded silicon controlled rectifier (SCR)-based ESD protection circuit in the I/O clamp and power clamp. The results revealed that the LDO regulator can not only effectively control the output voltage according to the load current, but it can also stably maintain the output voltage against the ESD surge. Moreover, the proposed LDO regulator with an embedded ESD protection circuit implemented in a 0.13 μm BCD process maintained an undershoot voltage of 21 mV and overshoot voltage of 19 mV for a load current of 300 mA.

A novel on-chip linear and switching mixed regulation against power analysis attacks

On-chip voltage converters such as low drop-out (LDO) regulators are capable of generating fast and scaled voltage levels against power analysis attacks (PAAs) due to the high bandwidths of feedback loops. Unfortunately, LDO regulators suffer from much power loss when they are utilized for outputting scaled voltage levels. In contrast, buck converters may achieve high power conversion efficiencies but are unable to generate output voltage with fast scaling patterns. In this paper, a novel hybrid voltage regulator that is consist of an LDO regulator and a buck converter connected in parallel is proposed to address the issues related with security against PAAs and power loss. The LDO regulator offers fast scaled voltage levels while the buck converter provides major load current. The result shows that the measurement-to-disclosure (MTD) value of a cryptographic circuit (CC) with the proposed hybrid voltage regulator maintains over 2 million with a 4.3% power loss.

Low-Voltage LDO Regulator Based on Native MOS Transistor with Improved PSR and Fast Response

In this paper, a low-voltage low-dropout analog regulator (ALDO) based on a native n-channel MOS transistor is proposed. Application of the native transistor with the threshold voltage close to zero allows elimination of the charge pump in low-voltage regulators using the pass element in a common drain configuration. Such a native pass transistor configuration allows simplification of regulator design and improved performance, with supply voltages below 1 V, compared to commonly used regulators with p-channel MOS transistors. In the presented design of ALDO regulator in 180 nm CMOS X-FAB technology, an output voltage of 0.7 V was achieved with an output current of 10 mA and a supply voltage of 0.8 V. Simulation results show that despite the low supply voltage, output voltage spikes do not exceed 70 mV at the worst technology corner when output current transients from 100 µA to 10 mA. Under such conditions, stable operation and power supply rejection PSR = 35 dB were achieved with an output capacitance of 0–500 pF. The proposed regulator allows to push the limit of ALDO regulator applications to voltages below 1 V with only slight degradation of its performance.