Low Dropout Linear Regulator Research Articles

Total ionization dose and electromagnetic pulse synergistic effects on low dropout linear regulator

As a power management chip widely used in various electronic systems, the low dropout regulator (LDO) plays a crucial role in the normal operation of electronic systems. Ionizing radiation and electromagnetic pulse (EMP) radiation can cause interference and damage to the LDO, posing risks to the proper functioning of electronic systems in large-scale scientific devices. In this study, through separate experimental investigations on the Total Ionizing Dose (TID) effects, EMP effects, and synergistic effect of the LDO, it was found that parameters such as the LDO output voltage decreases with increasing irradiation dose, with more severe degradation observed under grounded bias. The EMP effects mainly cause oscillations in the LDO output voltage and a slight increase in its mean value. The results of the synergistic effect experiments indicate that there is a certain synergistic interaction between the TID effects and the EMP effects. The synergistic effects lead to an increase in the amplitude of the oscillations and changes in the mean value of the output voltage.

Design of an Embedded Test Bench for Organic Photovoltaic Module Testing

In this article, a multipurpose embedded system for testing organic photovoltaic modules is presented. It is designed to include all the features for real-time monitoring, data acquisition, and power conversion based on a Ćuk converter, providing useful data for scientific investigation of the outdoor operation of organic photovoltaic modules. The embedded system allows both the scan of the I–V curve and the continuous operation of the organic photovoltaic module, such as at its maximum power. Voltage and current at the terminals of the organic photovoltaic module under test and up to four temperatures are continuously measured and stored on a Secure Digital card. The communication interface allows the embedded system to connect with other instruments, such as irradiance sensors, with digital serial output. The embedded system is designed both for laboratory and in-the-field use: it can be powered either by the AC electrical grid or a battery, which can also operate as a backup battery. Galvanic isolation divides the embedded system into the field-side and the logic-side functional sections, providing improved noise immunity and safe operation. The main power distribution system within the embedded system is a +9 V bus; ultra-low-noise linear low dropout regulators provide the +3.3 V and +5 V regulated voltages to supply the analog and digital circuits within the logic-side section, and a flyback converter supplies the field-side section of the board. The proposed embedded solution is validated using an experimental setup built at SolarTechLab, Politecnico di Milano. The experimental results report the feasibility of the proposed embedded system.

Noise Aware Fully Integrated Low Power and Low Inrush Current Fast Transient Response LDO

The complexity of Systems-on-Chip (SoC) designs necessitates robust linear regulator architectures to ensure stable operations and efficient power management in modern devices. In response to this demand, low-dropout (LDO) voltage regulators have emerged as a focal point for their scalability and superior performance across diverse application domains. This paper proposes an LDO linear regulator characterized by high power supply rejection ratio (PSR) and rapid transient response. The design of this LDO emphasizes low power consumption and minimal inrush current while incorporating advanced techniques to enhance PSR and stability across varying frequencies. Despite its compact footprint and low-power profile, this LDO achieves remarkable PSR across a broad spectrum of frequencies. To achieve swift transient response, the proposed design integrates variable biasing and transient boost capacitance. The variable bias structure enhances the slew rate and PSR of the LDO, contributing to its overall performance optimization. Additionally, the strategic placement and utilization of transient-boost capacitance leverage its voltage characteristics to bolster transient response without introducing additional quiescent current, thereby further enhancing circuit stability.

Ultra-low power low-dropout linear regulator with a load current tracking bias current generator for loT devices

This paper presents an ultra-low power low-dropout (LDO) linear regulator with a load current tracking bias current generator (BCG). The proposed LDO employs the load current tracking BCG to achieve stable and ultra-low power operation. The measurement results demonstrated that the proposed LDO produced a 1.2 V output and achieved 78 nA quiescent current, 145 mV mA−1 load regulation, and 2.2 mV V−1 line regulation.

Programmable 1 A ultra-low dropout LDO regulator for high-resolution camera sensors

In this article, design and realization of a high-performance linear low dropout regulator (LDO) capable of supplying 1 A of output current, designed and fabricated in 180 nm BCD technology of STMicroelectronics company, is described. The main purpose of this device is providing a stable output voltage for supplying high-resolution sensors of cameras in cellphones. The LDO is equipped with a big N-channel power transistor allowing an ultra-low dropout voltage around 50 mV at the maximal load current of 1 A even with a very low level of the output voltage of only 0.4 V. These features make the device suitable as a block following buck switching converters. Emphasis has been laid on assuring 1% accuracy of the output voltage across full temperature range and line and load conditions, very low quiescent current around 32 μA, necessary for battery powered applications such as cellphones, good transient response and a high power supply rejection ratio (PSRR) of more than 85 dB at 1 kHz. This combination of high-level parameters stands for an extraordinary device. The proposed LDO is a programmable device which means that the output voltage (up to 100 voltage versions in total) and other functions can be set via post-package electrical trimming. Last but not least, an efficient design for testability (DFT) is implemented in order to reduce the failed parts to a very low level, guaranteeing the highest quality level needed in the market.

Design of a LDO with High PSRR

One of the common ways to increase the PSRR(power supply rejection ratio) of LDO (low dropout linear regulator) is increasing the gain of error amplifier, but the stability of LDO system will also be reduced. A new high gain error amplifier is designed to push the poles inside the amplifier away from the origin, which ensures the stability of LDO system and improves the PSRR of low frequency band. At the TT process corner, the range of adjustable output voltage of LDO is 1.361~1.860 V under the simulation condition of 27 °C. When power supply ranges from 2.3 V to 3.3 V, the linear regulation rate is 238.3 µV/V; When the load changes from 0 to 20 mA, the load regulation rate is 9.6 µV/mA; At load current of 20 µA, the power supply rejection ratio of LDO is -97 dB@dc, and the phase margin of the whole circuit is greater than 66 degrees. The chip is verified in a 0.18 µm CMOS process. Setting the power supply voltage in the range of 2.3 to 3.3 V, the output voltage is stable at 1.8 V, and the error is only 1.9 mV, which is less than 0.2%.

Fully Integrated 1.8 V Output 300 mA Load LDO with Fast Transient Response

Based on an 0.18 μm process, this paper proposes a fully integrated 1.8 V output 300 mA load low-dropout linear regulator (LDO) with a fast transient response. By inserting a transient-enhanced biased Class AB super source follower at the gate of the output power transistor, this LDO can quickly adjust the gate voltage of the power transistor without additional power consumption. By adding an active capacitor circuit composed of a fast comparator with offset voltage at the output point, this LDO can quickly charge/discharge the transient current and accelerate the transient response without reducing the circuit stability. Simulation results show that the proposed LDO has an output voltage of 1.8 V, when the input voltage is 2 V to 5 V while consuming 66.4 μA of quiescent current. The proposed capless LDO has a 1.94 µV/mA load regulation, a 0.55 mV/V linear regulation, and a −60 dB@1 kHz power supply rejection. When the load current steps from 3 mA to 300 mA in 300 ns, the LDO settles in 400 ns with an overshoot and undershoot of 67 mV and 86 mV, respectively.

Design and Simulation of Low Dropout, Low Power Capless Linear Voltage Regulator

This paper demonstrates a low power, frequency compensated with on-chip capacitor, low dropout linear voltage regulator. The proposed low dropout regulator (LDO) delivers a constant output voltage of 2.4[Formula: see text]V for an input range of 2.5–6.8[Formula: see text]V. A minimal drop of 2[Formula: see text]mV and 20[Formula: see text]mV was observed at no load and full load output current of 0 A to 100[Formula: see text]mA, respectively. LDO is realized by a high-gain two-stage error amplifier, internally compensated by passive a high-pass filter to achieve stability over a load current range of 0–100[Formula: see text]mA without occupying as much area as an active high-pass filter. The LDO presented requires a bias current of 10[Formula: see text]mA with a reference voltage of 1.5[Formula: see text]V and is designed in 180-nm technology.

Design of a Wide Input Voltage Low Quiescent Current LDO

A low-dropout linear regulator (LDO) with wide input voltage range, wide output voltage range and low quiescent current power consumption is proposed, which is applied to the switching power supply chip to power the internal module of the switching power supply chip. The low-dropout linear regulator is based on a P-type PowerFET design consisting of an error amplifier, a Bandgap reference. The circuit was designed and implemented by SMIC 0.18um BCD process, simulated and verified using Spectre software. The simulation results show that the linear regulation is 0.04mV/V in the input voltage range of 3.5-30V, and the load regulation is 1mV/mA in the output load current range of 10uA to 10mA, and the quiescent current is only 10uA.

A Novel ON-State Resistance Modeling Technique for MOSFET Power Switches

Nowadays, electronic circuits’ time to market is essential, with engineers trying to reduce it as much as possible. Due to this, simulation has become the main testing concept used in the electronics domain. In order to perform the simulation of a circuit, a behavioral model must be created. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are semiconductor devices found in a multitude of electronic circuits, and they are also used as power switches in many applications, such as low-dropout linear voltage regulators, switching regulators, gate drivers, battery management systems, etc. A MOSFETs’ behavior is extremely complex to model, thus, creating high-performance models for these transistors is an imperative condition in order to emulate the exact real behavior of a circuit using them. An essential parameter of MOSFET power switches is the ON-state resistance (RDSON), because it determines the power losses during the ON state. Ideally, the power losses need to be zero. RDSON depends on multiple factors, such as temperature, load current, and gate-to-source voltage. Previous studies in this domain focus on the modeling of the MOSFET only in specific operating points, but do not cover the entire variation range of the parameters, which is critical for some applications. For this reason, in this paper, there was introduced for the first time a novel ON-state resistance modeling technique for MOSFET Power Switches, which solves the entire RDSON dependency on the transistor’s variables stated above. The novel RDSON modeling technique is based on modulating the transistor’s gate-to-source voltage such that the exact RDSON value is obtained in each possible operating point. The method was tested as a real-life example by creating a behavioral model for an N-channel MOSFET transistor and the chosen simulation environment was Oregon, USA, Computer-Aided Design (OrCAD) capture. The results show that the model is able to match the transistor’s RDSON characteristics with a maximum error of 0.8%. This is extremely important for applications in which the temperatures, voltages, and currents vary over a wide range. The new proposed modeling method covers a gap in the behavioral modeling domain, due to the fact that, until now, it was not possible to model the RDSON characteristics in all operating corners.

Design of a high-voltage resistant and highly reliable LDO for automotive applications

This paper presents a high reliability low dropout linear regulator with high voltage tolerance, which uses an open loop structure and is applied to the feedforward response portion of the power tube gate to enhance the transient response of the LDO. The proposed LDO is simulated using a 0.18um DTI isolated BCD process with a 3.3V-14V supply voltage, a maximum input voltage of 40V and an adjustable output voltage of 3.1V/5V. The line regulation is 0.086% at 40V high voltage input and the supply voltage rejection ratio of the circuit can be maintained at around 60dB.

An Ultra-Low Power Fast Transient LDO with Dynamic Bias

A low-dropout linear regulator (LDO) without external capacitors is designed, combining ultra-low power consumption and ultra-fast transient response. The common support voltage of the LDO is 2.5 V to 3.6 V with a stable output voltage of 1.2 V and an output current dynamic range of 10 μA to 20 mA to supply power to other circuit modules. A Rail-to-Rail Input-Output (RRIO) Class AB push-pull output amplifier and a dynamic bias circuit are also designed. Meanwhile, a dynamic bias circuit which can regulate the operating current of error amplifier is proposed by monitoring output voltage variation in order to provide a larger compensation current to the operational amplifier when the load current changes are at high frequency and maintain ultra-low operating current at low clock frequency. The LDO is designed without resistors, and the deep well NMOS is applied in the output stage in order to reduce the difficulty of loop compensation. Designed in a 180 nm CMOS process, the post-simulation results show that under the condition of 40 °C and 3 V input voltage, the static power consumption is 31.7 nA with a settling time (±5%) of less than 35 ns.

Compact Low-dropout Linear Regulator Design in 0.13 µm CMOS Technology for IoT Based Remote Infectious Disease Monitoring System

With the widespread adoption of the internet of things (IoT), power management of the different electronic (i.e. IoT) devices has become a major challenge. The low-dropout linear regulator (LDO) circuit is widely used for power management applications of electronic devices. This article reports the design and simulation of a low-dropout linear regulator (LDO) circuit, powered by a 1.2 V DC power supply voltage. In order to optimise the power dissipation, low layout silicon area and lower dropout voltage, a current mirror based transistor optimised LDO circuit has been implemented. The simulation results show that the proposed LDO regulator circuit exhibits a 582 mV low-dropout voltage, 1.568 mW power dissipation, and a very compact layout silicon area of 163.84 µm 2(12.795 × 12.805 µm). The proposed LDO linear regulator archi- tecture is designed and validated in 0.13 µm TSMC CMOS process technology using Mentor Graphic EDA tools.

ALDO2, a multi-function rad-hard linear regulator for SiPM-based HEP detectors

ALDO2 is a multi-function, adjustable, low dropout linear regulator designed in onsemi I3T80 0.35μm HV CMOS technology for use in HEP detectors that adopt silicon photomultipliers (SiPMs). The chip features four independent regulators, two low voltage channels (max 3.3 V) used to filter and stabilize the power supply of front-end chips, and two HV channels (max 70 V), specifically designed to provide the bias voltage to arrays of SiPMs. Each regulator can be independently shut down and is protected for over-current and over-temperature. The HV regulators also implement a circuit to monitor the bias current of the SiPM arrays, allowing to perform I–V curves and thus to fine-tune the working point of the SiPM arrays during the detector lifetime. The chip adopts radiation hardening techniques and has been fully qualified up to a TID of 20 Mrad, a 1-MeV-equivalent neutron fluence of 1015 cm−2, and with heavy ions up to 40 MeV cm2 mg−1 LET and 1010 cm−2 cumulative fluence. The chip will be installed in two CMS detectors in the HL-LHC phase, the Barrel Timing Detector (BTL) and the High Granularity Calorimeter (HGCAL).

Optimized Power Supply Rejection Ratio Modeling Technique for Simulation of Automotive Low-Dropout Linear Voltage Regulators

In the automotive domain, the vast majority of testing is performed through simulations, which can validate a system design before the actual implementation and can emphasize eventual faults in the design process. Hence, the simulation is of utmost importance. Behavioral models are necessary for the creation of each electronic device desired in the system, and some of the components have very complex behavior: low-dropout linear voltage regulators (LDOs), gate drivers, and switching regulators. In the automotive industry, LDOs are essential components because they power all the other subsystems and very accurate behavior is needed to make sure that the system behaves as in reality. LDO models are already commercially available and most of their intrinsic characteristics are modeled (dropout voltage, line regulation, load regulation, etc.). However, one characteristic that is extremely useful, yet the hardest to model, is the power supply rejection ratio (PSRR). This paper proposes a new PSRR modeling technique for automotive low-dropout voltage regulators. The new PSRR characteristic was modeled for an automotive LDO product in a Texas Instruments portfolio, which has a commercially available model, and was simulated using the PSpice Allegro simulator and the OrCAD Capture CIS environment.

The radiation tolerance of a low voltage LDO developed for the CMS HGCAL on-detector electronics system

The CMS detector will undergo the replacement of its current endcap calorimeter by a new high granularity calorimeter (HGCAL). The new HGCAL will need to withstand much higher radiation levels than the present endcaps. This poses tight requirements on the front-end electronics, including the powering chain. As part of this chain, a low-dropout linear regulator (LDO) has been designed and prototyped for post-regulation for HGCAL, providing extremely low noise and stable power to the analog front-end. We present results from tests of the LDO, including from a detailed irradiation campaign.

An Ultra-low Power Off Chip Capacitor-less LDO With High Transient Response

This paper presents a low-dropout linear regulator (LDO) with ultra-low power high transient response. This LDO adopts GAP-dynamic-bias circuit to achieve quiescent current as low as 242nA under 0-20mA load. A transient enhancement circuit based on window comparator is used to sense the output voltage change and further enhance the transient response. The circuit is designed and implemented using TSMC0.18um technology, and is verified by simulation using Spectre software. The simulation results show that when the load changes in the range of 10uA-20mA with a 1ns transition edge, the slowest overshoot and undershoot recovery times are only 2.36us and 2.15us. In the input voltage range of 2.5-3.6V, the linear regulation rate and load regulation rate are 0.479mV/V and 2.61nv/mA, respectively.

A novel 2.5 Gbps pre-transimpedance amplifier with the gain adaptively adjusted

A 2.5 Gbps transimpedance amplifier (TIA) with the feedback resistance self-adaptively adjusted is designed for the application of optical receivers in passive optical network and implemented in Global Foundries (GF) 0.18 [Formula: see text]m CMOS standard process. The main structure of the circuit consists of an improved three-stage current multiplexing push-pull inverter. With the diode-connected-transistor placed at each end of the inverter, the extra pole will be pulled away in order to increase the stability of the loop system. The feedback resistance of TIA is connected in parallel with the NMOS transistor, and the gate voltage of the tube is adjusted automatically to control the resistance value of this parallel structure in order to overcome the defect of the inverter which will work in the linear region on the condition of excessive optical power. A low-dropout linear regulator (LDO) is adopted from the power supply to the TIA to isolate power supply noise. The measured results demonstrate that the fabricated TIA with a photodetector capacitance of 3.2 pF has a transimpedance gain of 41.64 dB[Formula: see text] with a current signal frequency of 2.5 Gbit/s, and a −3 dB bandwidth of 2.35 GHz. The average input-referred noise current spectral density within the bandwidth is185 pA/Hz[Formula: see text], signal rise time is 195 ps, fall time is 227 ps, eye diagram height is 28 mV, optical sensitivity is −30.6 dBm, and power consumption is only 52 mW at 3.3 V power supply voltage, the chip area is [Formula: see text] mm2.

An RFID-Based Self-Biased 40 nm Low Power LDO Regulator for IoT Applications.

There are emerging applications, like bridge structural health monitoring, continuous patient condition and outdoor aiding of the elderly and the disabled, where Internet of things (IoT) nodes are used with very limited accessibility and no connection to the main supply network. They may also be exposed to harsh environmental conditions. These are applications where power and available area constraints are of great concern. In this paper, we design a 1.1 V low dropout (LDO) linear regulator in 40 technology to be embedded in IoT nodes. To address these constraints, we used state-of-the-art, variability-aware resistor-less sub-threshold biased CMOS-only ultra low power consumption configurations having low active area. The proposed LDO is internally compensated with embedded 18 Miller and 10 load capacitances. It can supply 1 maximum load current with 0.8 uA quiescent current. The dropout voltage of the regulator is 200 with minimum input voltage of 1.3 V. The efficiency of the regulator is 84%, which is about 99% of the maximum achievable efficiency for a 200 dropout voltage. The whole circuit, consisting of the embedded voltage reference and the Miller and load capacitances, takes less than 0.007 of the die size with 1 μ power consumption.

A Linear 0.98 mV Low-Dropout Voltage Regulator in 0.18-μm CMOS Technology

This paper presents a linear low-dropout (LDO) voltage regulator in 0.18-pm CMOS technology. The proposed LDO consists of voltage reference, error amplifier, pass device, output capacitor and resistive feedback network. A symmetrical operational transconductance amplifier (OTA) is implemented as an error amplifier and a PMOS transistor is used as a pass device to produce low dropout voltage and low quiescent current. The proposed design is simulated using Spectre simulator in Cadence software to verify its performances. The simulation results indicated that the LDO regulator achieves a regulated output voltage of 1.5 V with the ranges of supply voltage from 1.7 V to 2.0 V. The LDO regulator has a dropout voltage of 19.3 mV under maximum load current of 1.1 mA. The proposed LDO regulator is suitable for power management system.