Low-dropout Regulator Research Articles

Total ionization dose and electromagnetic pulse synergistic effects on low dropout linear regulator

As a power management chip widely used in various electronic systems, the low dropout regulator (LDO) plays a crucial role in the normal operation of electronic systems. Ionizing radiation and electromagnetic pulse (EMP) radiation can cause interference and damage to the LDO, posing risks to the proper functioning of electronic systems in large-scale scientific devices. In this study, through separate experimental investigations on the Total Ionizing Dose (TID) effects, EMP effects, and synergistic effect of the LDO, it was found that parameters such as the LDO output voltage decreases with increasing irradiation dose, with more severe degradation observed under grounded bias. The EMP effects mainly cause oscillations in the LDO output voltage and a slight increase in its mean value. The results of the synergistic effect experiments indicate that there is a certain synergistic interaction between the TID effects and the EMP effects. The synergistic effects lead to an increase in the amplitude of the oscillations and changes in the mean value of the output voltage.

A wideband high-PSR OCL LDO using a gain-relaxed OTA featuring dynamic complex zeros frequency compensation

This article proposes an Output-Capacitor-Less (OCL) Low-Dropout (LDO) regulator with an assisted positive feedback loop technique, which mimics a negative resistance, along with a single common-gate stage. Conventional techniques utilize multistage high-gain OTA to achieve a high DC loop gain. However, such an OTA suffers from high power consumption and sophisticated frequency compensation mechanisms. Instead, the use of a single-stage relatively low-gain OTA helps to extend the bandwidth. Then, the overall DC loop gain is maximized by the proposal of a novel negative resistance circuit. To further improve the PSR, a bulk-driven ripple canceling path that is insensitive to process corners is proposed making the LDO suitable for high-PSR applications. Stability is another challenge in the design of OCL LDOs due to its associated complex poles. We propose a new frequency compensation technique by introducing two complex zeros to eliminate these complex poles. Hence, the overall stability is improved. Since these complex poles location vary from light to heavy loads, the proposed zeros dynamically change accordingly. Besides, this suggested mechanism has been analyzed using the generalized time-and-transfer constants (TTCs) circuit analysis technique. Under heavy load conditions, the suggested LDO has attained phase and gain margins of 62.8° and 29 dB, respectively. Moreover, Monte Carlo simulations along with process and temperature variations have been investigated to prove the reliability of such a frequency compensation technique. The proposed LDO has been implemented in 65 nm CMOS technology node with a short pass transistor length of 100nm. The simulation results reveals that the LDO draws 299.4μA of quiescent current under light load conditions and 296.8μA under heavy load conditions (including the bandgap voltage reference). The suggested LDO functions at 1.2V supply voltage, delivers 0.93V output voltage and can handle a load current up to 10mA with load regulation of 17μV/mA, line regulation of 2.22mV/V, and PSR of −48.7dB at low frequencies. The PSR at 1MHz is at least −32.5dB which is superior to the reported recent LDOs.

A 600-mA Multifeedback Loop Capacitorless Low-Dropout Regulator With a –40-dB Power Supply Rejection at 1 MHz With 27.5-μA Quiescent Current Consumption

A 600-mA Multifeedback Loop Capacitorless Low-Dropout Regulator With a –40-dB Power Supply Rejection at 1 MHz With 27.5-μA Quiescent Current Consumption

An ADPLL-Based GFSK Modulator with Two-Point Modulation for IoT Applications.

To establish ubiquitous and energy-efficient wireless sensor networks (WSNs), short-range Internet of Things (IoT) devices require Bluetooth low energy (BLE) technology, which functions at 2.4 GHz. This study presents a novel approach as follows: a fully integrated all-digital phase-locked loop (ADPLL)-based Gaussian frequency shift keying (GFSK) modulator incorporating two-point modulation (TPM). The modulator aims to enhance the efficiency of BLE communication in these networks. The design includes a time-to-digital converter (TDC) with the following three key features to improve linearity and time resolution: fast settling time, low dropout regulators (LDOs) that adapt to process, voltage, and temperature (PVT) variations, and interpolation assisted by an analog-to-digital converter (ADC). It features a digital controlled oscillator (DCO) with two key enhancements as follows: ΔΣ modulator dithering and hierarchical capacitive banks, which expand the frequency tuning range and improve linearity, and an integrated, fast-converging least-mean-square (LMS) algorithm for DCO gain calibration, which ensures compliance with BLE 5.0 stable modulation index (SMI) requirements. Implemented in a 28 nm CMOS process, occupying an active area of 0.33 mm2, the modulator demonstrates a wide frequency tuning range of from 2.21 to 2.58 GHz, in-band phase noise of -102.1 dBc/Hz, and FSK error of 1.42% while consuming 1.6 mW.

A 640 nA IQ Output-Capacitor-Less Low Dropout (LDO) Regulator with Sub-Threshold Slew-Rate Enhancement for Narrow Band Internet of Things (NB-IoT) Applications.

An ultra-low quiescent current output-capacitor-less low dropout (OCL-LDO) regulator for power-sensitive applications is proposed in this paper. To improve the gain of the OCL-LDO feedback loop, the error amplifier employs a combination of a cross-coupled input stage for boosting the equivalent input transconductance and a negative resistance technique to improve the gain. Meanwhile, in order to address the issue of transient response of the ultra-low quiescent current OCL-LDO, a sub-threshold slew-rate enhancement circuit is proposed in this paper, which consists of a transient signal input stage and a slew-rate current increase branch. The proposed OCL-LDO is fabricated in a 0.18 μm CMOS process with an effective area of 0.049 mm2. According to the measurement results, the proposed OCL-LDO has a maximum load current of 100 mA and a minimum quiescent current of 640 nA at an input voltage of 1.2 V and an output voltage of 1 V. The overshoot and undershoot voltages are 197 mV and 201 mV, respectively, and the PSR of the OCL-LDO is -72.4 dB at 1 kHz when the load current is 100 μA. In addition, the OCL-LDO has a load regulation of 7.6 μV/mA and a line regulation of 0.87 mV/V.

Design of an Embedded Test Bench for Organic Photovoltaic Module Testing

In this article, a multipurpose embedded system for testing organic photovoltaic modules is presented. It is designed to include all the features for real-time monitoring, data acquisition, and power conversion based on a Ćuk converter, providing useful data for scientific investigation of the outdoor operation of organic photovoltaic modules. The embedded system allows both the scan of the I–V curve and the continuous operation of the organic photovoltaic module, such as at its maximum power. Voltage and current at the terminals of the organic photovoltaic module under test and up to four temperatures are continuously measured and stored on a Secure Digital card. The communication interface allows the embedded system to connect with other instruments, such as irradiance sensors, with digital serial output. The embedded system is designed both for laboratory and in-the-field use: it can be powered either by the AC electrical grid or a battery, which can also operate as a backup battery. Galvanic isolation divides the embedded system into the field-side and the logic-side functional sections, providing improved noise immunity and safe operation. The main power distribution system within the embedded system is a +9 V bus; ultra-low-noise linear low dropout regulators provide the +3.3 V and +5 V regulated voltages to supply the analog and digital circuits within the logic-side section, and a flyback converter supplies the field-side section of the board. The proposed embedded solution is validated using an experimental setup built at SolarTechLab, Politecnico di Milano. The experimental results report the feasibility of the proposed embedded system.

Design of High-Reliability Low-Dropout Regulator Combined with Silicon Controlled Rectifier-Based Electrostatic Discharge Protection Circuit Using Dynamic Dual Buffer

Overshoot and undershoot caused by the current load impact the accuracy of the required output voltage and circuit performance. The transient response issue in existing low-dropout (LDO) regulators is a dynamic specification that must be addressed at the design stage. This transient response is influenced by system parameters such as stability and gain. The LDO regulator suggested in this study is designed to minimize the change in output voltage by considerably enhancing the gain using a dynamic dual buffer structure. A dynamic dual buffer is utilized to effectively control undershoot and overshoot. Under the conditions that the input voltage range is from 3.3 to 4.5 V, the maximum load current is 300 mA, the output voltage is 3 V, and the output of the proposed LDO regulator with the dynamic dual buffer structure has undershoot and overshoot voltages of 41 mV and 31 mV, respectively. That is, the output voltage of the proposed LDO regulator effectively provided and discharged an additional current suited for the undershoot/overshoot conditions to enhance the transient response characteristics. Furthermore, the electrostatic discharge (ESD) robustness characteristics of the proposed LDO regulator improved because of the silicon-controlled rectifier underlying the ESD protection device embedded in the output node and power line.

A low dropout regulator design with 20.4 μA quiescent current and high power supply rejection

This paper presents a novel low dropout (LDO) regulator distinguished by its high power supply rejection (PSR) and low quiescent current. A capacitive feed-forward ripple cancellation (CFFRC) technique is introduced to effectively cancel power supply noise while simultaneously minimizing quiescent current. Additionally, the design incorporates feed-forward capacitors and back-to-back pseudo-resistors biasing to achieve reduced power consumption. Furthermore, the integration of negative feedback super source follower and Miller compensation techniques enhances the stability of the LDO. Fabricated using 180 nm CMOS technology, the LDO exhibits a quiescent current consumption of 20.4 μA. Experimental results demonstrate a maximal improvement of −41.55 dB in PSR compared to an LDO lacking these enhancements, with a maximum load current capability of 120 mA.

Noise Aware Fully Integrated Low Power and Low Inrush Current Fast Transient Response LDO

The complexity of Systems-on-Chip (SoC) designs necessitates robust linear regulator architectures to ensure stable operations and efficient power management in modern devices. In response to this demand, low-dropout (LDO) voltage regulators have emerged as a focal point for their scalability and superior performance across diverse application domains. This paper proposes an LDO linear regulator characterized by high power supply rejection ratio (PSR) and rapid transient response. The design of this LDO emphasizes low power consumption and minimal inrush current while incorporating advanced techniques to enhance PSR and stability across varying frequencies. Despite its compact footprint and low-power profile, this LDO achieves remarkable PSR across a broad spectrum of frequencies. To achieve swift transient response, the proposed design integrates variable biasing and transient boost capacitance. The variable bias structure enhances the slew rate and PSR of the LDO, contributing to its overall performance optimization. Additionally, the strategic placement and utilization of transient-boost capacitance leverage its voltage characteristics to bolster transient response without introducing additional quiescent current, thereby further enhancing circuit stability.

A power-efficient fast-transient OCL-LDO with adaptive super source follower and active capacitor compensation management

This paper presents a flipped voltage follower (FVF) based output-capacitor-less low-dropout regulator (OCL-LDO) with fast transient response, high power supply rejection (PSR), and low quiescent current for noise-sensitive circuits in internet-of-things (IoTs). An adaptive super source follower (ASSF) is proposed to effectively reduce the output impedance of the voltage buffer under heavy-loading conditions while keeping a low quiescent current under light-loading conditions. The active capacitor compensation management (ACCM) is proposed to solve the charge-sharing problem caused by the floating capacitors in the dynamic capacitor compensation circuit. The proposed OCL-LDO has been designed and fabricated in 22-nm CMOS technology. It can stabilize with load current ranging from 0 to 12 mA while consuming only 4.8-μA quiescent current. when the load current steps from 0.1 to 10 mA within 3.8 ns, the measured voltage undershoot is 55 mV and the recovery time is about 60 ns.

A 0.91-[formula omitted]A-quiescent-current capacitor-less LDO with sub-threshold transient enhancement and bulk-driven feed-forward supply ripple cancellation

This paper presents a capacitor-less low-dropout (OCL-LDO) regulator that features a low quiescent current for low power applications. To enhance the transient response of proposed OCL-LDO, a sub-threshold transient enhancement circuit including a transient signal input stage, a current subtractor, and a current amplifier is suggested. Meanwhile, a circuit made up of a bulk-driven ripple feed-forward circuit and a ripple introduction circuit is developed in order to improve PSR of the OCL-LDO. The proposed OCL-LDO is fabricated in 0.18 μm standard CMOS process and has an active area of 0.053 mm2. Based on measurement results, the proposed OCL-LDO has a maximum load current of 100 mA at 1.2 V input and 1 V output, and a minimum quiescent current of 0.91 μA. The overshoot voltage and undershoot voltage are 199 mV and 204 mV, respectively. PSR of the OCL-LDO is −71.8 dB at 1 KHz when the load current is 100 mA. Furthermore, the OCL-LDO exhibits a load regulation of 11.1 μV/mA and a line regulation of 1.05 mV/V.

A transient-enhanced output-capacitorless LDO regulator with non-inverting pull–push gain stage

A novel non-inverting pull–push gain stage output-capacitorless low-dropout regulator (OCL-LDO) is introduced, designed specifically for power management of system-on-chip (SoC). The incorporation of an innovative non-inverting gain stage (NIGS) serves to shift the non-dominant parasitic poles to higher frequencies, thereby enhancing the overall stability of the system. The proposed pull-push configuration markedly improves the slew rate limitation at the gate of the power transistor. Post-layout simulation outcomes, corroborated through a 180-nm CMOS fabrication process, indicate that the proposed LDO regulator maintains stability across a wide range of loading currents, from 0 mA to 100 mA, with a Miller compensation capacitance of only 3.5 pF. The circuit operates with a quiescent current of 143 μA when powered by a 1.5 V single supply. The LDO regulator boasts a dropout voltage of 300 mV, enabling it to deliver up to 100 mA of load current. Simulation results show that the undershoot voltage is only 63.7 mV when the load current jumps from 0 to 100 mA with edge of 100 ns, while employing a 100 pF capacitance load. The recovery time to return to equilibrium post this abrupt change is approximately 0.15 μs. The proposed OCL-LDO regulator exhibits a substantial enhancement in transient response compared to its predecessors, alongside a harmonized balance between line regulation and load regulation performance parameters.

A novel LDO circuit with high-speed current detection

Abstract This paper proposes a Low Dropout Regulator (LDO) circuit with high-speed current detection. The current detection circuit utilizes a latch-based structure to expedite comparisons and perform detection. Its primary objective is overcurrent protection in certain practical applications, achieving current limit functionality. The LDO circuit structure can stably provide a 5 V output voltage under a 9 V input voltage, with a maximum output current limit of 70 mA. In practical applications, the circuit can function with a load current of 40 mA, resulting in an output voltage (Vout) of 4.96 V. In the design of the LDO circuit, the Error Amplifier (EA) module departs from conventional internal structures, employing a dual-potential folded cascode common-gate common-source amplifier. This choice enhances parameters such as EA gain and Power Supply Rejection Ratio (PSRR). The gain achieves 98 dB, and the low-frequency PSR reaches 92 dB. Simultaneously, the dual potential configuration significantly economizes the layout area required in practical implementations. The LDO is designed using a 0.18 μm standard CMOS process.

An Output-Capacitorless LDO regulator with fast transient response and high PSRR

Abstract A fast transient response and high supply voltage rejection ratio (PSRR) output-capacitor-less low-dropout (OCL-LDO) regulator with a dual power transistor structure is proposed in this paper. The designed flip voltage follower (FVF) structure and the proposed back-gate control loop improve the transient performance of the system. The proposed PSRR enhancement circuit transmits the power supply voltage fluctuation 1:1 to the gate of the power transistor so that the influence of the power supply voltage fluctuation on the output voltage of the LDO is offset by the difference between the gate and source voltages of the power transistor. The simulated results have shown that the proposed OCL-LDO regulator achieves full range stability from 100 μA to 50 mA. The output voltage undershoot is reduced by more than 100 mV when the load current is stepped from 1 to 50 mA in 500 ns without the load capacitor. The PSRR enhancement circuit increases the PSRR of the LDO from 1 KHz to 10 MHz by more than 20 dB.

A Sub-1V High PSRR Bandgap Voltage Reference with Temperature Compensation for Low Dropout Regulator

A Sub-1V High PSRR Bandgap Voltage Reference with Temperature Compensation for Low Dropout Regulator

Capacitor-Less Low Dropout Regulator Development Research

Capacitor-Less Low Dropout Regulator Development Research

A Li-ion battery charger based on LDO regulator with pre-charge mode in 180 nm CMOS technology

This paper presents a novel Li-Ion battery charger that utilizes a low-dropout (LDO) regulator and incorporates four control modes: low constant current mode, pre-charge current mode, fast constant current mode, and constant voltage mode. The charger aims to meet specific criteria such as high precision, high efficiency, and small form factor. Through simulation results, the following specifications were obtained using a 1.8 V supply in a 0.18 μm complementary metal–oxide–semiconductor (CMOS) technology: a trickle current of 124.7 mA, a pre-charge current of 466.94 mA, a maximum charge current of 1.06 A, and a charge voltage of 4.21 V. The proposed charger demonstrates an efficiency of 92%.

An NMOS output-capacitorless low-dropout regulator with dynamic-strength event-driven charge pump

In this paper, an NMOS output-capacitorless low-dropout regulator (OCL-LDO) featuring dual-loop regulation has been proposed, achieving fast transient response with low power consumption. An event-driven charge pump (CP) loop with the dynamic strength control (DSC), is proposed in this paper, which overcomes trade-offs inherent in conventional structures. The presented design addresses and resolves the large signal stability issue, which has been previously overlooked in the event-driven charge pump structure. This breakthrough allows for the full exploitation of the charge-pump structure's potential, particularly in enhancing transient recovery. Moreover, a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage, leading to favorable static characteristics. A prototype chip has been fabricated in 65 nm CMOS technology. The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current (I Q) and can recover within 30 ns under 200 mA/10 ns loading change.

A high‐precision voltage reference with a curvature‐compensated bandgap for fluorescence detection

SummaryFluorescent optical fiber temperature sensors require accurate online temperature monitoring in hazardous environments with strong electromagnetic fields, high voltages, flammability, or explosiveness. This imposes stringent requirements on the temperature coefficient stability of the bandgap reference (BGR) circuit. To address these challenges, this paper proposes a high‐order curvature compensation bandgap reference (HCC_BGR) circuit fabricated using a 0.18‐μm bipolar‐CMOS‐DMOS (BCD) process. A traditional first‐order bandgap reference (TRA_BGR) circuit is also fabricated for comparison. Experimental results demonstrate that the proposed HCC_BGR circuit generates a stable 1.22‐V reference voltage with a low‐temperature coefficient of 5.56 ppm/°C from −20°C to 85°C. Compared to the TRA_BGR circuit, the HCC_BGR reduces the temperature coefficient by 3.07 times. Furthermore, the low‐dropout regulator (LDO) using the proposed HCC_BGR exhibits excellent line sensitivity of 1.52%/V from 3.4 to 5 V.

Ferroelectric Domain Wall Delayer and Low-Dropout Regulator.

A switching-type power converter providing an accurate and stable switching output voltage against line/load variations and power supply ripple is mostly complicated in system-on-chip power management integrated circuits (PMICs) within a limited occupation area. Here we fabricated domain wall (DW) nanodevices using an X-cut LiNbO3 thin film on silicon. The domain switching event occurs after a delay time predicted by Merz's law under the applied voltage. But the output current is irrespective of the applied voltage and can be adjusted by conducting wall width as well as input resistance in the circuit. The regulating currents appear repetitively across the volatile interfacial domains between the nanodevice and electrode under intermittently applied voltages. A wall-current-limited domain switching model is developed to explain the phenomenon. The multifunctional DW nanodevices with smaller occupation areas can serve as compact low-dropout regulators in PMICs, time-domain delayers in energy-efficient neural network systems, and on-chip electrostatic discharge protection besides nonvolatile memories and selectors.