Abstract
An ultra-low quiescent current output-capacitor-less low dropout (OCL-LDO) regulator for power-sensitive applications is proposed in this paper. To improve the gain of the OCL-LDO feedback loop, the error amplifier employs a combination of a cross-coupled input stage for boosting the equivalent input transconductance and a negative resistance technique to improve the gain. Meanwhile, in order to address the issue of transient response of the ultra-low quiescent current OCL-LDO, a sub-threshold slew-rate enhancement circuit is proposed in this paper, which consists of a transient signal input stage and a slew-rate current increase branch. The proposed OCL-LDO is fabricated in a 0.18 μm CMOS process with an effective area of 0.049 mm2. According to the measurement results, the proposed OCL-LDO has a maximum load current of 100 mA and a minimum quiescent current of 640 nA at an input voltage of 1.2 V and an output voltage of 1 V. The overshoot and undershoot voltages are 197 mV and 201 mV, respectively, and the PSR of the OCL-LDO is -72.4 dB at 1 kHz when the load current is 100 μA. In addition, the OCL-LDO has a load regulation of 7.6 μV/mA and a line regulation of 0.87 mV/V.
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