Fast transient low‐dropout regulator with undershoot and settling time reduction technique

Abstract

This article proposes an external capacitor-less low-dropout (LDO) regulator with undershoot and settling time reduction technique for fast transient response. In the proposed LDO, a feedback capacitor is applied instead of a complicated voltage-spike detection circuit to reduce undershoot voltage and settling time without consuming additional quiescent current. When an undershoot or overshoot voltage occurs in the load transient response, the undershoot voltage and settling time are reduced by increasing the gate discharging current or gate charging current of the pass transistor by the current flowing through the feedback capacitor. An adaptively biased single-stage error amplifier with a cross-coupled pair is used to improve stability without external capacitors at low quiescent current consumption. The proposed LDO regulator is implemented with a 0.18 μm CMOS process and consumes a quiescent current of 3.0 μA at a minimum load current of 0.1 mA. Compared with the conventional LDO regulator, the proposed LDO regulator reduces the undershoot voltage by 53.3% and the settling time by 55.5% without consuming additional quiescent current.