Low Dropout Linear Voltage Regulator Research Articles

Design and Simulation of Low Dropout, Low Power Capless Linear Voltage Regulator

This paper demonstrates a low power, frequency compensated with on-chip capacitor, low dropout linear voltage regulator. The proposed low dropout regulator (LDO) delivers a constant output voltage of 2.4[Formula: see text]V for an input range of 2.5–6.8[Formula: see text]V. A minimal drop of 2[Formula: see text]mV and 20[Formula: see text]mV was observed at no load and full load output current of 0 A to 100[Formula: see text]mA, respectively. LDO is realized by a high-gain two-stage error amplifier, internally compensated by passive a high-pass filter to achieve stability over a load current range of 0–100[Formula: see text]mA without occupying as much area as an active high-pass filter. The LDO presented requires a bias current of 10[Formula: see text]mA with a reference voltage of 1.5[Formula: see text]V and is designed in 180-nm technology.

A Novel ON-State Resistance Modeling Technique for MOSFET Power Switches

Nowadays, electronic circuits’ time to market is essential, with engineers trying to reduce it as much as possible. Due to this, simulation has become the main testing concept used in the electronics domain. In order to perform the simulation of a circuit, a behavioral model must be created. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are semiconductor devices found in a multitude of electronic circuits, and they are also used as power switches in many applications, such as low-dropout linear voltage regulators, switching regulators, gate drivers, battery management systems, etc. A MOSFETs’ behavior is extremely complex to model, thus, creating high-performance models for these transistors is an imperative condition in order to emulate the exact real behavior of a circuit using them. An essential parameter of MOSFET power switches is the ON-state resistance (RDSON), because it determines the power losses during the ON state. Ideally, the power losses need to be zero. RDSON depends on multiple factors, such as temperature, load current, and gate-to-source voltage. Previous studies in this domain focus on the modeling of the MOSFET only in specific operating points, but do not cover the entire variation range of the parameters, which is critical for some applications. For this reason, in this paper, there was introduced for the first time a novel ON-state resistance modeling technique for MOSFET Power Switches, which solves the entire RDSON dependency on the transistor’s variables stated above. The novel RDSON modeling technique is based on modulating the transistor’s gate-to-source voltage such that the exact RDSON value is obtained in each possible operating point. The method was tested as a real-life example by creating a behavioral model for an N-channel MOSFET transistor and the chosen simulation environment was Oregon, USA, Computer-Aided Design (OrCAD) capture. The results show that the model is able to match the transistor’s RDSON characteristics with a maximum error of 0.8%. This is extremely important for applications in which the temperatures, voltages, and currents vary over a wide range. The new proposed modeling method covers a gap in the behavioral modeling domain, due to the fact that, until now, it was not possible to model the RDSON characteristics in all operating corners.

Optimized Power Supply Rejection Ratio Modeling Technique for Simulation of Automotive Low-Dropout Linear Voltage Regulators

In the automotive domain, the vast majority of testing is performed through simulations, which can validate a system design before the actual implementation and can emphasize eventual faults in the design process. Hence, the simulation is of utmost importance. Behavioral models are necessary for the creation of each electronic device desired in the system, and some of the components have very complex behavior: low-dropout linear voltage regulators (LDOs), gate drivers, and switching regulators. In the automotive industry, LDOs are essential components because they power all the other subsystems and very accurate behavior is needed to make sure that the system behaves as in reality. LDO models are already commercially available and most of their intrinsic characteristics are modeled (dropout voltage, line regulation, load regulation, etc.). However, one characteristic that is extremely useful, yet the hardest to model, is the power supply rejection ratio (PSRR). This paper proposes a new PSRR modeling technique for automotive low-dropout voltage regulators. The new PSRR characteristic was modeled for an automotive LDO product in a Texas Instruments portfolio, which has a commercially available model, and was simulated using the PSpice Allegro simulator and the OrCAD Capture CIS environment.

A Dual Frequency Compensation Technique to Improve Stability and Transient Response for a Three Stage Low-Drop-Out Linear Regulator

A novel internal compensation technique named dual frequency compensation is proposed to improve the stability and the transient response of the on-chip output capacitor three stage low-drop-out linear voltage regulator (LDO). It exploits a combination of amplification and differentiation to sufficiently separate the dominant pole from the first non-dominant pole so that the latter is located after the unity gain frequency regardless of the load current value. The proposed LDO regulator is analyzed, designed, and simulated in standard 0.18 µm low voltage CMOS technology. The presented LDO regulator delivers a stable voltage of 1.2 V for an input supply voltage range of 1.35-1.85 V with a maximum line deviation of 4.68mV/V and can supply up to 150mA of the load current. The maximum transient variation of the output voltage is 54.5 mV when the load current pulses from 150mA to 0mA during a fall time of 1µs. The proposed LDO regulator has a low figure of merit compared with recent LDO regulators.

Total Dose Effects on Negative and Positive Low-Dropout Linear Regulators

Total ionizing dose (TID) functional failure analysis on positive and negative low-dropout linear voltage regulators is performed. Two parts have been chosen for this article: the LP2953 positive regulator and the LT1175 negative regulator. Different failure mechanisms are observed, which can be modeled with radiation-enabled SPICE simulations. The simulation results are shown to compare well with experimental data. Both voltage regulators contain three blocks, essential for accurate modeling: a bandgap reference, a power pass transistor, and an error amplifier. In this article, simulations were performed on each block independently to analyze the trends in parametric degradation after radiation exposure and describe the failure mechanisms. This article identifies the bandgap circuitry as the primary cause of failure for the negative regulator while degradations in all blocks contribute to the TID response of circuits.

Design of low quiescent current LDO voltage regulator for portable electronic devices

Low dropout linear voltage regulators are analog circuit blocksthat play an important role in power delivery process and prevent a system from fluctuations in the supply rails.There is a high demand on using LDO regulator in system-on-chip (SOC) applications, given their inherently noisy environment.This work presents a design of low dropout voltage regulator (LDO) to satisfy desiredparameters. Basic design parameters of the proposed LDO CMOS circuit are introduced. The proposed circuit is designedto achieve a low quiescent current and dropout voltage as well as large PSRR value as possible, while maintaining the stability is paramount.Simulation results of the proposed circuit using 180 nm process CMOS technology and its corner analysis are presented. The simulation of the proposed LDO design achieveslow quiescent current in the range of microamperes.

Fully integrated, low drop-out linear voltage regulator in 180 nm CMOS

This paper presents a capacitor-free low dropout (LDO) linear regulator based on a dual loop topology. The regulator utilizes two feedback loops to satisfy the challenges of hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes. The proposed design works without the need of a decoupling capacitor connected at the output and operates with a 0---100 pF capacitive load. The design has been taped out in a $$0.18\,\upmu \hbox {m}$$0.18μm CMOS process. The proposed regulator has a low component count, area of $$0.012\, \hbox {mm}^2$$0.012mm2 and is suitable for system-on-chip integration. It regulates the output voltage at 0.9 V from a 1.0---1.4 V supply. The measured results for a current step load from 250 to 500 $$\upmu \hbox {A}$$μA with a rise and fall time of $$1.5\,\upmu \hbox {s}$$1.5μs are an overshoot of 26 mV and undershoot of 26 mV with a settling time of $$3.5\,\upmu \hbox {s}$$3.5μs when $${C_L}$$CL between 0 and 100 pF. The proposed LDO regulator consumes a quiescent current of only $$10.5\,\upmu \hbox {A}$$10.5μA. The design is suitable for application with a current step edge time of 1 ns while maintaining $$\Delta V_{out}$$ΔVout of 64 mV.

Introduction to the special issue on “High performance analog circuits and design methodologies”

This special issue of the SPRINGER Journal of Analog Integrated Circuits and Signal Processing includes a special section composed of four papers related to ‘‘High performance analog circuits and design methodologies’’. They are selected among those presented at the Joint Conference of 4S-2014/2014 International Conference on Analog VLSI Circuits (AVIC 2014). This conference was jointly organized by Vietnam National University HCMC (VNU-HCM) Integrated Circuit Design Research and Education Center (ICDREC) and Institute of Electrical Engineers of Japan (IEEJ) as an event for commemorating the 20 anniversary of VNU-HCM and 10th anniversary of ICDREC. The conference is the successor of the former International Analog VLSI Workshop. Its purpose is to exchange information, ideas and recent research results on analog VLSI circuits and their applications. The first paper, ‘‘An Improvement of the Current– Voltage Conversion Technique in Over-Current Sensing Circuit for Low-Power Low Dropout Linear Voltage Regulators’’, by Ho Quang Tay, proposes a resistance-less over-current sensing circuit using current–voltage conversion technique for CMOS low dropout linear voltage (LDO) regulators with PMOS as pass device. The second paper, ‘‘Delta-Sigma DAC with Jitter-Shaper-Reducing Jitter Noise’’, by Yuki Watanabe et al., describes a novel delta-sigma digital-to-analog converter (DSDAC) using a jitter shaper to augment the noise caused by clock jitter. The third paper, ‘‘Design of a Symmetry-type Floating Impedance Scaling Circuits for a Fully Differential Filter’’, by Fujihiko Matsumoto et al., proposes the impedance scaling techniques in order to realize a small-size low frequency active filter. The final paper, ‘‘A Low-Power and Low-Gm Linear Transconductor Utilizing Control of a Threshold Voltage’’, by Takeshi Ohbuchi et al., proposes a linear transconductor that is realized by the scheme that the threshold voltages of the transistors are changed by the attenuated input voltage using body effect and reverse short-channel effect. On behalf of the editorial committee of this special section, we would like to express our great thanks to all the authors of the submitted manuscripts and all the reviewers for their great contribution and helpful effort. We also would like to thank all of the committee members for their valuable effort expended in this editorial work. Finally, we would like to express our special thanks to the Guest Editorial Secretary, Professor Cosy Muto, Nagasaki University and Professor Hiroo Sekiya, Chiba University, and the Advisor, Professor Takeshi Shima, Kanagawa University, for all their contributions and efforts.

An improvement of the current–voltage conversion technique in over-current sensing circuit for low-power low dropout linear voltage regulators

In this paper, a resistance-less over-current sensing circuit using current---voltage conversion technique for CMOS low dropout linear voltage (LDO) regulators with PMOS as pass device is proposed. The scheme of this over-current sensing uses the I---V conversion technique. This improvement results in an elimination of the body effect and reduces the deviation of the current limiter. The resulting current clamp value only varies from 190 to 250 mA when the supply voltage varies from 2.7 to 5 V. The total quiescent current of the LDO is 3.51 uA at the 5 V supply voltage. The current consumption of the over-current sensing circuit is about 1 uA.

Design Of A Low Voltage,Low Drop-Out (Ldo) Voltage Cmos Regulator

In this paper a low voltage, low drop-out (LDO) voltage regulator design procedure is proposed and implemented using 0.25 micron CMOS process. It discusses a 3 to 5V, 50mA CMOS low drop-out linear voltage regulator with a single compensation capacitor of 1pF. The experimental results show that the maximum output load current is 50mA and the regulated output voltage is 2.8V.The regulator provides a full load transient response with less than 5mV overshoots and undershoots. The active layout area is 358.28um × 243.30um.

Taking management to micro levels

The authors describe a 5 V power management system for Bluetooth and USB applications in 0.18 μm CMOS technology. It is based on a low-dropout linear voltage regulator. The system topology and operating princples are discussed.